CN204407332U - Display base plate - Google Patents
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- CN204407332U CN204407332U CN201520146239.XU CN201520146239U CN204407332U CN 204407332 U CN204407332 U CN 204407332U CN 201520146239 U CN201520146239 U CN 201520146239U CN 204407332 U CN204407332 U CN 204407332U
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Abstract
The utility model provides a kind of display base plate, belongs to display base plate technical field, and it can solve pixel electrode in existing array base palte easily in the problem of drain edge fracture.Display base plate of the present utility model comprises the first structure and the second structure; Described second structure has is located at the first structural clinch, and is positioned at the outer and main part be connected with clinch of the first structure; And described first structure has the thinning area that to be connected with its edge, in described thinning area, the thickness of the first structure is less than the thickness of the first structure outside thinning area; Described clinch is positioned on described thinning area at least partly; And the main part be positioned at least partly outside thinning area is directly connected with the clinch be positioned on described thinning area.
Description
Technical field
The utility model belongs to display base plate technical field, is specifically related to a kind of display base plate.
Background technology
Change in the array base palte of (ADS) pattern at senior super Wei Chang, for simplifying preparation technology, source region and source/drain electrode can be formed with in a patterning processes, in this case, pixel electrode is positioned at above source/drain electrode, and namely pixel electrode " overlap joint " is in drain electrode.
As shown in Figure 1, the thickness of 41 (with source electrode 42) of drain electrode is usually comparatively large, and about hundreds of micron, and pixel electrode 5 thinner thickness, only have some tens of pm.Therefore, as the angle of gradient comparatively large (for 90 degree in the figure) at drain electrode 41 edge, between pixel electrode 5 " overlap joint " part in drain electrode 41 (clinch 51) and the part (main part 52) being in outside drain electrode 41, easily rupture in drain electrode 42 edge (i.e. the joint of clinch 51 and main part 52), thus affect the function of array base palte.Certainly, also can comprise other known structure such as substrate 9, grid 1, gate insulation layer 2, active area 3, planarization layer 6, public electrode 7 in this array base palte, be not described in detail at this.
Utility model content
The utility model easily in the problem of drain edge fracture, provides a kind of display base plate not easily occurring to rupture for pixel electrode in existing array base palte.
The technical scheme that solution the utility model technical problem adopts is a kind of display base plate, and it comprises the first structure and the second structure; Described second structure has is located at the first structural clinch, and is positioned at the outer and main part be connected with clinch of the first structure; And
Described first structure has the thinning area that to be connected with its edge, and in described thinning area, the thickness of the first structure is less than the thickness of the first structure outside thinning area;
Described clinch is positioned on described thinning area at least partly; And the main part be positioned at least partly outside thinning area is directly connected with the clinch be positioned on described thinning area.
Preferably, described display base plate is array base palte, and described first structure is the drain electrode of thin-film transistor, and described second structure is pixel electrode.
Further preferably, described drain electrode is located on active area completely.
Preferably, described display base plate also comprises substrate, and the distance between described first structure and substrate is more than or equal to the distance between the main part of described second structure and substrate.
Preferably, described clinch covers whole thinning area.
Preferably, the part that overlapped portion, described thinning area covers comprises multiple sub-thinning area, and the thickness the closer to the first structure in the sub-thinning area of the first structural edge is less.
Preferably, the thickness of first structure of thickness outside thinning area of the first structure in described thinning area 1/2 to 2/3 between.
Accompanying drawing explanation
Cross-sectional view when Fig. 1 is the fracture of existing array base palte generation pixel electrode;
Fig. 2 is the cross-sectional view of the array base palte of embodiment of the present utility model;
Fig. 3 is the cross-sectional view in the array base palte preparation method of embodiment of the present utility model after forming photoresist layer;
Fig. 4 is the cross-sectional view in the array base palte preparation method of embodiment of the present utility model after photoresist layer being carried out to ladder exposure and development;
Fig. 5 is the cross-sectional view after being formed with source region in the array base palte preparation method of embodiment of the present utility model;
Fig. 6 is the cross-sectional view in the array base palte preparation method of embodiment of the present utility model after photoresist layer being carried out to first time ashing;
Fig. 7 is the cross-sectional view in the array base palte preparation method of embodiment of the present utility model after forming source electrode, drain electrode;
Fig. 8 is the cross-sectional view in the array base palte preparation method of embodiment of the present utility model after photoresist layer being carried out to second time ashing;
Fig. 9 is the cross-sectional view in the array base palte preparation method of embodiment of the present utility model after forming thinning area;
Figure 10 is the cross-sectional view in the array base palte preparation method of embodiment of the present utility model after stripping photolithography glue-line;
Figure 11 is the cross-sectional view in the array base palte preparation method of embodiment of the present utility model after forming pixel electrode;
Wherein, Reference numeral is: 1, grid; 2, gate insulation layer; 3, active area; 39, semiconductor layer; 41, drain; 411, thinning area; 42, source electrode; 49, source and drain metal level; 5, pixel electrode; 51, clinch; 52, main part; 6, planarization layer; 7, public electrode; 8, photoresist layer; 9, substrate; Q1, first area; Q2, second area; Q3, the 3rd region.
Embodiment
For making those skilled in the art understand the technical solution of the utility model better, below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
Embodiment 1:
As shown in Figure 2, the present embodiment provides a kind of display base plate, and it comprises the first structure and the second structure; Second structure has is located at the first structural clinch 51, and is positioned at the outer and main part 52 be connected with clinch 51 of the first structure;
First structure has the thinning area 411 that to be connected with its edge, and in thinning area 411, the thickness of the first structure is less than the thickness of the first structure outside thinning area 411;
Clinch 51 is positioned on thinning area 411 at least partly; And the main part be positioned at least partly outside thinning area 411 is directly connected with the clinch 51 be positioned on thinning area 411.
Wherein, the display base plate of the present embodiment can be for the substrate in liquid crystal indicator, Organic Light Emitting Diode (OLED) display unit etc., be such as array base palte, color membrane substrates, to box substrate etc.The first structure and the second structure that are in different layers is comprised at this display base plate.The thinner thickness of subregion (thinning area 411) is had in first structure, and this thinning area 411 is connected with the edge of the first structure, namely should there be at least part of overlap at the edge of thinning area 411 and the edge of the first structure, and can not be thinning area 411 to be positioned at completely in the middle part of the first structure and by non-thinning area around.Second structure then some (clinch 51) is located on this thinning area 411, and another part (main part 52) is positioned at outside thinning area 411; And, portion body portion 52 is had at least to be directly connected with the clinch 51 on thinning area 411, thus when the main part 52 of the second structure is connected with clinch 51, because clinch 51 is at least partially on thinning area 411, therefore at least can reduce the difference in height of this part clinch 51 and main part 52, ensure to connect reliably, not easily rupture.
Visible, first structure of the display base plate of the present embodiment has thinning area 411, namely the first structure is " ladder " shape, its " ladder " top has normal thickness, the realization of the function of the first structure own can be ensured, second structure then " overlap joint " (is namely overlapped on the lower of " ladder ") on the thinning area 411 of the first structure, thus, difference in height (section is poor) between the clinch 51 of the second structure and main part 52 is less, therefore between its clinch 51 and main part 52, be less likely to occur fracture, better can ensure the performance of display base plate.
Preferably, the display base plate of the present embodiment is array base palte, and the first structure is drain electrode 41, second structure of thin-film transistor is pixel electrode 5.
That is, the present embodiment display base plate is preferably array base palte (more specifically the array base palte of liquid crystal indicator), and drain electrode 41, the second structure that the first structure is wherein thin-film transistor is pixel electrode 5.This is because the thickness of general drain electrode 41 is large more than the thickness of pixel electrode 5, therefore the most easily ruptures when pixel electrode 5 snaps in drain electrode 41, the most applicable the utility model.
In the following description of the present embodiment, drain electrode 41, second structure being all thin-film transistor with the first structure is pixel electrode 5 for example is described.But, should be appreciated that protection range of the present utility model is not limited to this, in the display base plate of any type, as long as occur that a structure is overlapped on another structural situation, all can use the utility model.Such as, if the source electrode of thin-film transistor 42,41 parts that drain are positioned on active area 3, and another part is positioned at outside active area 3, then also can using active area 3 as the first structure, and source electrode 42, drain electrode 41 is as the second structure.
Preferably, drain electrode 41 is located on active area 3 completely.
That is, this drain electrode 41 is preferably positioned on active area 3 completely, and is not positioned at the part outside active area 3.This is because the drain electrode 41 of this structure can be formed in a patterning processes with active area 3 on the one hand simultaneously, preparation technology is fairly simple.
Wherein, above array base palte can be the array base palte of senior super dimension field translative mode.
That is, this array base palte can be the array base palte that senior super Wei Chang changes (ADS) pattern, namely on its pixel electrode 5, is also provided with planarization layer 6 (or passivation layer), planarization layer 6 is then provided with the public electrode 7 of form of slits.But obviously, if this array base palte be twisted-nematic (TN) pattern, along other types such as face switch (IPS) patterns, be also feasible.
Preferably, display base plate also comprises substrate 9, and the distance between the first structure and substrate 9 is more than or equal to the distance between the main part 52 of the second structure and substrate 9.
That is, the position residing for above first structure (drain electrode 41) should than the position higher (at least flushing) of the main part 52 of the second structure (pixel electrode 5).Such as, as shown in Figure 2, the main part 52 of pixel electrode 5 (the second structure) is directly located on gate insulation layer 2,41 (the first structures) that drain then are located on active area 3, active area 3 is located on gate insulation layer 2, therefore drain electrode 41 (the first structures) exceed the thickness of active area 3 than the main part 52 of pixel electrode 5 (the second structure).This is because the difference in height in the above case between the main part 52 of the second structure and clinch 51 is larger, more easily ruptures, therefore more need to use the utility model.
Preferably, the thickness of first structure of thickness outside thinning area 411 of the first structure in thinning area 411 1/2 to 2/3 between.
That is, if with the maximum ga(u)ge of the first structure (thickness of the first structure outside thinning area 411) for 1, then the thickness of the first structure in thinning area 411 is 1/2 to 2/3, and the thickness being namely thinned the part of removing is 1/3 to 1/2.This thickness difference is generally enough to avoid the second structure (pixel electrode 5) to rupture.
Preferably, clinch 51 covers whole thinning area 411.
That is, first structure (drain electrode 41) can all cover (reality also can exceed thinning area 411) thinning area 411 by the clinch 51 of the second structure (pixel electrode 5) completely, thus the contact area both increasing, reduce contact resistance.Certainly, if clinch 51 covers a part for thinning area 411, be also feasible.It should be noted that, thinning area 411 can set the size in its region according to the needs of technique, as long as can ensure to connect reliably, repeats no more here.
Preferably, the part that overlapped portion 51, thinning area 411 covers comprises multiple sub-thinning area 411, and less the closer to the thickness of the first structure in the sub-thinning area 411 at the first structure (drain electrode 41) edge.
That is, thinning area 411 also can be divided into multistage, and it is thinner the closer to the thinning area 411 at the first structure (drain electrode 41) edge, thinning area 411 is also divided into multiple " ladder " in other words, can better prevent the second structure (pixel electrode 5) from rupturing in thinning area 411 like this.
As shown in Figures 2 to 11, the present embodiment also provides a kind of preparation method of above-mentioned display base plate, and it comprises:
Step 1, form the first structure, and by thinning for the subregion of the first structure, form the thinning area 411 adjacent with the edge of the first structure;
Step 2, form the second structure, the second structure has is located at the first structural clinch 51, and is positioned at the outer and main part 52 be connected with clinch 51 of the first structure, and clinch 51 is positioned on thinning area 411 at least partly; And the main part 52 be positioned at least partly outside thinning area is directly connected with the clinch 51 be positioned on described thinning area.
Visible, for preparing above-mentioned display base plate, can first form the first structure, and form thinning area 411 wherein, be formed to the second structure that small part covers this thinning area 411 afterwards again.
Preferably, comprise thinning for the subregion of the first structure in step 1: the region covering the non-thinning area of corresponding first structure with photoresist, by dry etching by thinning for the first structure not covered by photoresist.
That is, can carry out thinning to the first structure by the technique of dry etching.Dry etching is the technology that the mordant gas of apparatus etches structure, because its etching speed is usually comparatively slow, controls than being easier to, therefore the first structure that can be used for removing specific thicknesses is to form thinning area 411.Certainly, form the mode of thinning area 411 and be not limited to this, such as, if the first structure has photosensitive material, then the exposure can carrying out in various degree to its position, thinning area 411 and the position of non-thinning area, thus formation thinning area 411.
Preferably, in step 1, utilize ladder to be exposed in a patterning processes to form the first structure and by thinning for the subregion of the first structure.
That is, ladder exposure technology can be utilized to form the photoresist layer 8 of different-thickness at diverse location, thus after single exposure, first form the first above-mentioned structure by etching, continue afterwards to form thinning area 411 in the first structure.
Preferably, display base plate is array base palte, and the first structure is drain electrode 41, second structure of thin-film transistor is pixel electrode 5.Preferred, above active area 3 is synchronous with drain electrode 41 (the first structure) in step 1 formation, and drain electrode 41 is located on active area 3 completely.
That is, the method for the present embodiment is preferred for preparing above-mentioned array base palte.Concrete, describe in detail to the preparation method of this array base palte below, it comprises the following steps:
S101, in substrate 9, form grid 1, grid line, gate insulation layer 2 successively by patterning processes.
That is, by the patterning processes of routine, substrate 9 forms the conventional structures such as grid 1, grid line, gate insulation layer 2.Certainly, in this step, also can comprise the operation forming other known structure such as resilient coating (before forming grid 1), be not described in detail at this.
S102, in substrate 9, form semiconductor layer 39, source and drain metal level 49, photoresist layer 8 successively.
That is, on gate insulation layer 2, form complete semiconductor layer 39, source and drain metal level 49, photoresist layer 8 successively by the method for routine (deposition or on foot), obtain structure as shown in Figure 3.
Wherein, source and drain metal level 49 can be made up of the metal or alloy of molybdenum, niobium, tungsten, titanium etc., and thickness can at hundreds of micron.
S103, photoresist layer 8 is carried out ladder exposure and developed, the photoresist layer 8 of the first thickness is retained at first area Q1, second area Q2 retains the photoresist layer 8 of photoresist layer the 8, three region Q3 reservation the 3rd thickness of the second thickness, and all the other regions do not retain photoresist layer 8; Wherein, the region of Q1 corresponding active area 3 in first area for conducting electricity when thin-film transistor conducting, the thinning area 411 of at least corresponding drain electrode 41 of second area Q2, region in the 3rd at least corresponding active area 3 of region Q3 except first area Q1 and second area Q2, and, first thickness is less than the second thickness, and the second thickness is less than the 3rd thickness.
That is, exposure in various degree (as used the exposure of gray level mask plate) is carried out to the different piece of this photoresist layer 8, thus after development, retains the photoresist layer 8 of different-thickness at diverse location.Wherein, structure as shown in Figure 4, in corresponding active area 3 for region (" the raceway groove ") place of conducting electricity during in thin-film transistor conducting, retains the photoresist layer 8 of the thinnest (i.e. the first thickness); In the position of the thinning area 411 for the formation of drain electrode 41, retain the photoresist layer 8 of intermediate gauge (i.e. the second thickness); In other positions (source electrode 42, the non-thinning area of drain electrode 41) of active area 3, then retain the photoresist layer 8 of the thickest (i.e. the 3rd thickness); And the position outside active area 3, then do not retain photoresist layer 8.
Wherein, if data wire synchronously will be formed with source electrode 42, then also can retain the photoresist layer 8 of the 3rd thickness in the position of respective data lines, namely the 3rd region Q3 also can comprise the region of respective data lines.
S104, removing without photoresist covering source and drain metal level 49 and semiconductor layer 39, be formed with source region 3.
That is, to do not removed (as removed respectively with different etching agents) by the source and drain metal level 49 that covers without photoresist and semiconductor layer 39 by etching, by outside active area 3 (if synchronously form data wire, if then also outside data wire) source and drain metal level 49 and semiconductor layer 39 remove, thus make remaining semiconductor layer be formed with source region 3, and active area 3 covers source and drain metal level 49, namely obtain structure as shown in Figure 5.
S105, ashing is carried out to photoresist layer 8, the photoresist layer 8 of removing first area Q1, and at second area Q2 and the 3rd region Q3 reserve part photoresist layer 8.
That is, by cineration technics by thinning for photoresist layer 8, it at least wants thinning first thickness, thus the photoresist layer 8 of first thickness at first area Q1 (raceway groove) place is removed completely, and second area Q2 and the 3rd Q3 place, region also remain with certain thickness photoresist layer 8, thus obtain structure as shown in Figure 6.
Certainly, in the podzolic process of photoresist layer 8, the area of actual photoresist layer 8 also can reduce a little, but belongs to because of it inevitable error that technique causes, therefore no longer considers at this.
The source and drain metal level 49 of S106, removing first area Q1, forms source electrode 42, drain electrode 41.
Now first area Q1 (raceway groove) place no longer includes photoresist layer 8, therefore is removed by the source and drain metal level 49 at this place by etching, thus forms source electrode separately 42 and drain electrode 41, obtains structure as shown in Figure 7.
S107, ashing is carried out to photoresist layer 8, the photoresist layer 8 of removing second area Q2, and at the 3rd region Q3 reserve part photoresist layer 8.
That is, again by cineration technics by thinning for photoresist layer 8, its photoresist layer 8 that will be thinned to second area Q2 is completely removed, and the 3rd Q3 place, region also remains with certain thickness photoresist layer 8, thus obtains structure as shown in Figure 8.
The source and drain metal level 49 of S108, thinning second area Q2, forms thinning area 411.
Now the source and drain metal level 49 of second area Q2 (thinning area 411) exposes, thus by dry etch process, it is thinning and form above-mentioned thinning area 411, obtains structure as shown in Figure 9.Wherein, thinning process gas used, technological parameter etc. can be adjusted as required by those skilled in the art.Such as, when want thinning to as if the drain electrode 41 of metal of thickness hundreds of microns time, the chlorine of concentration 99% can be adopted as process gas (other can be the protective gas such as nitrogen), and etch period can at 20 seconds to 40 seconds, such as, be 30 seconds; According to above etching parameters, can by the thinning area 411 thinning 1/3 to 1/2 of drain electrode 41.
Preferably, in this step, carry out in various degree to the zones of different of thinning area 411 thinning, and it is larger the closer to the thinning degree in the region at drain electrode 41 (the first structure) edge, thus its thinning area 411 formed is divided into multiple sub-thinning area, namely it can obtain the above-mentioned structure with sub-thinning area.
Concrete, realize by the photoresist layer 8 of second area Q2 being further divided into multiple different-thickness with upper type.So, then can first remove photoresist layer 8 the thinnest in second area Q2, and part thinning area 411 is exposed, and carry out thinning to it; Again photoresist layer 8 slightly thick in second area Q2 is removed afterwards, another part thinning area 411 is exposed, and it is carried out thinning (thinning area 411 exposed is certainly also by thinning further), different thinning degree can be obtained at the diverse location of thinning area 411 like this, namely form sub-thinning area.
Certainly, when sub-thinning area will be formed, be also noted that and etching parameters is adjusted.Such as, the sub-thinning area exposed at first also can be etched gradually in the etching of sub-thinning area afterwards, therefore need during selective etching parameter to consider this point, but because its specific implementation is that those skilled in the art can select as required, therefore be not described in detail at this.
The photoresist layer 8 of S109, removing the 3rd region Q3.
Peel off by final remaining photoresist layer 8, thus obtain structure as shown in Figure 10, comprising the drain electrode 41 with thinning area 411.
S110, to be formed by patterning processes and comprise the figure of pixel electrode 5 (the second structure).
That is, continue to form pixel electrode 5 by conventional method, this pixel electrode 5 has the clinch 51 covered on drain electrode 41 thinning area 411, and the main part 52 be positioned at outside thinning area 411, obtain structure (just in time covering whole thinning area 411 for clinch 51) as shown in figure 11.
Like this, when thinning area 411 is divided into multiple sub-thinning area, the clinch 51 now formed just can cover multiple sub-thinning area, thus reduces the impact of difference in height better.
S111, optional, continue to form planarization layer 6, public electrode 7.
That is, continue to prepare other the known structure such as planarization layer 6, public electrode 7, thus obtain the array base palte of the ADS pattern of structure as shown in Figure 2.
Of course it is to be understood that the preparation method of above array base palte also can carry out many distortion.Such as, thin-film transistor also can be top gate type, can prepare gate insulation layer 2 and grid 1 (grid line) after being formed with source region 3 again; For another example, array base palte can be TN pattern, then it just no longer needs to continue to prepare public electrode 7 after formation pixel electrode 5; For another example, source electrode 42, drain electrode 41 are not formed in a patterning processes with active area 3 yet, source region 3 be can first be formed with, source electrode 42, drain electrode 41 (corresponding, now source electrode 42, drain electrode 41 is also not necessarily only positioned on active area 3) prepared afterwards again; For another example, if active area 3 is made up of metal-oxide semiconductor (MOS), then also can comprises in its preparation and form other known steps of etching barrier layer (ESL) etc.
Be understandable that, the illustrative embodiments that above execution mode is only used to principle of the present utility model is described and adopts, but the utility model is not limited thereto.For those skilled in the art, when not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection range of the present utility model.
Claims (7)
1. a display base plate, is characterized in that, comprises the first structure and the second structure; Described second structure has is located at the first structural clinch, and is positioned at the outer and main part be connected with clinch of the first structure;
Described first structure has the thinning area that to be connected with its edge, and in described thinning area, the thickness of the first structure is less than the thickness of the first structure outside thinning area;
Described clinch is positioned on described thinning area at least partly; And the main part be positioned at least partly outside thinning area is directly connected with the clinch be positioned on described thinning area.
2. display base plate according to claim 1, is characterized in that,
Described display base plate is array base palte, and described first structure is the drain electrode of thin-film transistor, and described second structure is pixel electrode.
3. display base plate according to claim 2, is characterized in that,
Described drain electrode is located on active area completely.
4. display base plate as claimed in any of claims 1 to 3, is characterized in that,
Described display base plate also comprises substrate, and the distance between described first structure and substrate is more than or equal to the distance between the main part of described second structure and substrate.
5. display base plate as claimed in any of claims 1 to 3, is characterized in that,
Described clinch covers whole thinning area.
6. display base plate as claimed in any of claims 1 to 3, is characterized in that,
The part that overlapped portion, described thinning area covers comprises multiple sub-thinning area, and the thickness the closer to the first structure in the sub-thinning area of the first structural edge is less.
7. display base plate as claimed in any of claims 1 to 3, is characterized in that,
The thickness of first structure of thickness outside thinning area of the first structure in described thinning area 1/2 to 2/3 between.
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| CN201520146239.XU CN204407332U (en) | 2015-03-13 | 2015-03-13 | Display base plate |
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| CN201520146239.XU CN204407332U (en) | 2015-03-13 | 2015-03-13 | Display base plate |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104733473A (en) * | 2015-03-13 | 2015-06-24 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104733473A (en) * | 2015-03-13 | 2015-06-24 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method thereof |
| WO2016145758A1 (en) * | 2015-03-13 | 2016-09-22 | 京东方科技集团股份有限公司 | Display substrate and manufacturing method thereof |
| US9791758B2 (en) | 2015-03-13 | 2017-10-17 | Boe Technology Group Co., Ltd. | Display substrate and manufacturing method thereof |
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