CN204406008U - Thin-film transistor array base-plate and display device - Google Patents
Thin-film transistor array base-plate and display device Download PDFInfo
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- CN204406008U CN204406008U CN201520099817.9U CN201520099817U CN204406008U CN 204406008 U CN204406008 U CN 204406008U CN 201520099817 U CN201520099817 U CN 201520099817U CN 204406008 U CN204406008 U CN 204406008U
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Abstract
The utility model provides a kind of thin-film transistor array base-plate, this thin-film transistor array base-plate comprises first substrate, be arranged on the multi-strip scanning line of transposition insulator on first substrate and a plurality of data lines, arrange on the first substrate bind district and second grid driving circuit for the gate driver circuit binding first grid driving circuit, wherein second grid driving circuit is integrated on this first substrate.The utility model also provides a kind of display device of this thin-film transistor array base-plate of application.Thin-film transistor array base-plate of the present utility model and the display device applying this thin-film transistor array base-plate arrange for the second grid driving circuit to sweep trace input sweep signal and the gate driver circuit binding district for binding first grid driving circuit on thin-film transistor array base-plate simultaneously, ensure that the transistor on thin-film transistor array base-plate can normally be opened, production yield can be improved.
Description
Technical field
The utility model relates to display technique field, particularly relates to a kind of thin-film transistor array base-plate and uses the display device of this thin-film transistor array base-plate.
Background technology
With traditional cathode-ray tube (CRT) (Cathode Ray Tube, CRT) display is compared, liquid crystal display (Liquid Crystal Display, LCD) is widely used in the electronic products such as monitor, mobile device and panel computer due to its volume is little, lightweight, thickness is thin, power consumption is little, radiationless advantage.
The display panel of liquid crystal display comprises color membrane substrates, thin-film transistor array base-plate and the liquid crystal between color membrane substrates and thin-film transistor array base-plate.Wherein, thin-film transistor array base-plate is provided with sweep trace and the data line of transposition insulator, at the pixel electrode that cross section is connected with transistor and is connected with transistor, color membrane substrates is provided with public electrode, pixel electrode, public electrode and Formation of liquid crystals liquid crystal capacitance therebetween.In addition, thin-film transistor array base-plate is also provided with gate driver circuit and source electrode drive circuit, gate driver circuit is used for providing signal to sweep trace, to open all crystals pipe that this sweep trace is expert at, source electrode drive circuit provides display voltage to charge to liquid crystal capacitance by the transistor opened to pixel electrode, thus realizes the normal display of picture.
In recent years, along with the increasingly mature of LCD plate technique and people are to the requirement of its apparent size, increasing display panels develops towards narrow frame, therefore gate driver circuit is passed through the method integration of mask etch on thin-film transistor array base-plate by the design producer of display panels, namely GIA (the Gate In Array) circuit of industry general designation, but the design production technology due to GIA circuit is not very ripe, guarantee to design successful GIA circuit once very difficult, and light shield also can be caused in the fabrication process repeatedly to revise and to cause the not exploitativeness of GIA circuit and scrapping of thin-film transistor array base-plate, even cause the overall failure of Project design.In addition, for high-resolution liquid crystal display panel, the cabling of GIA circuit will be more complicated than the cabling of low resolution display panels.Therefore, when adopting separately GIA circuit to drive the transistor on thin-film transistor array base-plate, in certain width range, more space is not had to realize the cabling of GIA circuit, or cannot realize GIA circuit trace in certain width range, this all can cause the yield of display panels can not be guaranteed.
Therefore, need to provide a kind of thin-film transistor array base-plate and display device, it can solve in the GIA circuit design process of display panels in above-mentioned prior art and cause because light shield is repeatedly revised and GIA circuit trace complicated the problem that display panels yield is low.
Utility model content
In view of above problem, the utility model provides a kind of thin-film transistor array base-plate and display device of high yield.
Particularly, embodiment of the present utility model provides a kind of thin-film transistor array base-plate, this thin-film transistor array base-plate comprises first substrate, is arranged on the multi-strip scanning line of transposition insulator on this first substrate and a plurality of data lines, binds district and second grid driving circuit for the gate driver circuit binding first grid driving circuit, wherein, this second grid driving circuit is integrated on this first substrate.
In one embodiment, this thin-film transistor array base-plate also comprises this first grid driving circuit, and this first grid driving circuit is bundled in this gate driver circuit binding district.
In one embodiment, this first grid driving circuit is integrated chip.
In one embodiment, this first grid driving circuit is connected with a part for this multi-strip scanning line on this first substrate.
In one embodiment, this second grid driving circuit is connected with another part of this multi-strip scanning line on this first substrate.
In one embodiment, this gate driver circuit binding district is arranged on this first substrate.
In one embodiment, this second grid driving circuit is arranged on this first substrate and binds the relative another side in district with this gate driver circuit.
In one embodiment, this gate driver circuit binding district is connected with this multi-strip scanning line on this first substrate.
In one embodiment, this second grid driving circuit is connected with this multi-strip scanning line on this first substrate.
Embodiment of the present utility model also provides a kind of display device, and this display device comprises above-mentioned thin-film transistor array base-plate.
Thin-film transistor array base-plate of the present utility model and the display device applying this thin-film transistor array base-plate are arranged for the second grid driving circuit to sweep trace input sweep signal and the gate driver circuit binding district for binding first grid driving circuit on thin-film transistor array base-plate simultaneously.When second grid driving circuit cannot normally work, district's binding first grid driving circuit can be bound at gate driver circuit, to ensure that the transistor on thin-film transistor array base-plate can normally be opened, improve the production yield of thin-film transistor array base-plate and display device.
Accompanying drawing explanation
The planar structure schematic diagram of the display device that Fig. 1 provides for the first embodiment of the present utility model.
The planar structure schematic diagram of the thin-film transistor array base-plate of the display device that Fig. 2 provides for the second embodiment of the present utility model.
Embodiment
For further setting forth the utility model for the technological means reaching predetermined utility model object and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to according to the thin-film transistor array base-plate that the utility model proposes and its embodiment of display device, method, step, structure, feature and effect, be described in detail as follows.
About aforementioned and other technology contents, feature and effect of the present utility model, can clearly present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, when can to the utility model for the technological means reaching predetermined object and take and effect be able to more deeply and concrete understanding, but institute's accompanying drawings is only to provide with reference to the use with explanation, is not used for being limited the utility model.
Refer to Fig. 1, the planar structure schematic diagram of the display device that Fig. 1 provides for the first embodiment of the present utility model.As shown in Figure 1, display device comprises thin-film transistor array base-plate 12 that color membrane substrates (not shown) and color membrane substrates be oppositely arranged, liquid crystal (not shown), flexible PCB 127 and printed circuit board (PCB) 128 between color membrane substrates and thin-film transistor array base-plate 12.Thin-film transistor array base-plate 12 connects printed circuit board (PCB) 128 through flexible PCB 127.Thin-film transistor array base-plate 12 is provided with viewing area 10 and surrounds the non-display area (sign) of viewing area 10.Thin-film transistor array base-plate 12 comprises first substrate 120, be arranged on the multi-strip scanning line 121 of transposition insulator first substrate 120 being positioned at viewing area 10 and a plurality of data lines 122, be formed in the transistor 123 of cross section and be arranged on first substrate 120 is positioned at non-display area bind district 124, second grid driving circuit 125 and source electrode drive circuit 126 for the gate driver circuit binding (Bonding) first grid driving circuit.Wherein, source electrode drive circuit 126 connects a plurality of data lines 122 for a plurality of data lines 122 input data signal; Gate driver circuit binding district 124 is arranged on the one side on first substrate 120, connects multi-strip scanning line 121, for binding the first grid driving circuit that can input sweep signal to multi-strip scanning line 121; Second grid driving circuit 125 is arranged on the relative another side in the limit of first substrate 120 being bound place, district 124 with gate driver circuit, connects multi-strip scanning line 121, for inputting sweep signal to multi-strip scanning line 121.
Particularly, first grid driving circuit can be gate driver circuit integrated chip, when first grid driving circuit is bundled in gate driver circuit binding district 124, at time schedule controller (Timingcontrol, TCON), under control, sweep signal is inputted to drive the transistor 123 that on first substrate 120, corresponding sweep trace 121 is expert to multi-strip scanning line 121 successively.Wherein, first grid driving circuit comprises multi-stage shift register, shift register receives gating start signal, gating displacement clock signal and the gating enable signal that TCON exports, shift register inputs sweep signal according to the gating start signal received, gating displacement clock signal and gating enable signal to the sweep trace 121 of correspondence, and inputs sweep signal according to gating displacement clock signal to next line sweep trace 121 after all crystals pipe 123 of being expert at by the sweep trace 121 of correspondence is opened.
Second grid driving circuit 125 has the principle of work identical with first grid driving circuit, its concrete principle of work describes in first grid driving circuit, do not repeat them here, with first grid driving circuit unlike, second grid driving circuit 125 is that mask etch is on first substrate 120, that is, second grid driving circuit 125 directly designs on the first substrate 120 of thin-film transistor array base-plate 12, i.e. the GIA circuit of industry general designation.
Source electrode drive circuit 126 can be the source electrode drive circuit integrated chip be bundled on first substrate 120, under the control of TCON, the data-signal inputted by high frequency stores in mnemon therein, and the data-signal be stored in mnemon is converted to the display voltage that exports pixel electrode (not shown) to after the transistor 123 that corresponding sweep trace 121 is expert at is opened and by a plurality of data lines 122 to drive the pixel of the correspondence on first substrate 120.Wherein, source electrode drive circuit 126 internal main will comprise bidirectional shift register, input data register, data latch, level shifter, A/D converter and voltage follower.
Particularly, when source electrode drive circuit 126 receives the display data of TCON output, shift register is each input data register of gating successively, and display data enters input data register according to system clock tandem, after the display data of a line is filled with, data latch is opened by latch signal, and display data all enters data latch and latches.Now, display data in data latch is via after A/D converter, transfer simulating signal to digital signal, and low level digital signal is converted to high-tension digital signal via level displacement shifter by digital signal after conversion again, and then selects target gray voltage from multistage grayscale voltage (as 256 rank).But, because this target gray voltage does not possess driving force, therefore must add voltage order one follower thereafter, to drive a plurality of data lines 122 on first substrate 120, and then this target gray voltage is being sent to pixel electrode (sign).
Flexible PCB 127 adopts the mode of conducting film or conducting resinl to be pressed together on the first substrate 120 of thin-film transistor array base-plate 12, in the present embodiment, flexible PCB 127 and source electrode drive circuit 126 are on same one side of first substrate 120, certainly it will be appreciated by those skilled in the art that, flexible PCB 127 also can bind same at first substrate 120 of district 124 or second grid driving circuit 125 with gate driver circuit.
Printed circuit board (PCB) 128 is provided with TCON and power module, voltage generator and common electric voltage generator.Wherein, TCON is for controlling the work schedule of first grid driving circuit, second grid driving circuit 125 and source electrode drive circuit 126 and inputting the sweep signals such as gating start signal, gating displacement clock signal and gating enable signal to first grid driving circuit and/or second grid driving circuit 125, in addition, TCON is also for inputting RGB data signal to source electrode drive circuit 126; Power module is used for the gate high-voltage of first grid driving circuit and/or second grid driving circuit 125 input service, grid low-voltage and supply voltage; This grayscale voltage for generation of grayscale voltage, and is sent to source electrode drive circuit 126 by voltage generator; Common electric voltage generator is used for sending common electric voltage to source electrode drive circuit 126.It should be noted that in other embodiments, TCON and power module all can be integrated in source electrode drive circuit 126.
Particularly, due to second grid driving circuit 125 be by gate driver circuit mask etch on first substrate 120, although the design simulation success of second grid driving circuit 125, but in actual production, but can not guarantee the second grid driving circuit 125 energy volume production success of all thin-film transistor array base-plates 12, if therefore there is the inoperable situation of second grid driving circuit 125, then can bind first grid driving circuit in the gate driver circuit binding district 124 on the first substrate 120 of corresponding thin-film transistor array base-plate 12, by first grid driving circuit for multi-strip scanning line 121 provides sweep signal.
Therefore, the gate driver circuit that the present embodiment is provided with for binding first grid driving circuit on first substrate 120 simultaneously binds district 124 and second grid driving circuit 125, this kind of design can make when second grid driving circuit 125 cisco unity malfunction, employing binding first grid driving circuit drives the multi-strip scanning line 121 on first substrate 120, can normally work to make display device.Particularly, when second grid driving circuit 125 cisco unity malfunction, radium-shine method can be adopted to be disconnected with multi-strip scanning line 121 by the second grid driving circuit 125 on first substrate 120, or directly adopt the TCON in printed circuit board (PCB) 128 to control the sequential of second grid driving circuit 125, and adopt the direct current-direct current voltage converter in printed circuit board (PCB) 128 that closedown voltage is supplied to second grid driving circuit 125 thus control second grid driving circuit 125 and close, impact to prevent the 125 pairs of display frames of second grid driving circuit.Certainly, if when second grid driving circuit 125 can normally work, second grid driving circuit 125 now can be adopted to drive the multi-strip scanning line 121 on first substrate 120, and gate driver circuit be bound district 124 and do reserved.
Display device of the present utility model when second grid driving circuit 125 design and produce bad or cannot normally work time, can bind first grid driving circuit adopts first grid driving circuit to drive multi-strip scanning line 121 in gate driver circuit binding district 124, and without the need to redesigning, mask etch second grid driving circuit 125, therefore without the need to again changing thin-film transistor array base-plate 12, reduce the scrappage of thin-film transistor array base-plate 12 and display device, and when the designing and producing criterion of acceptability or can normally work of second grid driving circuit 125, gate driver circuit can be bound district 124 does reserved, improve the maintenanceability of display device and produce yield.
Refer to Fig. 2, the planar structure schematic diagram of the thin-film transistor array base-plate of the display device that Fig. 2 provides for the second embodiment of the present utility model.As shown in Figure 2, thin-film transistor array base-plate 22 comprises first substrate 220, is arranged on the multi-strip scanning line 221 of transposition insulator on first substrate 220 and binds district 224, second grid driving circuit 225, source electrode drive circuit 226 and first grid driving circuit 227 with a plurality of data lines 222, the transistor 223 being formed in cross section, gate driver circuit.Wherein, first grid driving circuit 227 is bundled in gate driver circuit binding district 224, second grid driving circuit 225 is integrated on first substrate 220, gate driver circuit binding district 224 is arranged on one side on first substrate 220, and second grid driving circuit 225 is arranged on the relative another side in the limit of first substrate 220 being bound place, district 224 with gate driver circuit.
Particularly, total 2n bar sweep trace 221 on thin-film transistor array base-plate 22, first grid driving circuit 227 and the 1st article of sweep trace G1 to the n-th article of sweep trace Gn is connected, second grid driving circuit 225 is connected to 2n article of sweep trace G2n with (n+1)th article of sweep trace Gn+1, that is, first grid driving circuit 227 is responsible for opening all crystals pipe 223 that the 1st article of sweep trace G1 to the n-th article of sweep trace Gn is expert at, second grid driving circuit 225 is responsible for opening all crystals pipe 223 that (n+1)th article of sweep trace Gn+1 to 2n article of sweep trace G2n is expert at, namely the transistor 223 opening thin-film transistor array base-plate 22 the first half is responsible for by first grid driving circuit 227, the transistor 223 opening thin-film transistor array base-plate 22 the latter half is responsible for by second grid driving circuit 225.Wherein, second grid driving circuit 225 is GIA circuit, and first grid driving circuit 227 is grid integrated chip.Because the transistor 223 opening thin-film transistor array base-plate 22 half is responsible for by second grid driving circuit 225, therefore in prior art, connect the GIA circuit of whole sweep trace, the cabling of second grid driving circuit 225 on thin-film transistor array base-plate 22 of the present embodiment is few, take up room little, reduce thin-film transistor array base-plate 22 and bad risk occurs.
In another embodiment of the present utility model, the all crystals pipe 223 of all row opening the 1st article of sweep trace G1 to the n-th article of sweep trace Gn place is responsible for by second grid driving circuit 225, first grid driving circuit 227 is responsible for opening all crystals pipe 223 of (n+1)th article of sweep trace Gn+1 to all row at 2n article of sweep trace G2n place, that is, the transistor 223 opening thin-film transistor array base-plate 22 the first half is responsible for by second grid driving circuit 225, and the transistor 223 opening thin-film transistor array base-plate 22 the latter half is responsible for by first grid driving circuit 227.Certainly it will be understood by those skilled in the art that, first grid driving circuit 227 can open all crystals pipe 223 that a part of sweep trace 221 on thin-film transistor array base-plate 22 is expert at, the all crystals pipe 223 that the sweep trace 221 of the other part that second grid driving circuit 225 can be opened on thin-film transistor array base-plate 22 is expert at, wherein, these two parts can not be overlapping.
In the present embodiment, thin-film transistor array base-plate 22 is responsible for inputting sweep signal to the sweep trace 221 of part by first grid driving circuit 227, second grid driving circuit 225 is responsible for inputting sweep signal to the sweep trace 221 of another part, while all crystals pipe 223 that ensure that on thin-film transistor array base-plate 22 is able to normal work, decrease the cabling of second grid driving circuit 225, and then make the design and manufaction of second grid driving circuit 225 become easy, ensure that the production yield of thin-film transistor array base-plate 22 to a certain extent.
The above, it is only preferred embodiment of the present utility model, not any pro forma restriction is done to the utility model, although the utility model discloses as above with preferred embodiment, but and be not used to limit the utility model, any those skilled in the art, do not departing within the scope of technical solutions of the utility model, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solutions of the utility model content, according to any simple modification that technical spirit of the present utility model is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solutions of the utility model.
Claims (10)
1. a thin-film transistor array base-plate, this thin-film transistor array base-plate comprises first substrate, is arranged on the multi-strip scanning line of transposition insulator on this first substrate and a plurality of data lines, it is characterized in that, the gate driver circuit that this thin-film transistor array base-plate also comprises for binding first grid driving circuit binds district and second grid driving circuit, wherein, this second grid driving circuit is integrated on this first substrate.
2. thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, this thin-film transistor array base-plate also comprises first grid driving circuit, and this first grid driving circuit is bundled in this gate driver circuit binding district.
3. thin-film transistor array base-plate as claimed in claim 2, it is characterized in that, this first grid driving circuit is integrated chip.
4. thin-film transistor array base-plate as claimed in claim 2, it is characterized in that, this first grid driving circuit is connected with a part for this multi-strip scanning line on this first substrate.
5. thin-film transistor array base-plate as claimed in claim 4, it is characterized in that, this second grid driving circuit is connected with another part of this multi-strip scanning line on this first substrate.
6. thin-film transistor array base-plate as claimed in claim 1, is characterized in that, this gate driver circuit binding district is arranged on this first substrate.
7. thin-film transistor array base-plate as claimed in claim 6, it is characterized in that, this second grid driving circuit is arranged on this first substrate and binds the relative another side in district with this gate driver circuit.
8. thin-film transistor array base-plate as claimed in claim 1, is characterized in that, this gate driver circuit binding district is connected with this multi-strip scanning line on this first substrate.
9. thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, this second grid driving circuit is connected with this multi-strip scanning line on this first substrate.
10. a display device, is characterized in that, this display device comprises the thin-film transistor array base-plate as described in any one of claim 1-9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520099817.9U CN204406008U (en) | 2015-02-11 | 2015-02-11 | Thin-film transistor array base-plate and display device |
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| CN201520099817.9U CN204406008U (en) | 2015-02-11 | 2015-02-11 | Thin-film transistor array base-plate and display device |
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| CN204406008U true CN204406008U (en) | 2015-06-17 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109523970A (en) * | 2018-12-24 | 2019-03-26 | 惠科股份有限公司 | Display module and display device |
| CN110473464A (en) * | 2019-07-30 | 2019-11-19 | 武汉华星光电技术有限公司 | Display panel |
-
2015
- 2015-02-11 CN CN201520099817.9U patent/CN204406008U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109523970A (en) * | 2018-12-24 | 2019-03-26 | 惠科股份有限公司 | Display module and display device |
| WO2020134947A1 (en) * | 2018-12-24 | 2020-07-02 | 惠科股份有限公司 | Display module and display apparatus |
| CN110473464A (en) * | 2019-07-30 | 2019-11-19 | 武汉华星光电技术有限公司 | Display panel |
| US11378851B2 (en) | 2019-07-30 | 2022-07-05 | Wuhan China Star Optoelectronics Technology Co., Ltd | Display panel and display device |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: Kunshan Longteng Optronics Co., Ltd. |