CN204374951U - A kind of interruptable controller of neural network processor - Google Patents
A kind of interruptable controller of neural network processor Download PDFInfo
- Publication number
- CN204374951U CN204374951U CN201520054799.2U CN201520054799U CN204374951U CN 204374951 U CN204374951 U CN 204374951U CN 201520054799 U CN201520054799 U CN 201520054799U CN 204374951 U CN204374951 U CN 204374951U
- Authority
- CN
- China
- Prior art keywords
- register
- comparer
- door
- result
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The utility model relates to a kind of interruptable controller of neural network processor.Interruptable controller is by error comparator, iterative steps comparer, data bulk comparer, error e rror register, minimum precision Emin register, preset value maxepochs register, iterative steps counter, preset value num_data register, data counter, internal bus, with door, interrupt differentiating that register or door and external interrupt request output signal and form.The result of error comparator exports, the result of iterative steps comparer exports and differentiates that a position of register is connected with interruption simultaneously; The result of error comparator exports and is connected with door with the result output of iterative steps comparer; Export with the result of door and differentiate that a position of register is connected with interruption; The result of data bulk comparer exports and differentiates that a position of register is connected with interruption; Interrupt differentiate register four position all with or door be connected.
Description
Technical field
The utility model relates to Processing with Neural Network field, particularly the interruptable controller of neural network processor.
Background technology
Artificial neural network is widely used in the field such as Based Intelligent Control, pattern-recognition, and artificial neural network processor is the hardware platform realizing artificial neural network function.Artificial neural network processor will experience different working stages and state when carrying out work, and this just needs special control gear controls to guarantee processor work stability to it.Can be controlled by the mode of interrupting in embedded human artificial neural networks processor.The utility model design for be the interruptable controller of embedded neural network processor based on ARM microprocessor and FPGA, structure is simple, definite functions and stable.
Summary of the invention
The problem that the utility model design will solve is the interruption control problem of embedded neural network processor, and hardware design has that structure is simple, definite functions and stable feature, and Software for Design has succinct feature efficiently.
This interruptable controller is by error comparator, iterative steps comparer, data bulk comparer, error e rror register, minimum precision Emin register, preset value maxepochs register, iterative steps counter, preset value num_data register, data counter, internal bus, with door, interrupt differentiating that register or door and external interrupt request output signal and form.Wherein the result of error comparator exports and differentiates that a position of register is connected with interruption; The result of iterative steps comparer exports and differentiates that a position of register is connected with interruption; The result of error comparator exports and is connected with door with the result output of iterative steps comparer; Export with the result of door and differentiate that a position of register is connected with interruption; The result of data bulk comparer exports and differentiates that a position of register is connected with interruption; Interrupt differentiate register four position all with or door be connected; Error e rror register, minimum precision Emin register, preset value maxepochs register, iterative steps counter, preset value num_data register are all connected by internal bus with data counter.
Wherein said error comparator is used for judging whether neural metwork training meets precision conditions.If error e rror is not more than minimum precision Emin, meet network convergence condition, otherwise do not meet network convergence condition.
Described iterative steps comparer is used for the frequency of training judging whether network training reaches default.While not exceeding preset value maxepochs, precision conditions meets then network convergence, otherwise network is not restrained.
Described data bulk comparer is used for judging whether all operational datas are disposed.If be less than preset value num_data, then untreated complete, otherwise processed.
The more described error in judgement that is used for door compares and satisfies condition with iterative steps simultaneously.As the then network training convergence that satisfies condition simultaneously, otherwise do not restrain.
Described interruption differentiates that register is used for storing the result relevant to 3 comparers, and is used for asking external interrupt and providing ARM microprocessor as the foundation of interrupt type identification.
Described or door is used for producing unique interrupt request.3 comparers and 4 kinds of correlated results producing with door via or door after produce unique interrupt request.
Software for Design aspect, after ARM microprocessor enters interrupt service routine, according to interrupting differentiating that the value of register performs corresponding operation.
Accompanying drawing explanation
Fig. 1 is interrupt control apparatus structural representation
In Fig. 1,1 be error comparator, 2 are iterative steps comparers, 3 are data bulk comparers, 4 are error e rror registers, 5 are minimum precision Emin registers, 6 are preset value maxepochs registers, 7 are iterative steps counters, 8 are preset value num_data registers, 9 are data counters, 10 are internal buss, 11 is be interrupt differentiating that register, 13 is or door, 14 is that external interrupt request outputs signal with door, 12.
Embodiment
The interruption generation device of described neural network processor is by error comparator (1), iterative steps comparer (2), data bulk comparer (3), error e rror register (4), minimum precision Emin register (5), preset value maxepochs register (6), iterative steps counter (7), preset value num_data register (8), data counter (9), internal bus (10), with door (11), interrupt differentiating register (12), or door (13) and external interrupt request output signal (14) composition.
The result of described error comparator (1) exports and differentiates that a position of register (12) is connected with interruption; The result of iterative steps comparer (2) exports and differentiates that a position of register (12) is connected with interruption; The result of error comparator (1) exports and is connected with door (11) with the result output of iterative steps comparer (2); Export with the result of door (11) and differentiate that a position of register (12) is connected with interruption; The result of data bulk comparer (3) exports and differentiates that a position of register (12) is connected with interruption; Interrupt differentiate register (12) four position all with or door (13) be connected; Error e rror register (4), minimum precision Emin register (5), preset value maxepochs register (6), iterative steps counter (7), preset value num_data register (8) are connected with internal bus (10) with data counter (9).
The utility model can provide the interruption in two kinds of stages to control, and is network training stage, network working stage respectively.
The error signal e rror produced in the network training stage is delivered to error e rror register (4) and in error comparator (1), carries out size with the value in default minimum precision Emin register (5) and compare by internal bus (10).If the minimum precision Emin that error signal e rror > presets, then illustrate and do not meet accuracy requirement, comparer exports 0; Otherwise just meet accuracy requirement, comparer exports 1.
In the network training stage, the iterative steps signal produced by iterative steps counter (7) is carried out size with the value in preset value maxepochs register (6) and compares in iterative steps comparer (2).If the value > preset value maxepochs of iterative steps counter, then training time-out is described, comparer exports 0; Otherwise export 1.
When the output of error comparator (1) and iterative steps comparer (2) is 1 simultaneously, then the neural network network convergence of training; Otherwise network is not restrained.
At network working stage, neural network processor often processes one group of operational data, then data counter (9) adds 1.The value of data counter (9) is carried out size with the value in preset value num_data register (8) and is compared in data bulk comparer (3).If the value < preset value num_data of data counter, then illustrate that neural network processor is not yet finished the work, comparer exports 0; Otherwise then neural network processor is finished the work, comparer exports 1.
The value relevant to three comparers writes interrupts differentiating register (12).Interrupt differentiating that register (12) has four, the value of four is passed through or door (13) produces the external interrupt port that unique external interrupt request output signal (14) outputs to ARM microprocessor.As shown in Figure 1, according to order from top to down specify interrupt differentiate register (12) value as follows: on duty be 0100 time, training neural network convergence; On duty when being 1000,1010,0010, the neural network of training does not restrain; On dutyly represent that neural network processor is finished the work when being 0001; On dutyly represent neural network processor unfinished work when being 0000.
Claims (1)
1. the interruptable controller of a neural network processor, it is characterized in that: interruptable controller by error comparator, iterative steps comparer, data bulk comparer, error e rror register, minimum precision Emin register, preset value maxepochs register, iterative steps counter, preset value num_data register, data counter, internal bus, with door, interrupts differentiating that register or door and external interrupt request output signal and forms, wherein error comparator result output and interrupt differentiating that a position of register is connected; The result of iterative steps comparer exports and differentiates that a position of register is connected with interruption; The result of error comparator exports and is connected with door with the result output of iterative steps comparer; Export with the result of door and differentiate that a position of register is connected with interruption; The result of data bulk comparer exports and differentiates that a position of register is connected with interruption; Interrupt differentiate register four position all with or door be connected; Error e rror register, minimum precision Emin register, preset value maxepochs register, iterative steps counter, preset value num_data register are all connected by internal bus with data counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520054799.2U CN204374951U (en) | 2015-01-27 | 2015-01-27 | A kind of interruptable controller of neural network processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520054799.2U CN204374951U (en) | 2015-01-27 | 2015-01-27 | A kind of interruptable controller of neural network processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204374951U true CN204374951U (en) | 2015-06-03 |
Family
ID=53331152
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520054799.2U Expired - Fee Related CN204374951U (en) | 2015-01-27 | 2015-01-27 | A kind of interruptable controller of neural network processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204374951U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108154230A (en) * | 2016-12-05 | 2018-06-12 | 北京深鉴科技有限公司 | The monitoring method and monitoring device of deep learning processor |
-
2015
- 2015-01-27 CN CN201520054799.2U patent/CN204374951U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108154230A (en) * | 2016-12-05 | 2018-06-12 | 北京深鉴科技有限公司 | The monitoring method and monitoring device of deep learning processor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101833336B (en) | Dual-redundancy attitude control system and debug method of coaxial unmanned helicopter | |
| WO2015106582A1 (en) | Dsp/fpga-based dynamically-configurable tool intelligent controller, and control method | |
| CN105718257B (en) | Timer arrangement and timing method based on embedded system | |
| CN113119111A (en) | Mechanical arm and track planning method and device thereof | |
| CN104753439A (en) | PID (piping and instrument diagram) intelligent speed regulating method of electric motor | |
| CN204374951U (en) | A kind of interruptable controller of neural network processor | |
| CN106026156A (en) | Measured extinction angle detection method and detection system of DC power transmission system | |
| CN108037733B (en) | Numerical control machine tool debugging system and method | |
| CN201749341U (en) | Trajectory control card | |
| CN202975638U (en) | Configurable device for relay time of electromagnet needle selector | |
| CN103676965A (en) | Cantilever control method, device and system of engineering machine and engineering machine | |
| US10088812B2 (en) | Function unit, analog input unit, and programmable controller system | |
| CN204376367U (en) | The microcomputer protective relay device of automatic calibration function | |
| CN103624965A (en) | Meter-weight control system of plastic-pipe extruding equipment | |
| CN103516288A (en) | Self-adaptive encoder speed measuring device and method | |
| CN208621928U (en) | A kind of control device sent for CAN signal processing | |
| CN204856390U (en) | Modular can splice portable keyboard of computer | |
| CN105573292A (en) | Stage equipment performance matching test and debugging system | |
| CN111222228A (en) | Method for controlling working frequency of LLC (logical Link control) and terminal equipment | |
| CN106950848A (en) | A kind of nc machining simulation device based on tangle bintree model | |
| CN205375150U (en) | Realize PLC controlling means at FPGA platform | |
| Mu et al. | Fuzzy-LQR based anti-swing control of gantry crane | |
| CN204759195U (en) | Automobile -used sensor output circuit simulates | |
| CN204883211U (en) | Automatic excitation control unit of calibration function | |
| CN110781045B (en) | CPU IO interrupt performance testing device based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150603 Termination date: 20220127 |