CN205375150U - Realize PLC controlling means at FPGA platform - Google Patents
Realize PLC controlling means at FPGA platform Download PDFInfo
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- CN205375150U CN205375150U CN201620093635.5U CN201620093635U CN205375150U CN 205375150 U CN205375150 U CN 205375150U CN 201620093635 U CN201620093635 U CN 201620093635U CN 205375150 U CN205375150 U CN 205375150U
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Abstract
The utility model discloses a realize PLC controlling means at FPGA platform uses the IEC -61131 -3 standard on the FPGA -PLC, has overcome traditional PLC's closure and compatible subalternation shortcoming, is favorable to breaking high -end PLC producer monopolization situation, still utilize the characteristic of FPGA parallel execution for FPGA -PLC can the parallel execution PLC process, promoted PLC's real -time by a wide margin, FPGA's processing is the implementation procedure of pure hardware, makes the FPGA -PLC system have very high stability.
Description
Technical field
The invention belongs to microprocessor and control technical field, specifically one realizes PLC control device in FPGA platform.
Background technology
Programmable logic controller (PLC) PLC (ProgrammableLogicController) has been widely used in manufacture system for many years, the hard PLC of tradition is through the development of decades, having become as a mature technology, it is widely used at industrial control field with its high speed, high-performance, high reliability.But, the hard PLC of tradition has very big shortcoming: the product between production firm is mutually incompatible, lacks clearly consistent standard, it is difficult to build open hardware architecture；The programmed method difference of each vendor product is very big, and technology monopoly is relatively strong, and staff has to pass through the professional training of long period could grasp the programmed method of a certain kind product；The production of tradition PLC is monopolized by Ji Jia manufacturer, causes that PLC is expensive.Shortcoming Soft-PLC in order to improve the hard PLC of tradition is born, and Soft-PLC is based on the control system of the open architecture of IPC or EPC.The features such as it has the function of hard PLC, opening system structure, follow international industrial standard and actual industrial standard (such as IEC61131-3 standard and IEC61491 standard), can make full use of the resource of PC, higher data-handling capacity, friendly man machine interface.Soft-PLC utilizes software engineering that the Industrial PC of standard can convert to Full Featured PLC process controller.Soft-PLC can the function such as all round computer and the digital output modul of PLC, Analog control, mathematical operation, numerical value process, communication network, kernel is controlled, it is possible to provide powerful instruction set, accurately scan period, operate and connect the Open architecture of various I/O system and network reliably by multitask.Soft-PLC provides the function same with hard PLC, has been provided simultaneously with the various advantages of PC environment, and the relatively conventional PLC of Soft-PLC has a lot of advantage.But, Soft-PLC has a fatal shortcoming: Soft-PLC is a kind of software simulated implementation conventional hardware PLC control device controlling function, this causes that the real-time of Soft-PLC is much worse than the hard PLC of tradition, and at a lot of high-speed industrial control fields, Soft-PLC cannot requirement of real time.
Summary of the invention
For the shortcoming of prior art, the present invention provides a kind of and realizes PLC in FPGA platform and control device, utilizes the FPGA can the characteristic of executed in parallel program so that FPGA-PLC serial and concurrent mixing can perform PLC program so that the real-time of PLC is greatly improved.
The technical scheme realizing the object of the invention is:
A kind of method realizing PLC control in FPGA platform, comprises the steps:
1) PLC ladder diagram is generated；
2) the structured text file of IEC61131-3 standard is generated；
3) logic dependencies in PLC each row structured text is determined；
The structured text file that analytical procedure 2 obtains, obtains the dependence between PLC logic；
4) the concurrent scan model of FPGA process is set up；
The dependence produced by step 3 obtains the concurrent scan model of FPGA process；
5) realize structured text to change to FPGA；
Concurrent scan model realization structured text according to step 4 is changed to FPGA；
6) comprehensive generation FPGA firmware；
Use FPGA tool set by step 5) in combine with FPGA module realize IEC61131-3 basic function module storehouse carry out
Comprehensive generation FPGA firmware.
Step 3) in the definition of dependence: if the input parameter of B (logic arithmetic expression formula) comprises the output parameter of A (logic arithmetic expression formula), then B depends on A, and namely the output of A can affect the output of B.In Scan Architecture text, all logic arithmetic expression statements just can obtain the dependence between logic arithmetic expression formula, i.e. dependence between PLC logic:
Y1=X1ORX2 (1)
Y2=Y1ANDX3 (2)
Y3=X2ORY2ORX4 (3)
In formula: (1) (2) (3) are abstract 3 row structured text logic arithmetic expression formulas out, (1) what '=' left side Y1, Y2, the Y3 of (2) (3) represented is output variable, '=', X1, X2, Y1, X3, X2, Y2, X4 represented on the right is input variable, and OR logic or operator, AND are logic and operation symbols；
The input of each a line logic arithmetic expression formula extracted in structured text file and output variable, often extract input and the output variable of a line logic arithmetic expression formula, just distributing an initial value to new input and output variable is the enumerator of 1, by the numerical values recited of this enumerator, determine the dependence between the Different Logic arithmetical expression in structured text, first time extracts the input variable of formula (1): X1, X2, output variable is: Y1.Because the input variable of each row logic arithmetic expression formula is only with once, and output variable is used every time, so Y1 is put into keyword set, (keyword set is exactly the set of output variable of logic arithmetic expression formula, below collectively referred to as key word) in save, just start keyword set and be combined into sky
Initialize:
Y1_Count=1,
X1_Count=1,
X2_Count=1,
These three key word Counter Value, it is possible to calculate the value of current line logic arithmetic expression formula ID (number value of logic arithmetic expression formula), the computing formula of following ID is given below:
ID=Yx_Count=MAX{X1_Count ..., Xn_Count} (4)
In formula, ID: the number value of current line logic arithmetic expression formula；Yx_Count: in x represent 1 to the numeral of n；X1_Count ..., Xn_Count: represent the value of input key word enumerator；MAX{X1_Count ..., Xn_Count}: in MAX represent the maximum taking out all of key word count value；
Calculate with formula (4):
nullID=Yx_Count=MAX{X1_Count，X2_Count}=MAX{1,1}=1,So the ID=1 of the first row logic arithmetic expression formula,Now can the ID=1 of hold mode (1),When second time extracts formula (2) key word，According to the definition above relied on，What compare is the output key word of the input key word whether contained (1) of formula (2)，Owing to the output key word of formula (1) has all been put in keyword set，So the key word preserved in key word and keyword set that inputs having only to extraction formula (2) compares，See whether the input key word of formula (2) includes the key word in keyword set，If had, indicate dependence，Present keyword set has had a key word Y1，The input key word of formula (2) comprises the Y1 in keyword set，So there being dependence，Now need with the value of Y1_Count+1 replace that the value of Y1_Count calculates _ ID，So can guarantee that ID value that current line logic arithmetic expression formula calculates than it rely on ID value at least big 1，Thus ensureing to perform according to the order relied on；
nullThe ID value of calculating formula (2) is carried out below with formula (4)，The key word Y2 of extraction formula (2)、Y1、X3，Because in Y1 Already in keyword set，Explanation has dependence，So replacing the value of Y1_Count to calculate the ID value of current line with Y1_Count+1，ID=Y2_Count=MAX{Y1_Count+1，X3_Count}={2,1}=2，Now can the ID=2 of hold mode (2)，The ID=3 of formula (3) in like manner can be calculated according to the calculating process of formula (2)，The dependence of every a line logic arithmetic expression formula just can be determined either directly through ID numerical value: (1) ID=1 by ID value、(2) ID=2、(3) ID=3 illustrates that logic arithmetic expression formula execution sequence is that (1) → (2) → (3) perform in order，Execution sequence is to perform according to ID value order from small to large.
Step 4) in, every a line logic arithmetic expression formula can be mapped to an independent FPGA process.Each process beginning is a judgement about current process group number, only when current process group number is equal to certain constant, this process just starts effective work, this constant is considered a Process_ID, determining when a FPGA process is performed, the design is referred to as process group sequence number value.Process_ID and ID is numerically equal, as long as ID determines, Process_ID determines that.What Process_ID value was identical is considered same process group, the task parallelism work in same process group, say, that the meeting that Process_ID value is identical is executed simultaneously, in parallel；
In order to guarantee the concurrent process execution in order held water, an independent process is used to realize above-mentioned process group management function.Current process group number is mainly ceaselessly circulated incremental by this process: journey cur_pro_no (current process group number) value when FPGA resets is 0, otherwise when a upper process group terminates, cur_pro_no just increases certainly, until returning to 0 after arriving max_pro_no (maximum process group number) and recirculating, the time that one complete sweep cycle of FPGA-PLC is all performed equal to all process groups, the mode being incremented by by this process group number sequential loop realizes the function of the order concurrent scan execution program of PLC.Value that process group number is incremented to and when wherein Process_ID (numerically equal with ID value) value is equal, corresponding process will be performed.If there being the value that the Process_ID value of multirow process is incremented to process group identical, then the process that these a few row Process_ID values are identical is just executed in parallel.
Step 5) in, structured text uses boolean logical expression and module logic expression formula both expression formulas, and therefore transformation is also undertaken by both of these case；
Lower of boolean logical expression situation need to accord with, the boolean calculation expression formula in structured text, the logical operator directly replacing with Verilog language, and following table is exactly logical operator substitution table,
| Structured text | AND | OR | NOT | NOT(x1)AND(m0 OR x0) |
| Hardware description language | & | | | ~ | ～(x1) & (m0 | x0) |
Module logic expression formula in structured text is converted into an example of certain module in IEC61131-3 base library, and by the parameter needed for gauze transmission, such as structured text Counter module TON0 (IN:=NOT (x1) AND (m0ORx0), PT:=T#2000000ns) conversion Verilog language is exactly TONTON0 (sys_clk, sys_rstn, TON0_IN0_WIRE, TON0_OUT0_WIRE)；Wherein TON0 is an example of TON module；
This is according to the concurrent scan model of step 4 and step 5 structured text to VerilogHDL rule, it is achieved structured text is to the conversion of FPGA；
Step 6) in use FPGA tool set by step 5) in combine with FPGA module realize IEC61131-3 basic function module storehouse carry out comprehensively generation FPGA firmware；
One realizes PLC in FPGA platform and controls device, including output part, chip part, importation, port section and serial ports part；
Chip part is connected respectively with output part, importation, port section and serial ports part.
Output part, include output port, relay isolation circuit, output optical coupling isolation circuit, output port, relay isolation circuit, output optical coupling isolation circuit sequence connect, input optical coupling isolation circuit be also connected with the fpga chip of chip part；
Chip part, include fpga chip；
Importation, including input port, input optical coupling isolation circuit, input port is connected with input optical coupling isolation circuit, and input optical coupling is isolated circuit and is also connected with the fpga chip of chip part；
Port section, include debugging port；
Serial ports part, include communication serial port；
Beneficial effect:
The invention provides and a kind of realize the PLC method controlled and device in FPGA platform, IEC-61131-3 standard has been applied on FPGA-PLC, has overcome the shortcomings such as the tradition closure of PLC and poor compatibility, be conducive to breaking high-end PLC producer monopolization situation；Also utilize the characteristic of FPGA executed in parallel so that FPGA-PLC can executed in parallel PLC process, greatly improve the real-time of PLC, the process of FPGA be pure hardware realize process so that FPGA-PLC system has significantly high stability.
Accompanying drawing explanation
Fig. 1 this apparatus structure block diagram
Detailed description of the invention
Below in conjunction with drawings and Examples, present invention is further elaborated, but is not limitation of the invention
Embodiment
A kind of method realizing PLC control in FPGA platform, comprises the steps:
1) PLC ladder diagram is generated；
2) the structured text file of IEC61131-3 standard is generated；
3) logic dependencies in PLC each row structured text is determined；
The structured text file that analytical procedure 2 obtains, obtains the dependence between PLC logic；
4) the concurrent scan model of FPGA process is set up；
The dependence produced by step 3 obtains the concurrent scan model of FPGA process；
5) realize structured text to change to FPGA；
Concurrent scan model realization structured text according to step 4 is changed to FPGA；
6) comprehensive generation FPGA firmware；
Use FPGA tool set by step 5) in combine with FPGA module realize IEC61131-3 basic function module storehouse carry out comprehensively generation FPGA firmware.
Step 3) in the definition of dependence: if the input parameter of B (logic arithmetic expression formula) comprises the output parameter of A (logic arithmetic expression formula), then B depends on A, and namely the output of A can affect the output of B.In Scan Architecture text, all logic arithmetic expression statements just can obtain the dependence between logic arithmetic expression formula, i.e. dependence between PLC logic:
Y1=X1ORX2 (1)
Y2=Y1ANDX3 (2)
Y3=X2ORY2ORX4 (3)
In formula: (1) (2) (3) are abstract 3 row structured text logic arithmetic expression formulas out, (1) what '=' left side Y1, Y2, the Y3 of (2) (3) represented is output variable, '=', X1, X2, Y1, X3, X2, Y2, X4 represented on the right is input variable, and OR logic or operator, AND are logic and operation symbols；
The input of each a line logic arithmetic expression formula extracted in structured text file and output variable, often extract input and the output variable of a line logic arithmetic expression formula, just distributing an initial value to new input and output variable is the enumerator of 1, by the numerical values recited of this enumerator, determine the dependence between the Different Logic arithmetical expression in structured text, first time extracts the input variable of formula (1): X1, X2, output variable is: Y1.Because the input variable of each row logic arithmetic expression formula is only with once, and output variable is used every time, so Y1 is put into keyword set, (keyword set is exactly the set of output variable of logic arithmetic expression formula, below collectively referred to as key word) in save, just start keyword set and be combined into sky
Initialize:
Y1_Count=1,
X1_Count=1,
X2_Count=1,
These three key word Counter Value, it is possible to calculate the value of current line logic arithmetic expression formula ID (number value of logic arithmetic expression formula), the computing formula of following ID is given below:
ID=Yx_Count=MAX{X1_Count ..., Xn_Count} (4)
In formula, ID: the number value of current line logic arithmetic expression formula；Yx_Count: in x represent 1 to the numeral of n；X1_Count ..., Xn_Count: represent the value of input key word enumerator；MAX{X1_Count ..., Xn_Count}: in MAX represent the maximum taking out all of key word count value；
Calculate with formula (4):
nullID=Yx_Count=MAX{X1_Count，X2_Count}=MAX{1,1}=1,So the ID=1 of the first row logic arithmetic expression formula,Now can the ID=1 of hold mode (1),When second time extracts formula (2) key word，According to the definition above relied on，What compare is the output key word of the input key word whether contained (1) of formula (2)，Owing to the output key word of formula (1) has all been put in keyword set，So the key word preserved in key word and keyword set that inputs having only to extraction formula (2) compares，See whether the input key word of formula (2) includes the key word in keyword set，If had, indicate dependence，Present keyword set has had a key word Y1，The input key word of formula (2) comprises the Y1 in keyword set，So there being dependence，Now need with the value of Y1_Count+1 replace that the value of Y1_Count calculates _ ID，So can guarantee that ID value that current line logic arithmetic expression formula calculates than it rely on ID value at least big 1，Thus ensureing to perform according to the order relied on；
nullThe ID value of calculating formula (2) is carried out below with formula (4)，The key word Y2 of extraction formula (2)、Y1、X3，Because in Y1 Already in keyword set，Explanation has dependence，So replacing the value of Y1_Count to calculate the ID value of current line with Y1_Count+1，ID=Y2_Count=MAX{Y1_Count+1，X3_Count}={2,1}=2，Now can the ID=2 of hold mode (2)，The ID=3 of formula (3) in like manner can be calculated according to the calculating process of formula (2)，The dependence of every a line logic arithmetic expression formula just can be determined either directly through ID numerical value: (1) ID=1 by ID value、(2) ID=2、(3) ID=3 illustrates that logic arithmetic expression formula execution sequence is that (1) → (2) → (3) perform in order，Execution sequence is to perform according to ID value order from small to large.
Step 4) in, every a line logic arithmetic expression formula can be mapped to an independent FPGA process.Each process beginning is a judgement about current process group number, only when current process group number is equal to certain constant, this process just starts effective work, this constant is considered a Process_ID, determining when a FPGA process is performed, the design is referred to as process group sequence number value.Process_ID and ID is numerically equal, as long as ID determines, Process_ID determines that.What Process_ID value was identical is considered same process group, the task parallelism work in same process group, say, that the meeting that Process_ID value is identical is executed simultaneously, in parallel；
In order to guarantee the concurrent process execution in order held water, an independent process is used to realize above-mentioned process group management function.Current process group number is mainly ceaselessly circulated incremental by this process: journey cur_pro_no (current process group number) value when FPGA resets is 0, otherwise when a upper process group terminates, cur_pro_no just increases certainly, until returning to 0 after arriving max_pro_no (maximum process group number) and recirculating, the time that one complete sweep cycle of FPGA-PLC is all performed equal to all process groups, the mode being incremented by by this process group number sequential loop realizes the function of the order concurrent scan execution program of PLC.Value that process group number is incremented to and when wherein Process_ID (numerically equal with ID value) value is equal, corresponding process will be performed.If there being the value that the Process_ID value of multirow process is incremented to process group identical, then the process that these a few row Process_ID values are identical is just executed in parallel.
Step 5) in, structured text uses boolean logical expression and module logic expression formula both expression formulas, and therefore transformation is also undertaken by both of these case；
Lower of boolean logical expression situation need to accord with, the boolean calculation expression formula in structured text, the logical operator directly replacing with Verilog language, and following table is exactly logical operator substitution table,
| Structured text | AND | OR | NOT | NOT(x1)AND(m0 OR x0) |
| Hardware description language | & | | | ~ | ～(x1) & (m0 | x0) |
Module logic expression formula in structured text is converted into an example of certain module in IEC61131-3 base library, and by the parameter needed for gauze transmission, such as structured text Counter module TON0 (IN:=NOT (x1) AND (m0ORx0), PT:=T#2000000ns) conversion Verilog language is exactly TONTON0 (sys_clk, sys_rstn, TON0_IN0_WIRE, TON0_OUT0_WIRE)；Wherein TON0 is an example of TON module；
This is according to the concurrent scan model of step 4 and step 5 structured text to VerilogHDL rule, it is achieved structured text is to the conversion of FPGA；
Step 6) in use FPGA tool set by step 5) in combine with FPGA module realize IEC61131-3 basic function module storehouse carry out comprehensively generation FPGA firmware；
One realizes PLC in FPGA platform and controls device, including output part, chip part, importation, port section and serial ports part；
Chip part is connected respectively with output part, importation, port section and serial ports part.
Output part, include output port, relay isolation circuit, output optical coupling isolation circuit, output port, relay isolation circuit, output optical coupling isolation circuit sequence connect, input optical coupling isolation circuit be also connected with the fpga chip of chip part；
Chip part, include fpga chip；
Importation, including input port, input optical coupling isolation circuit, input port is connected with input optical coupling isolation circuit, and input optical coupling is isolated circuit and is also connected with the fpga chip of chip part；
Port section, include debugging port；
Serial ports part, include communication serial port；
As shown in Figure 1:
One realizes PLC in FPGA platform and controls device, including output part 1, chip part 2, importation 3, port section 4 and serial ports part 5；
Chip part 2 is connected respectively with output part 1, importation 3, port section 4 and serial ports part 5.
Output part 1, include output port 6, relay isolation circuit 7, output optical coupling isolation circuit 8, output port 6, relay isolation circuit 7, output optical coupling isolation circuit 8 are linked in sequence, and input optical coupling isolation circuit 8 is also connected with the fpga chip 9 of chip part 2；
Chip part 2, include fpga chip 9；
Importation 3, including input port 10, input optical coupling isolation circuit 11, input port 10 is connected with input optical coupling isolation circuit 11, and input optical coupling is isolated circuit 11 and is also connected with the fpga chip 9 of chip part 2；
Port section 4, include debugging port 12；
Serial ports part 5, include communication serial port 13.
Claims (3)
1. one kind realizes PLC control device in FPGA platform, it is characterised in that include output part, chip part, importation, port section and serial ports part；
Chip part is connected respectively with output part, importation, port section and serial ports part.
2. according to claim 1 FPGA platform realize PLC control device, it is characterized in that, output part includes output port, relay isolation circuit, output optical coupling isolation circuit, output port, relay isolation circuit, output optical coupling isolation circuit sequence connect, and input optical coupling isolation circuit is also connected with the fpga chip of chip part.
3. according to claim 1 FPGA platform realize PLC control device, it is characterized in that, importation, include input port, input optical coupling isolation circuit, input port is connected with input optical coupling isolation circuit, and input optical coupling isolation circuit is also connected with the fpga chip of chip part.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105511394A (en) * | 2016-01-29 | 2016-04-20 | 桂林电子科技大学 | Method and device for achieving PLC controlling in FPGA platform |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105511394A (en) * | 2016-01-29 | 2016-04-20 | 桂林电子科技大学 | Method and device for achieving PLC controlling in FPGA platform |
| CN105511394B (en) * | 2016-01-29 | 2018-06-29 | 桂林电子科技大学 | A kind of method for realizing PLC controls in FPGA platform |
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