CN204361121U

CN204361121U - A kind of LED chip with SiO2 sidewall PN junction protection process structure

Info

Publication number: CN204361121U
Application number: CN201520077175.2U
Authority: CN
Inventors: 宋超; 张振; 黎连佳
Original assignee: JIANGSU E-LITE SEMICONDUCTOR Co Ltd
Current assignee: JIANGSU E-LITE SEMICONDUCTOR Co Ltd
Priority date: 2015-02-03
Filing date: 2015-02-03
Publication date: 2015-05-27
Anticipated expiration: 2025-02-03

Abstract

The utility model discloses one and there is SiO ₂the LED chip of sidewall PN junction protection process structure; comprise substrate; be positioned at the N-type layer of substrate top surface; be positioned at the P-type layer of N-type layer upper surface; be positioned at the current barrier layer of P-type layer upper surface, be positioned at the current extending of current barrier layer upper surface, be positioned at the P electrode of current extending upper surface; be positioned at the N electrode of N-type layer upper surface, the upper surface at the edge of wherein said LED chip forms SiO ₂layer a, the P-type layer of edge, N-type layer carries out insulation protection; At described SiO ₂the upper surface of layer a forms SiO ₂layer b, with the SiO of insulation ₂the layer P-type layer of edge and N-type layer are carried out protecting and are completed to chip manufacturing, prevent from introducing polluting impurity and causing chip to leak electricity; The pollution impurity edge in remaining processing procedure effectively can be avoided to cause electric leakage, significantly can promote the electric leakage performance of large scale LED chip, increase product yield.

Description

A kind of LED chip with SiO2 sidewall PN junction protection process structure

Technical field

The utility model relates to technical field of semiconductor device, particularly relates to one and has SiO ₂the LED chip of sidewall PN junction protection process structure.

Background technology

In the manufacturing process of large scale LED chip, because its edge area is large, be easy to introduce contaminating impurity at chip surface, comprise each metal ion species, organic substance, inorganic matter ion etc., this contaminating impurity is easy to the PN joint walking around LED at chip edge, cause the electric leakage of chip, reduce the electric property of LED chip, reduce the quality of product.

In existing processing procedure, after ICP etching N type layer, because of P-type layer, the N-type layer close proximity at edge, so be easy to the electric leakage causing LED chip, fabrication steps is more, and the contaminating impurity possibility of introducing is larger, the electric leakage probability of the LED chip made is larger, and the yield of product is lower.

Utility model content

The purpose of this utility model is the defect overcoming prior art existence, improves one and has SiO ₂the LED chip of sidewall PN junction protection process structure.After the ICP etching of large scale LED chip, with the SiO of insulation ₂the P-type layer of exposure of layer edge and N-type layer are carried out protecting and are completed to chip manufacturing, the pollution impurity edge in remaining processing procedure effectively can be avoided to cause electric leakage, significantly can promote the electric leakage performance of large scale LED chip, increase product yield.

The utility model solves the technical scheme that its technical problem adopts: one has SiO ₂the LED chip of sidewall PN junction protection process structure; comprise substrate; be positioned at the N-type layer of substrate top surface; be positioned at the P-type layer of N-type layer upper surface; be positioned at the current barrier layer of P-type layer upper surface, be positioned at the current extending of current barrier layer upper surface, be positioned at the P electrode of current extending upper surface; be positioned at the N electrode of N-type layer upper surface, the upper surface at the edge of described LED chip forms SiO ₂layer a, the P-type layer of edge, N-type layer carries out insulation protection.

At described SiO ₂the upper surface of layer a forms SiO ₂layer b, with the SiO of insulation ₂the layer P-type layer of edge and N-type layer are carried out protecting and are completed to chip manufacturing, prevent from introducing polluting impurity and causing chip to leak electricity.

Further, described substrate is the one in sapphire, carborundum, gallium nitride, silicon materials.

Further, described current blocking layer material is SiO ₂.

Further, described SiO ₂layer a, thickness is 150 nanometers.

Further, described SiO ₂layer b, thickness is 78 nanometers.

Preparation technology of the present utility model, comprises the following steps:

After ICP etching, make the current barrier layer under above-mentioned P electrode;

When doing making current barrier layer, the SiO of preserving edge ₂layer a, the P-type layer of edge, N-type layer carries out insulation protection;

At described SiO ₂the upper surface of layer a makes SiO ₂layer b, prevents introducing pollution impurity and causes chip to leak electricity.

Beneficial effect: the utility model solves the defect existed in background technology, has 2 layers of SiO at edge ₂layer, i.e. SiO ₂layer a and SiO ₂layer b, SiO ₂layer a, after ICP etches processing procedure, protects chip edge always, prevents introducing pollution impurity and causes chip to leak electricity.The LED chip that technique of the present invention is made is on electric leakage yield, higher than existing common process by 9.88%.

Accompanying drawing explanation

Below in conjunction with accompanying drawing, the utility model is described in further detail.

Fig. 1 is the structural representation of existing LED chip;

Wherein: 101 is substrate, 102 is N-type layer, and 103 is P-type layer, and 104 is current barrier layer, and 105 is current extending, and 106 is P electrode, and 107 is N electrode, and 108 is SiO ₂layer b.

Fig. 2 is that the utility model one has SiO ₂the structural representation of the LED chip of sidewall PN junction protection process structure.

Wherein: 201 is substrate, 202 is N-type layer, and 203 is P-type layer, and 204 is current barrier layer, and 205 is current extending, and 206 is P electrode, and 207 is N electrode, and 208 is SiO ₂layer a, 209 is SiO ₂layer b.

Embodiment

Provide this practical embodiment below in conjunction with accompanying drawing, embodiment is provided.

As shown in Figure 2, the utility model provides one to have SiO ₂the LED chip of sidewall PN junction protection process structure; comprise substrate 201; be positioned at the N-type layer 202 of substrate top surface; be positioned at the P-type layer 203 of N-type layer 202 upper surface; be positioned at the current barrier layer 204 of P-type layer 203 upper surface, be positioned at the current extending 205 of current barrier layer 204 upper surface, be positioned at the P electrode 206 of current extending 205 upper surface; be positioned at the N electrode 207 of N-type layer 202 upper surface, the upper surface at the edge of described LED chip forms SiO ₂layer a 208, the P-type layer 203 of edge, N-type layer 202 carries out insulation protection.

Wherein, at described SiO ₂the upper surface of layer a 208 forms SiO ₂layer b 209, with the SiO of insulation ₂the layer P-type layer 203 of edge and N-type layer 202 are carried out protecting and are completed to chip manufacturing, prevent from introducing polluting impurity and causing chip to leak electricity.

Wherein, described substrate 201 is the one in sapphire, carborundum, gallium nitride, silicon materials; Described current barrier layer 204 material is SiO ₂; Described SiO ₂layer a 208, thickness is 150 nanometers; Described SiO ₂layer b 209, thickness is 78 nanometers.

After ICP etching, make the current barrier layer 204 under above-mentioned P electrode 206;

When doing making current barrier layer 204, the SiO of preserving edge ₂layer a 208, the P-type layer 203 of edge, N-type layer 202 carries out insulation protection;

At described SiO ₂the upper surface of layer a 208 makes SiO ₂layer b 209, prevents introducing pollution impurity and causes chip to leak electricity.

Should be appreciated that specific embodiment described above only for explaining the utility model, and be not used in restriction the utility model.Still be among protection range of the present utility model by spirit institute's apparent change of extending out of the present utility model or change.

Claims

1. one kind has the LED chip of SiO2 sidewall PN junction protection process structure, it is characterized in that: comprise substrate, be positioned at the N-type layer of substrate top surface, be positioned at the P-type layer of N-type layer upper surface, be positioned at the current barrier layer of P-type layer upper surface, be positioned at the current extending of current barrier layer upper surface, be positioned at the P electrode of current extending upper surface, be positioned at the N electrode of N-type layer upper surface, the upper surface at the edge of described LED chip forms SiO2 layer a; SiO2 layer b is formed at the upper surface of described SiO2 layer a.

2. a kind of LED chip with SiO2 sidewall PN junction protection process structure according to claim 1, is characterized in that: described substrate is the one in sapphire, carborundum, gallium nitride, silicon materials.

3. a kind of LED chip with SiO2 sidewall PN junction protection process structure according to claim 1, is characterized in that: described current blocking layer material is SiO2.

4., according to the arbitrary described a kind of LED chip with SiO2 sidewall PN junction protection process structure of claims 1 to 3, it is characterized in that: described SiO2 layer a thickness is 150 nanometers.

5., according to the arbitrary described a kind of LED chip with SiO2 sidewall PN junction protection process structure of claims 1 to 3, it is characterized in that: described SiO2 layer b thickness is 78 nanometers.