CN204330877U - A kind of automatic blood analyzer gem hole voltage Intelligent detection circuit - Google Patents
A kind of automatic blood analyzer gem hole voltage Intelligent detection circuit Download PDFInfo
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- CN204330877U CN204330877U CN201520033366.9U CN201520033366U CN204330877U CN 204330877 U CN204330877 U CN 204330877U CN 201520033366 U CN201520033366 U CN 201520033366U CN 204330877 U CN204330877 U CN 204330877U
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Abstract
The utility model discloses a kind of automatic blood analyzer gem hole voltage Intelligent detection circuit, and this circuit comprises gem hole JP1 voltage-dividing detection circuit, gem hole JP2 voltage-dividing detection circuit, gem hole voltage detecting gating circuit and gem hole voltage A/D change-over circuit; Gem hole JP1 voltage-dividing detection circuit and gem hole JP2 voltage-dividing detection circuit are connected respectively to the input end of gem hole voltage detecting gating circuit, the output terminal of gem hole voltage detecting gating circuit is by after the input end that is connected to A/D change-over circuit, convert simulating signal to digital signal through A/D conversion, finally pass to FPGA controller.The utility model has the advantage of: realize processing two-way gem hole voltage signal by circuit mode, to the I/O interface resource effect of being very helpful of saving FPGA, simultaneously can detect gem hole voltage rapidly, to judging whether gem hole plug-hole is very helpful effect.
Description
Technical field
The utility model relates to Medical Instruments, particularly the gem hole voltage intelligent detecting method of blood analyser.
Background technology
Blood analyser is one of instrument of hospital clinical inspection widespread use.Under electrical impedance counting principle, the recognition effect of analyser on hemocyte pulse signal is the key factor affecting its precision index.Can gem hole whether unobstructed, directly affects blood analyser and normally detect haemocyte.By the detection to gem hole voltage, can detect that whether voltage on gem hole is normal fast, thus judge gem hole whether plug-hole.
Traditional blood analyser gem hole voltage detecting circuit, occupy the I/O mouth resource of more FPGA or MCU, gem hole voltage is obtained by the detection of single channel, relatively loaded down with trivial details in detection, A/D transfer process, dirigibility is not high enough, can not meet and detect gem hole voltage fast, impact is existed on the analysis speed of blood analyser entirety.
Summary of the invention
The purpose of this utility model is for the deficiencies in the prior art, devise that one to be applied in blood analyser simply, gem hole voltage intelligent detecting method efficiently, can detect two-way gem hole voltage detecting circuit and make corresponding A/D and change, thus overcome the defect of above-mentioned recognition methods, therefore improve the reliability of instrument.
Thinking of the present utility model is: in order to save the I/O mouth resource of FPGA, utilize the effect of single eight path analoging switch pio chips, by the control signal of FPGA, gating output is carried out to two-way or plurality of voltages signal, and make corresponding A/D and change, finally digital signal is passed to FPGA, realize gem hole voltage Intelligent Measurement fast.
The utility model is achieved through the following technical solutions:
A kind of automatic blood analyzer gem hole voltage Intelligent detection circuit, this circuit comprises gem hole JP1 voltage-dividing detection circuit, gem hole JP2 voltage-dividing detection circuit, gem hole voltage detecting gating circuit and gem hole voltage A/D change-over circuit; Gem hole JP1 voltage-dividing detection circuit and gem hole JP2 voltage-dividing detection circuit are connected respectively to the input end of gem hole voltage detecting gating circuit, the output terminal of gem hole voltage detecting gating circuit is by after the input end that is connected to A/D change-over circuit, convert simulating signal to digital signal through A/D conversion, finally pass to FPGA controller.
Furtherly, when after system electrification, gem hole JP1, gem hole JP2 voltage-dividing detection circuit carry out dividing potential drop detection to gem hole JP1, gem hole JP2 simultaneously, gem hole voltage detecting gating circuit exports gem hole voltage signal by the control signal gating of FPGA after obtaining voltage signal from the output terminal of gem hole JP1 voltage-dividing detection circuit, gem hole JP2 voltage-dividing detection circuit simultaneously; After gem hole voltage A/D change-over circuit receives gem hole voltage signal, analog quantity is converted to digital quantity and sends to FPGA processor, form a gem hole voltage Intelligent detection circuit.
Described gem hole JP1 voltage-dividing detection circuit comprises resistance R25, resistance R26, resistance R27, resistance R66, resistance R67, electric capacity C70, electric capacity C71, electric capacity C72, gem hole JP1, analog switch chip U13 and operational amplifier chip U14; + 60V direct supply is by connecting with gem hole JP1 after connecting ground connection with resistance R66, resistance R67 again; Ground connection after resistance R66 is connected with the positive pole of electric capacity C70 with the common port of resistance R67, electric capacity C70 two ends are in parallel with electric capacity C71 two ends, and electric capacity C72 two ends are in parallel with the two ends of gem hole JP1; Gem hole JP1, electric capacity C72 connect 8 ports of analog switch chip U13 after connecting with resistance R27 with the common port of resistance R67,2 ports of analog switch chip U13 are by rear ground connection of connecting with resistance R26,6 ports meet the control signal VAC of FPGA, the direct ground connection of 3 port of analog switch chip U13,4 ports of analog switch chip U13 meet+12V, 5 ports of analog switch chip U13 meet+5V, and 7 ports meet-12V, 1 port connect with resistance R25 after ground connection; 3 ports of 1 port of analog switch chip U13 and the public termination operational amplifier chip U14 of resistance R25,7 ports of operational amplifier chip U14 meet+12V, 4 ports of operational amplifier chip U14 meet-12V, 1 port of operational amplifier chip U14,5 ports, 8 ports are unsettled, are the output VOUT1 of gem hole JP1 voltage-dividing detection circuit after 6 ports of operational amplifier chip U14 are connected with 2 ports.
When this circuit working, the enable analog switch chip U13 of FPGA control signal VAC, the dividing potential drop of gem hole JP1 be in parallel with gem hole JP1 again after resistance R27 connects with resistance R25 after the voltage of equivalent resistance, namely equivalent resistance connect with resistance R66, resistance R67 after dividing potential drop under 60V direct supply, so gem hole JP1 dividing potential drop
1 port of analog switch chip U13 and the public termination of resistance R25 play the operation amplifier chip U14 input end of pressure stabilization function, the output end voltage of gem hole JP1 voltage-dividing detection circuit
Described gem hole JP2 voltage-dividing detection circuit by resistance R28, resistance R29, resistance R30, resistance R87, resistance R88, electric capacity C89, electric capacity C90, electric capacity C91, gem hole JP2, analog switch chip U15 and operational amplifier chip U16 form; + 60V direct supply is by connecting with gem hole JP2 after connecting ground connection with resistance R87, resistance R88 again; Ground connection after resistance R87 is connected with the positive pole of electric capacity C89 with the common port of resistance R88, electric capacity C89 two ends are in parallel with electric capacity C90 two ends, and electric capacity C91 two ends are in parallel with the two ends of gem hole JP2; Gem hole JP2, electric capacity C91 connect 8 ports of analog switch chip U15 after connecting with resistance R30 with the common port of resistance R88,2 ports of analog switch chip U15 are by rear ground connection of connecting with resistance R29,6 ports of analog switch chip U15 meet the control signal VAC of FPGA, the direct ground connection of 3 port of analog switch chip U15,4 ports of analog switch chip U15 meet+12V, 5 ports of analog switch chip U15 meet+5V, 7 ports of analog switch chip U15 meet-12V, 1 port of analog switch chip U15 connect with resistance R28 after ground connection; 3 ports of 1 port of analog switch chip U15 and the public termination operational amplifier chip U16 of resistance R28; 7 ports of operational amplifier chip U16 meet+12V, 4 ports of operational amplifier chip U16 meet-12V, 1 port of operational amplifier chip U16,5 ports, 8 ports are unsettled, are the output VOUT2 of gem hole JP2 voltage-dividing detection circuit after 6 ports of operational amplifier chip U16 are connected with 2 ports.
When this circuit working, the enable analog switch chip U15 of FPGA control signal VAC, the dividing potential drop of gem hole JP2 be in parallel with gem hole JP2 again after resistance R30 connects with resistance R28 after the voltage of equivalent resistance, namely equivalent resistance connect with resistance R87, resistance R88 after dividing potential drop under 60V direct supply, so gem hole JP2 dividing potential drop
1 port of analog switch chip U15 and the public termination of resistance R28 play the operation amplifier chip U16 input end of pressure stabilization function, the output end voltage of gem hole JP2 voltage-dividing detection circuit
Described gem hole voltage detecting gating circuit is made up of single eight path analoging switch chip U52, 5 ports of single eight path analoging switch chip U52 meet the output VOUT1 of gem hole JP1 voltage-dividing detection circuit, 4 ports of single eight path analoging switch chip U52 meet the output VOUT2 of gem hole JP2 voltage-dividing detection circuit, 9 ports of single eight path analoging switch chip U52 meet the control gating signal VC1 of FPGA, 10 ports of single eight path analoging switch chip U52 meet the control gating signal VC2 of FPGA, 11 ports of single eight path analoging switch chip U52 meet the control gating signal VC3 of FPGA, 16 ports of single eight path analoging switch chip U52 meet+5V, 6 of single eight path analoging switch chip U52, 7, ground connection after 8 ports are connected, 1 of single eight path analoging switch chip U52, 2, 12, 13, 14, 15 ports are unsettled, 3 ports of single eight path analoging switch chip U52 are the gem hole detectable voltage signals output VOUT0 of gating.
9,10,11 ends of FPGA control signal VC1, VC2, VC3 difference order eight path analoging switch chip U52, and with the set time in turn gating gem hole JP1, gem hole JP2 voltage-dividing detection circuit output signal to gem hole voltage A/D change-over circuit, realize processing in real time in turn two-way voltage signal.
Described gem hole voltage A/D change-over circuit is by operational amplifier chip U53, and A/D conversion chip U47, resistance R134, electric capacity C120, electric capacity C121 and stabilivolt D17 form; 3 ports of operation amplifier chip U53 export VOUT0 with the voltage of gem hole voltage detecting gating circuit and are connected, 4 ports of operation amplifier chip U53 meet-12V, 7 ports of operation amplifier chip U53 meet+12V, 1 port of operation amplifier chip U53,5 ports and 8 ports are unsettled, with 3 ports of A/D conversion chip U47 are connected after connecting after 6 ports of operation amplifier chip U53 are connected with 2 ports with resistance R134 again; The negative pole of stabilivolt D17 connects 2 ports of U53 and the common port of 6 ports, its plus earth, 1 port of A/D conversion chip U47 connects+5V power supply, ground connection after 1 port of A/D conversion chip U47 and the common port of+5V are connected with the positive pole of electric capacity C121, electric capacity C120 is connected in parallel on the two ends of electric capacity C121, the 2 port ground connection of A/D conversion chip U47, and 4 ports meet the A/D clock signal AD_CLK of FPGA, 5 ports meet the A/D data-signal AD_DATA of FPGA, and 6 ports meet the A/D chip selection signal AD_CS of FPGA.
After the output VOUT0 of gem hole voltage detecting gating circuit has connected 3 ports of operation amplifier chip U53 of pressure stabilization function, voltage signal is input to A/D conversion chip U47; Under the chip selection signal AD_CS of FPGA and the effect of clock signal AD_CLK, convert digital quantity to through A/D conversion chip U47 and pass to FPGA process from 5 ports.
The utility model has the advantage of: realize processing two-way gem hole voltage signal by circuit mode, to the I/O interface resource effect of being very helpful of saving FPGA, simultaneously can detect gem hole voltage rapidly, to judging whether gem hole plug-hole is very helpful effect.
Accompanying drawing explanation
Fig. 1 is structured flowchart of the present utility model;
Fig. 2 is gem hole JP1 voltage-dividing detection circuit of the present utility model;
Fig. 3 is gem hole JP2 voltage-dividing detection circuit of the present utility model;
Fig. 4 is gem hole voltage detecting gating circuit of the present utility model;
Fig. 5 is gem hole voltage A/D change-over circuit of the present utility model.
Embodiment
The present invention will by reference to the accompanying drawings, is described further by following examples.
Embodiment.
Accompanying drawing 1 is the structured flowchart of the utility model gem hole voltage Intelligent detection circuit.Form primarily of FPGA, gem hole JP1 voltage-dividing detection circuit, gem hole JP2 voltage-dividing detection circuit, gem hole voltage detecting gating circuit and gem hole voltage A/D change-over circuit.The wherein input end of the output termination gem hole voltage detecting gating circuit of gem hole JP1 voltage-dividing detection circuit, gem hole JP2 voltage-dividing detection circuit, the output termination gem hole voltage A/D change-over circuit input end of gem hole voltage detecting gating circuit, last FPGA is connected with the control end of gem hole voltage A/D change-over circuit with gem hole JP1, gem hole JP2 voltage-dividing detection circuit, thus makes whole circuit become as a whole.
Accompanying drawing 2 is gem hole JP1 voltage-dividing detection circuit figure of the present utility model.Gem hole JP1 voltage-dividing detection circuit by resistance R25, resistance R26, resistance R27, resistance R66, resistance R67, electric capacity C70, electric capacity C71, electric capacity C72, gem hole JP1, analog switch chip U13 and operational amplifier chip U14 form; Wherein resistance R25 is 50K Ω, resistance R26 is 1K Ω, resistance R27 is 1M Ω, resistance R66 is 4.7K Ω, and resistance R67 is the resistance of 56K Ω, and electric capacity C70 is 10uF, electric capacity C71 is 100nF, electric capacity C72 is the electric capacity of 50pF, and U13 is DG419DY analog switch chip, and U14 is TL081C operational amplifier.+ 60V direct supply is by connecting with gem hole JP1 after connecting ground connection with resistance R66, resistance R67 again; Ground connection after resistance R66 is connected with the positive pole of electric capacity C70 with the common port of resistance R67, electric capacity C70 two ends are in parallel with electric capacity C71 two ends, and electric capacity C72 two ends are in parallel with the two ends of gem hole JP1; Gem hole JP1, electric capacity C72 connect 8 ports of analog switch chip U13 after connecting with resistance R27 with the common port of resistance R67,2 ports of analog switch chip U13 are by rear ground connection of connecting with resistance R26,6 ports meet the control signal VAC of FPGA, the direct ground connection of 3 port, 4 ports meet+12V, 5 ports meet+5V, and 7 ports meet-12V, 1 port connect with resistance R25 after ground connection; 3 ports of 1 port of analog switch chip U13 and the public termination operational amplifier chip U14 of resistance R25,7 ports of operational amplifier chip U14 meet+12V, 4 ports meet-12V, 1 port, 5 ports, 8 ports are unsettled, and 6 ports are the output VOUT1 of gem hole JP1 voltage-dividing detection circuit after being connected with 2 ports.
After circuit powers on, the enable analog switch chip U13 of FPGA control signal VAC, when FPGA control signal VAC control simulation switch chip U13 is connected to S1, resistance R25 is connected with resistance R26 ground connection, the voltage that now testing circuit exports is 0V, when being connected to S2 the dividing potential drop of gem hole JP1 be in parallel with gem hole JP1 again after resistance R27 connects with resistance R25 after the voltage of equivalent resistance, namely equivalent resistance connect with resistance R66, resistance R67 after dividing potential drop under 60V direct supply, its resistance
the normal Standard resistance range of gem hole JP1 is: 10K Ω-20K Ω.Therefore be 8.4-14.1V in the dividing potential drop of normal not plug-hole state lowerside stone hole JP1, the output end voltage of gem hole JP1 voltage-dividing detection circuit
namely the output terminal output voltage of normal not plug-hole state lowerside stone hole voltage-dividing detection circuit is 0.4-0.7V.
Accompanying drawing 3 is gem hole JP2 voltage-dividing detection circuit figure of the present utility model.Gem hole JP2 voltage-dividing detection circuit by resistance R28, resistance R29, resistance R30, resistance R87, resistance R90, electric capacity C89, electric capacity C90, electric capacity C91, gem hole JP2, analog switch chip U15 and operational amplifier chip U16 form; Wherein resistance R28 is 50K Ω, resistance R29 is 1K Ω, resistance R30 is 1M Ω, resistance R87 is 10K Ω, and resistance R88 is the resistance of 100K Ω, and electric capacity C89 is 10uF, electric capacity C90 is 100nF, electric capacity C91 is the electric capacity of 50pF, and U15 is DG419DY analog switch chip, and U16 is TL081C operational amplifier.+ 60V direct supply is by connecting with gem hole JP2 after connecting ground connection with resistance R87, resistance R88 again; Ground connection after resistance R87 is connected with the positive pole of electric capacity C89 with the common port of resistance R88, electric capacity C90 two ends are in parallel with electric capacity C89 two ends, and electric capacity C91 two ends are in parallel with the two ends of gem hole JP2; Gem hole JP2, electric capacity C91 connect 8 ports of analog switch chip U15 after connecting with resistance R30 with the common port of resistance R88,2 ports of analog switch chip U15 are by rear ground connection of connecting with resistance R29,6 ports meet the control signal VAC of FPGA, the direct ground connection of 3 port, 4 ports meet+12V, 5 ports meet+5V, and 7 ports meet-12V, 1 port connect with resistance R28 after ground connection; 3 ports of 1 port of analog switch chip U15 and the public termination operational amplifier chip U16 of resistance R28,7 ports of operational amplifier chip U16 meet+12V, 4 ports meet-12V, 1 port, 5 ports, 8 ports are unsettled, and 6 ports are the output VOUT2 of gem hole JP2 voltage-dividing detection circuit after being connected with 2 ports.
After circuit powers on, the enable analog switch chip U15 of FPGA control signal VAC, when FPGA control signal VAC control simulation switch chip U15 is connected to S1, resistance R28 is connected with resistance R29 ground connection, the voltage that now testing circuit exports is 0V, when being connected to S2 the dividing potential drop of gem hole JP2 be in parallel with gem hole JP2 again after resistance R28 connects with resistance R30 after the voltage of equivalent resistance, namely equivalent resistance connect with resistance R87, resistance R88 after dividing potential drop under 60V direct supply, its resistance
the normal Standard resistance range of gem hole JP2 is: 30K Ω-50K Ω.Therefore be 12.5-18.2V in the dividing potential drop of normal not plug-hole state lowerside stone hole JP2, the output end voltage of gem hole JP2 voltage-dividing detection circuit
namely the output terminal output voltage of normal not plug-hole state lowerside stone hole JP2 voltage-dividing detection circuit is 0.60-0.87V.
Accompanying drawing 4 is the utility model gem hole voltage gating circuit, is made up of single eight path analoging switch chip U52, and single eight path analoging switch chip U52 are CD4051; 5 ports of single eight path analoging switch chip U52 meet the output terminal VOUT1 of gem hole JP1 voltage-dividing detection circuit, 4 ports meet the output terminal VOUT2 of gem hole JP2 voltage-dividing detection circuit, 9 ports meet the control gating signal VC1 of FPGA, 10 ports meet the control gating signal VC2 of FPGA, 11 ports meet the control gating signal VC3 of FPGA, 16 ports meet+5V, 6, the connected rear ground connection of 7,8 ports, 1,2,12,13,14,15 ports are unsettled, and 3 ports are that the gem hole detectable voltage signals of gating exports VOUT0.
Under the control of FPGA, by control gating signal VC1, VC2, VC3 of three road FPGA, with the output voltage of set time gating gem hole JP1 voltage detecting circuit, gem hole JP2 voltage detecting circuit, achieve like this and the object that A/D change-over circuit processes is outputted in turn in real time to two-way gem hole voltage.
Fig. 5 is gem hole voltage A/D change-over circuit of the present utility model, by pressure stabilization function operational amplifier chip U53, A/D conversion chip U47, resistance R134, electric capacity C120, electric capacity C121 and stabilivolt D17 form; Wherein operational amplifier chip U53 is TL081C voltage stabilizing chip; A/D conversion chip U47 is ADS7883A/D conversion chip; resistance R134 is the resistance of 100 Ω; electric capacity C120 is the electric capacity of 100nF, electric capacity C121 is the electric capacity of 10uF; stabilivolt D17 plays pressure stabilization function, and protection A/D conversion chip U47 is because of the too high damage of input voltage.
3 ports of operation amplifier chip U53 export VOUT0 with the voltage of gem hole voltage detecting gating circuit and are connected, 4 ports meet-12V, 7 ports meet+12V, and 1 port, 5 ports and 8 ports are unsettled, and 6 ports are connected with 3 ports of A/D conversion chip U47 after connecting with resistance R134 after being connected with 2 ports again; The negative pole of stabilivolt D17 connects 2 ports of operation amplifier chip U53 and the common port of 6 ports, its plus earth, 1 port of A/D conversion chip U47 connects+5V power supply, ground connection after 1 port of U47 and the common port of+5V are connected with the positive pole of C121, C120 is connected in parallel on the two ends of C121, the 2 port ground connection of A/D conversion chip U47, and 4 ports meet the A/D clock signal AD_CLK of FPGA, 5 ports meet the A/D data-signal AD_DATA of FPGA, and 6 ports meet the A/D chip selection signal AD_CS of FPGA.
After voltage gating circuit output VOUT0 is connected to the input end of A/D change-over circuit, after the pressure stabilization function of operational amplifier chip U53, after matching connection resistance R134 under the chip selection signal AD_CS of FPGA and the double action of clock signal AD_CLK, convert digital quantity to through A/D conversion chip U47 and pass to FPGA process from 5 ports.
Claims (5)
1. an automatic blood analyzer gem hole voltage Intelligent detection circuit, is characterized in that: this circuit comprises gem hole JP1 voltage-dividing detection circuit, gem hole JP2 voltage-dividing detection circuit, gem hole voltage detecting gating circuit and gem hole voltage A/D change-over circuit; Gem hole JP1 voltage-dividing detection circuit and gem hole JP2 voltage-dividing detection circuit are connected respectively to the input end of gem hole voltage detecting gating circuit, the output terminal of gem hole voltage detecting gating circuit is by after the input end that is connected to A/D change-over circuit, convert simulating signal to digital signal through A/D conversion, finally pass to FPGA controller.
2. automatic blood analyzer gem hole voltage Intelligent detection circuit according to claim 1, is characterized in that: described gem hole JP1 voltage-dividing detection circuit comprises resistance R25, resistance R26, resistance R27, resistance R66, resistance R67, electric capacity C70, electric capacity C71, electric capacity C72, gem hole JP1, analog switch chip U13 and operational amplifier chip U14; + 60V direct supply is by connecting with gem hole JP1 after connecting ground connection with resistance R66, resistance R67 again; Ground connection after resistance R66 is connected with the positive pole of electric capacity C70 with the common port of resistance R67, electric capacity C70 two ends are in parallel with electric capacity C71 two ends, and electric capacity C72 two ends are in parallel with the two ends of gem hole JP1; Gem hole JP1, electric capacity C72 connect 8 ports of analog switch chip U13 after connecting with resistance R27 with the common port of resistance R67,2 ports of analog switch chip U13 are by rear ground connection of connecting with resistance R26,6 ports meet the control signal VAC of FPGA, the direct ground connection of 3 port of analog switch chip U13,4 ports of analog switch chip U13 meet+12V, 5 ports of analog switch chip U13 meet+5V, and 7 ports meet-12V, 1 port connect with resistance R25 after ground connection; 3 ports of 1 port of analog switch chip U13 and the public termination operational amplifier chip U14 of resistance R25,7 ports of operational amplifier chip U14 meet+12V, 4 ports of operational amplifier chip U14 meet-12V, 1 port of operational amplifier chip U14,5 ports, 8 ports are unsettled, are the output VOUT1 of gem hole JP1 voltage-dividing detection circuit after 6 ports of operational amplifier chip U14 are connected with 2 ports.
3. automatic blood analyzer gem hole voltage Intelligent detection circuit according to claim 1, it is characterized in that: described gem hole JP2 voltage-dividing detection circuit is by resistance R28, resistance R29, resistance R30, resistance R87, resistance R88, electric capacity C89, electric capacity C90, electric capacity C91, gem hole JP2, analog switch chip U15 and operational amplifier chip U16 form; + 60V direct supply is by connecting with gem hole JP2 after connecting ground connection with resistance R87, resistance R88 again; Ground connection after resistance R87 is connected with the positive pole of electric capacity C89 with the common port of resistance R88, electric capacity C89 two ends are in parallel with electric capacity C90 two ends, and electric capacity C91 two ends are in parallel with the two ends of gem hole JP2; Gem hole JP2, electric capacity C91 connect 8 ports of analog switch chip U15 after connecting with resistance R30 with the common port of resistance R88,2 ports of analog switch chip U15 are by rear ground connection of connecting with resistance R29,6 ports of analog switch chip U15 meet the control signal VAC of FPGA, the direct ground connection of 3 port of analog switch chip U15,4 ports of analog switch chip U15 meet+12V, 5 ports of analog switch chip U15 meet+5V, 7 ports of analog switch chip U15 meet-12V, 1 port of analog switch chip U15 connect with resistance R28 after ground connection; 3 ports of 1 port of analog switch chip U15 and the public termination operational amplifier chip U16 of resistance R28; 7 ports of operational amplifier chip U16 meet+12V, 4 ports of operational amplifier chip U16 meet-12V, 1 port of operational amplifier chip U16,5 ports, 8 ports are unsettled, are the output VOUT2 of gem hole JP2 voltage-dividing detection circuit after 6 ports of operational amplifier chip U16 are connected with 2 ports.
4. automatic blood analyzer gem hole voltage Intelligent detection circuit according to claim 1, is characterized in that: described gem hole voltage detecting gating circuit is made up of single eight path analoging switch chip U52, 5 ports of single eight path analoging switch chip U52 meet the output VOUT1 of gem hole JP1 voltage-dividing detection circuit, 4 ports of single eight path analoging switch chip U52 meet the output VOUT2 of gem hole JP2 voltage-dividing detection circuit, 9 ports of single eight path analoging switch chip U52 meet the control gating signal VC1 of FPGA, 10 ports of single eight path analoging switch chip U52 meet the control gating signal VC2 of FPGA, 11 ports of single eight path analoging switch chip U52 meet the control gating signal VC3 of FPGA, 16 ports of single eight path analoging switch chip U52 meet+5V, 6 of single eight path analoging switch chip U52, 7, ground connection after 8 ports are connected, 1 of single eight path analoging switch chip U52, 2, 12, 13, 14, 15 ports are unsettled, 3 ports of single eight path analoging switch chip U52 are the gem hole detectable voltage signals output VOUT0 of gating.
5. automatic blood analyzer gem hole voltage Intelligent detection circuit according to claim 1, it is characterized in that: described gem hole voltage A/D change-over circuit is by operational amplifier chip U53, A/D conversion chip U47, resistance R134, electric capacity C120, electric capacity C121 and stabilivolt D17 form; 3 ports of operation amplifier chip U53 export VOUT0 with the voltage of gem hole voltage detecting gating circuit and are connected, 4 ports of operation amplifier chip U53 meet-12V, 7 ports of operation amplifier chip U53 meet+12V, 1 port of operation amplifier chip U53,5 ports and 8 ports are unsettled, with 3 ports of A/D conversion chip U47 are connected after connecting after 6 ports of operation amplifier chip U53 are connected with 2 ports with resistance R134 again; The negative pole of stabilivolt D17 connects 2 ports of U53 and the common port of 6 ports, its plus earth, 1 port of A/D conversion chip U47 connects+5V power supply, ground connection after 1 port of A/D conversion chip U47 and the common port of+5V are connected with the positive pole of electric capacity C121, electric capacity C120 is connected in parallel on the two ends of electric capacity C121, the 2 port ground connection of A/D conversion chip U47, and 4 ports meet the A/D clock signal AD_CLK of FPGA, 5 ports meet the A/D data-signal AD_DATA of FPGA, and 6 ports meet the A/D chip selection signal AD_CS of FPGA.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520033366.9U CN204330877U (en) | 2015-01-19 | 2015-01-19 | A kind of automatic blood analyzer gem hole voltage Intelligent detection circuit |
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| CN201520033366.9U CN204330877U (en) | 2015-01-19 | 2015-01-19 | A kind of automatic blood analyzer gem hole voltage Intelligent detection circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112683949A (en) * | 2020-11-30 | 2021-04-20 | 深圳市科曼医疗设备有限公司 | Method and system for detecting blockage of jewel hole and storage medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112683949A (en) * | 2020-11-30 | 2021-04-20 | 深圳市科曼医疗设备有限公司 | Method and system for detecting blockage of jewel hole and storage medium |
| CN112683949B (en) * | 2020-11-30 | 2023-09-19 | 深圳市科曼医疗设备有限公司 | Gem hole blocking detection method, system and storage medium |
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