CN204291192U - A kind of multi-screen splicing processor - Google Patents
A kind of multi-screen splicing processor Download PDFInfo
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- CN204291192U CN204291192U CN201420326021.8U CN201420326021U CN204291192U CN 204291192 U CN204291192 U CN 204291192U CN 201420326021 U CN201420326021 U CN 201420326021U CN 204291192 U CN204291192 U CN 204291192U
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Abstract
The utility model relates to a kind of multi-screen splicing processor that can carry out self-defined station symbol display, comprise splicing control module, power module, Video input card and video frequency output card, described splicing control module comprises FPGA module, matrix exchanger and microprocessor, and described microprocessor is connected with FPGA module and matrix exchanger respectively, and described FPGA module is connected with matrix exchanger, described Video input card is connected with matrix exchanger, and described video frequency output card is connected with matrix exchanger; Multi-screen splicing processor can not only complete and carry out splicing to multiple display unit and complete image display function, can also carry out self-defined station symbol or masking-out display; Meanwhile, station symbol or masking-out editor and display can be carried out in real time, when station symbol or masking-out process, multichannel can be carried out and process simultaneously, not limit by CPU processing speed and bandwidth.
Description
Technical field
The utility model relates to a kind of multi-screen splicing processor, particularly a kind of multi-screen splicing processor of display.
Background technology
Multi-screen splicing processor is widely used in the fields such as video display, watch-dog, major function distributes to N number of video display unit (as rear-projection unit) after a complete picture signal is divided into N block, completes and form a jumbotron dynamic image display screen with multiple ordinary video display unit.Access while simultaneously can supporting various video equipment, as: DVD, video camera, satellite receiver, Set Top Box, standard computer a-signal.Multi-screen splicing processor can realize multiple physics and export the ultrahigh resolution display translation after being combined into the superposition of resolution, make screen wall form a ultrahigh resolution, super brightness, super large display size logic display screen, complete multiple signal source (network signal, rgb signal and vision signal) windowing on screen wall, move, the Presentation Function of the various mode such as convergent-divergent.
Station symbol and masking-out function, be widely used in field of video displaying, facilitates user to distinguish different video channels.Station symbol function, can be used for helping user to carry out video source sign, while display image, also increases characters information display function.Masking-out function is generally used for as video increases picture effect.In prior art, the realization of station symbol and masking-out function, mainly contains 2 kinds of modes; First is carry out video editing, and station symbol or masking-out are inserted in video, be held in fixed video file, by player plays, this mode shortcoming is station symbol or masking-out, and one-step solidification can not be revised flexibly.The second is by nonlinear editing technology, and station symbol or masking-out are inserted in video, and play display by non-linear editing, this way needs extra nonlinear editing technology, increases Project Cost and system complexity.
Utility model content
The utility model is in order to solve the problem of prior art, provide a kind of multi-screen splicing processor that can carry out self-defined station symbol display, comprise splicing control module, power module, Video input card and video frequency output card, described splicing control module comprises FPGA module, matrix exchanger and microprocessor, described microprocessor is connected with FPGA module and matrix exchanger respectively, described FPGA module is connected with matrix exchanger, described Video input card is connected with matrix exchanger, and described video frequency output card is connected with matrix exchanger.
Be below attached technical scheme of the present utility model:
Preferably, described FPGA module comprises input-output unit able to programme and configurable logic block.
Preferably, described matrix exchanger comprises signal input part, signal output part and signal processing module.
Preferably, described Video input card and video frequency output card have multiple respectively, and each Video input card or video frequency output card are connected with matrix exchanger separately.
Preferably, described multi-screen splicing processor comprises computer and display, and described Video input card is connected with computer, and described video frequency output card is connected with display.
Preferably, described display is spliced by multiple independent display unit.
Advantageous Effects of the present utility model: multi-screen splicing processor not only completes and carries out splicing to multiple display unit and complete outside image display function, the also function of practicable part non-linear editing, can carry out self-defined station symbol or masking-out display; Meanwhile, station symbol or masking-out editor and display can be carried out in real time, when station symbol or masking-out process, multichannel can be carried out and process simultaneously, not limit by CPU processing speed and bandwidth.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the utility model embodiment multi-screen splicing processor.
Fig. 2 is that the utility model embodiment video matrix exchanges schematic diagram.
Fig. 3 is the annexation block diagram of the utility model embodiment multi-screen splicing processor.
Fig. 4 is the utility model embodiment Video processing flow chart.
Fig. 5 is the display effect schematic diagram of the utility model embodiment multi-screen splicing processor.
In figure: multi-screen splicing processor 1, splicing control module 11, power module 12, Video input card 13, video frequency output card 14, display unit 2, image 3.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described further.
As depicted in figs. 1 and 2, the present embodiment multi-screen splicing processor 1 comprises splicing control module 11, power module 12, Video input card 13 and video frequency output card 14, and described power module 12 provides electric energy for multi-screen splicing processor.Described splicing controller 11 comprises matrix exchanger and FPGA module.Multiple signals can be transported on the arbitrary passage output channel from input channel switching by matrix exchanger, and independent of one another between output channel.Described matrix exchanger comprises signal input part, signal output part and signal processing module.Described FPGA (Field-Programmable Gate Array, field programmable gate array) module comprises input-output unit able to programme (IOB), configurable logic block (CLB), digital dock administration module.Described input-output unit able to programme is the interface section of FPGA module and external circuitry, complete under different electrical characteristic to the driving of input/output signal with mate requirement.Described configurable logic block is the basic logic unit in FPGA module, and it comprises a configurable switch matrix.Described digital dock administration module mainly for providing accurate clock comprehensive, and can reduce shake, and realizes filtering function.By FPGA module, user is programmed by FPGA, carries out station symbol or masking-out process, can carry out multichannel and process simultaneously, not limit by CPU processing speed and bandwidth.As shown in Figure 2, multi-channel video can be linked in matrix exchanger respectively by multiple Video input card, through matrix switch, gives different video frequency output cards by video of not going the same way, video frequency output card for completing the process such as superposition, roaming of video, and by video frequency output.
As shown in Figure 3 and Figure 4, described splicing control module 11 also comprises microcontroller (CPU), program storage, encoder and transceiver.Described transceiver is connected with computer the corresponding interface, and the control command of computer is transferred to CPU by encoder and transceiver.The signal input part of output port on computer with multi-screen splicing processor can be connected by user, user by computer by video input multi-screen splicing processor.Those skilled in the art are known, also video content can be inputted multi-screen splicing processor, as long as Interface Matching by other input equipments.As shown in Figure 4, user completes vision signal access multi-screen splicing processor by video input step, then user carries out station symbol setting by the software on computer, can according to user's needs, setting table target position, size, color, content (picture or word content, font) etc.; FPGA module is arranged according to station symbol carries out station symbol process, when carrying out station symbol process, can carry out multichannel and process simultaneously, not limit by CPU processing speed and bandwidth, complete the overlap-add procedure of video content and station symbol by FPGA; Then splicing is carried out to video, become specific format to output on display Video Quality Metric through video frequency output card.In figure, arrow represents Video processing flow direction.As shown in Figure 5, described display is spliced by 4 display units 2, and namely multiple screen synthesizes one and shows.Described image 3 (also visual make station symbol) display section image in each display unit 2, shows complete image in the display.
The utility model is not only completed by FPGA module and matrix converter and carries out splicing to multiple display unit and complete outside image display function, can also carry out self-defined station symbol or masking-out display; Meanwhile, station symbol or masking-out editor and display can be carried out in real time, meet the needs of on-the-spot performance, when station symbol or masking-out process, multichannel can be carried out and process simultaneously, not limit by CPU processing speed and bandwidth.It is to be noted; above-mentioned preferred embodiment is only and technical conceive of the present utility model and feature is described; its object is to person skilled in the art can be understood content of the present utility model and implement according to this, protection range of the present utility model can not be limited with this.All equivalences done according to the utility model Spirit Essence change or modify, and all should be encompassed within protection range of the present utility model.
Claims (6)
1. a multi-screen splicing processor, comprise splicing control module, power module, Video input card and video frequency output card, it is characterized in that: described splicing control module comprises FPGA module, matrix exchanger and microprocessor, and described microprocessor is connected with FPGA module and matrix exchanger respectively, and described FPGA module is connected with matrix exchanger, described Video input card is connected with matrix exchanger, and described video frequency output card is connected with matrix exchanger.
2. multi-screen splicing processor as claimed in claim 1, is characterized in that: described FPGA module comprises input-output unit able to programme and configurable logic block.
3. multi-screen splicing processor as claimed in claim 2, is characterized in that: described matrix exchanger comprises signal input part, signal output part and signal processing module.
4. multi-screen splicing processor as claimed in claim 3, it is characterized in that: described Video input card and video frequency output card have multiple respectively, each Video input card or video frequency output card are connected with matrix exchanger separately.
5. multi-screen splicing processor as claimed in claim 4, it is characterized in that: described multi-screen splicing processor comprises computer and display, and described Video input card is connected with computer, described video frequency output card is connected with display.
6. multi-screen splicing processor as claimed in claim 5, is characterized in that: described display is spliced by multiple independent display unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420326021.8U CN204291192U (en) | 2014-06-16 | 2014-06-16 | A kind of multi-screen splicing processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420326021.8U CN204291192U (en) | 2014-06-16 | 2014-06-16 | A kind of multi-screen splicing processor |
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| CN204291192U true CN204291192U (en) | 2015-04-22 |
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| CN201420326021.8U Expired - Fee Related CN204291192U (en) | 2014-06-16 | 2014-06-16 | A kind of multi-screen splicing processor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105373023A (en) * | 2015-11-24 | 2016-03-02 | 中国航空工业集团公司沈阳飞机设计研究所 | Avionics integration test integrated control assembly |
| CN106385553A (en) * | 2016-08-14 | 2017-02-08 | 深圳市芯智科技有限公司 | High-resolution ultrahigh-definition display system and method |
-
2014
- 2014-06-16 CN CN201420326021.8U patent/CN204291192U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105373023A (en) * | 2015-11-24 | 2016-03-02 | 中国航空工业集团公司沈阳飞机设计研究所 | Avionics integration test integrated control assembly |
| CN106385553A (en) * | 2016-08-14 | 2017-02-08 | 深圳市芯智科技有限公司 | High-resolution ultrahigh-definition display system and method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| DD01 | Delivery of document by public notice |
Addressee: Ma Guoguang Document name: Notification to Make Rectification |
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| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20171215 Address after: 361000 Fujian city of Xiamen province Xiamen software park two sunrise Road No. 54 unit 502 Patentee after: Xiamen Sunzone Precision Technology Co., Ltd. Address before: 361008 Fujian city of Xiamen province Xiamen software park two sunrise Road No. 54 unit 502 Patentee before: Ma Guoguang |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150422 Termination date: 20190616 |