CN204290400U - A kind of control system of battery SOC management system - Google Patents
A kind of control system of battery SOC management system Download PDFInfo
- Publication number
- CN204290400U CN204290400U CN201420767983.7U CN201420767983U CN204290400U CN 204290400 U CN204290400 U CN 204290400U CN 201420767983 U CN201420767983 U CN 201420767983U CN 204290400 U CN204290400 U CN 204290400U
- Authority
- CN
- China
- Prior art keywords
- resistance
- connects
- pin
- electric capacity
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Secondary Cells (AREA)
Abstract
The utility model relates to a kind of control system of battery SOC management system, the output comprising battery management module connects the input of balance module and the input of temperature sampling module respectively, battery management module input connects the both positive and negative polarity of battery pack, the input of battery management module connects the output of MCU module, the output of MCU module connects the input of MOSFET control module and the input of RS485 interface module respectively, the output of MOSFET control module connects the input of battery management module, the input of MCU module connects the output of temperature sampling module and the output of current measurement module respectively, the input of current measurement module connects the negative pole of battery pack, power module is electrically connected battery management module respectively, balance module, current measurement module, MOSFET control module, RS485 interface module, MCU module and temperature sampling module.The accuracy that native system is measured is high.
Description
Technical field
The utility model belongs to digital and electronic field, particularly relates to a kind of control system of battery SOC management system.
Background technology
Ferric phosphate lithium cell (LiFePO4) has that volume is little, lightweight, energy density is high, good seal, without leakage, memory-less effect, the feature such as discharge performance is high, self-discharge rate is low, charging is rapid, have extended cycle life, operating ambient temperature range is wide, energy-conservation and environmental protection, be particularly suitable for high-voltage great-current and the violent motive use occasion of the fluctuation of load.
Although ferric phosphate lithium cell in short circuit, overcharge, extrude, remain safe under service condition that acupuncture etc. is harsh, extreme influence can be caused to the cycle life of battery.Ferric phosphate lithium cell production technology more complicated, the consistency difference of cell can be larger than sealed valve control lead-acid battery, this just causes the voltage of battery pack phase individual monomers battery after charging to rise rapidly, thus causing the phenomenon of ferric phosphate lithium cell group reduced lifetime or damage, the generation in order to avoid above phenomenon just needs to ensure the safe and reliable of battery with battery management system.
Battery management system (Battery Management System; i.e. BMS); it is the core component of battery protection and management; not only to ensure that cell safety uses reliably; and the performance of battery will be given full play to and increase the service life; management system plays a function served as bridge between high-voltage DC power supply and battery, between battery and load, so the fail safe of the safety management mode of battery management system to battery is most important.Battery management system mainly comprises data acquisition unit, battery SOC (state-of-charge, State of Charge) evaluation unit, control unit, balanced unit and communication unit, this wherein SOC evaluation unit be again the key of this management system.
Ferric phosphate lithium cell in use, the SOC of Accurate Measurement battery to reasonable employment ferric phosphate lithium cell, increasing the service life has key effect.The method that tradition measures SOC has open circuit voltage method usually, Current integrating method, artificial neural net, Kalman filtering algorithm etc., but the factor in fact affecting SOC is very complicated, such as serviceability temperature, charge-discharge magnification, cycle-index, internal resistance changes, the factors such as self discharge all have a certain impact to SOC, conventional method often only considers these two parameters of voltage and current integration, this will inevitably bring certain impact for the estimating precision of SOC, especially under the high-voltage great-current operating states such as container tyre formula gantry, this impact highly significant sometimes.Existing control circuit is complicated, the defect that certainty of measurement is low.
Utility model content
The purpose of this utility model is the control system providing a kind of battery SOC management system, is intended to solve above-mentioned technical problem.
The utility model is achieved in that a kind of control system of battery SOC management system, and this control system comprises battery management module, balance module, current measurement module, MOSFET control module, RS485 interface module, MCU module, temperature sampling module, battery pack and power module, the output of described battery management module connects the input of described balance module and the input of described temperature sampling module respectively, described battery management module input connects the both positive and negative polarity of described battery pack, the input of described battery management module connects the output of described MCU module, the output of described MCU module connects input and the RS485 interface module of described MOSFET control module respectively, the output of described MOSFET control module connects the input of described battery management module, the input of described MCU module connects the described output of temperature sampling module and the output of current measurement module respectively, the input of described current measurement module connects the negative pole of described battery pack, and described power module is electrically connected described battery management module respectively, balance module, current measurement module, MOSFET control module, RS485 interface module, MCU module and temperature sampling module.
Further technical scheme of the present utility model is: described battery management module comprises Battery disposal chip U2, 16th pin of described Battery disposal chip U2 connects one end of electric capacity C35, 17th pin of described Battery disposal chip U2 connects one end of electric capacity C31 and one end of electric capacity C18 respectively, 18th pin of described Battery disposal chip U2 connects one end of electric capacity C32 and one end of electric capacity C19 respectively, 19th pin of described Battery disposal chip U2 is through resistance R75 one end of contact resistance R73 and one end of electric capacity C36 respectively, the other end of described resistance R73 connects one end of thermistor NTC1, 20th pin of described Battery disposal chip U2 connects one end of described electric capacity C36, 31st pin of described Battery disposal chip U2 is through resistance R49 one end of contact resistance R32 and the grid of field effect transistor Q23 respectively, the other end of described resistance R32 connects the source electrode of described field effect transistor Q23, the drain electrode of described field effect transistor Q23 is through the negative pole of resistance R90 connecting luminous diode LED1, 32nd pin of described Battery disposal chip U2 connects one end of electric capacity C33 and one end of electric capacity C20 respectively, one end of the 38th pin contact resistance R92 of described Battery disposal chip U2, one end of the 39th pin contact resistance R93 of described Battery disposal chip U2, the 40th pin one end of contact resistance R94 and one end of resistance R42 respectively of described Battery disposal chip U2, one end of the 41st pin contact resistance R95 of described Battery disposal chip U2, the 42nd pin one end of contact resistance R96 and one end of resistance R41 respectively of described Battery disposal chip U2, the 45th pin one end of contact resistance R58 and one end of resistance R34 respectively of described Battery disposal chip U2, one end of the other end contact resistance R59 of described resistance R34, the other end of described resistance R59 connects the drain electrode of field effect transistor Q25, grid one end of contact resistance R57 and one end of resistance R33 respectively of described field effect transistor Q25, the other end of described resistance R58 connects the grid of field effect transistor Q24, the drain electrode of described field effect transistor Q24 is through the negative pole of resistance R91 connecting luminous diode LED2, one end of the 52nd pin resistance R60 of described Battery disposal chip U2, one end of the 53rd pin contact resistance R56 of described Battery disposal chip U2, the 54th pin one end of contact resistance R55 and one end of electric capacity C40 respectively of described Battery disposal chip U2, one end of the 55th pin contact resistance R54 of described Battery disposal chip U2, the 56th pin one end of contact resistance R53 and one end of electric capacity C39 respectively of described Battery disposal chip U2, the 57th pin one end of contact resistance R52 and one end of electric capacity C38 respectively of described Battery disposal chip U2, one end of the 58th pin contact resistance R51 of described Battery disposal chip U2, one end of the 59th pin contact resistance R50 of described Battery disposal chip U2, 60th pin of described Battery disposal chip U2 is through resistance R76 one end of contact resistance R74 and one end of electric capacity C37 respectively, the other end of described resistance R74 connects one end of thermistor NTC2, 64th pin of described Battery disposal chip U2 connects one end of electric capacity C21 and the negative pole of voltage stabilizing didoe D13 respectively.
Further technical scheme of the present utility model is: described balance module comprises binding post J1, the 1st pin one end of contact resistance R15 and one end of inductance L 9 respectively of described binding post J1, and the other end of described inductance L 9 connects one end of electric capacity C11 respectively, the negative pole of voltage stabilizing didoe D6, one end of resistance R14 and one end of resistance R48, the other end of described resistance R48 connects one end of electric capacity C17, and the other end of described resistance R14 connects the drain electrode of field effect transistor Q16, one end of the grid difference contact resistance R31 of described field effect transistor Q16, the negative pole of voltage stabilizing didoe D12 and one end of resistance R40, the 2nd pin of described binding post J1 connects one end of inductance L 8, and the other end of described inductance L 8 connects the other end of electric capacity C11 respectively, the positive pole of voltage stabilizing didoe D6, the source electrode of field effect transistor Q16, the other end of resistance R31, the positive pole of voltage stabilizing didoe D12, one end of resistance R47, one end of resistance R13, one end of voltage stabilizing didoe D5 and one end of electric capacity C10, the other end of described resistance R47 connects one end of electric capacity C16, and the other end of described resistance R13 connects the drain electrode of field effect transistor Q15, one end of the grid difference contact resistance R30 of described field effect transistor Q15, the negative pole of voltage stabilizing didoe D11 and one end of resistance R39, the 3rd pin of described binding post J1 connects the other end of described resistance R15 and one end of inductance L 7 respectively, and the other end of described inductance L 7 connects the other end of electric capacity C10 respectively, the positive pole of voltage stabilizing didoe D5, the source electrode of field effect transistor Q15, the other end of resistance R30, the positive pole of voltage stabilizing didoe D11, one end of resistance R46, one end of resistance R12, the negative pole of voltage stabilizing didoe D4, one end of electric capacity C9, the other end of described resistance R46 connects one end of electric capacity C15, and the other end of described resistance R12 connects the drain electrode of field effect transistor Q14, one end of the grid difference contact resistance R29 of described field effect transistor Q14, the negative pole of voltage stabilizing didoe D10 and one end of resistance R38, described binding post J1 the 4th pin connects one end of inductance L 6, and the other end of described inductance L 6 connects the other end of electric capacity C9 respectively, the positive pole of voltage stabilizing didoe D4, the source electrode of field effect transistor Q14, the other end of resistance R29, the positive pole of voltage stabilizing didoe D10, one end of resistance R45, one end of resistance R11, the negative pole of voltage stabilizing didoe D3 and one end of electric capacity C8, the other end of described resistance R45 connects one end of electric capacity C14, and the other end of described resistance R11 connects the drain electrode of field effect transistor Q13, one end of the grid difference contact resistance R28 of described field effect transistor Q13, the negative pole of voltage stabilizing didoe D9 and one end of resistance R37, the 5th pin of described binding post J1 connects one end of inductance L 5, and the other end of described inductance L 5 connects the other end of electric capacity C8 respectively, the positive pole of voltage stabilizing didoe D3, the source electrode of field effect transistor Q13, the other end of resistance R28, the positive pole of voltage stabilizing didoe D9, one end of resistance R44, one end of resistance R10, the negative pole of voltage stabilizing didoe D2 and one end of electric capacity C7, the other end of described resistance R44 connects one end of electric capacity C13, and the other end of described resistance R10 connects the drain electrode of field effect transistor Q12, one end of the grid difference contact resistance R27 of described field effect transistor Q12, the negative pole of voltage stabilizing didoe D8 and one end of resistance R36, the 6th pin of described binding post J1 connects one end of inductance L 4, and the other end of described inductance L 4 connects the other end of electric capacity C7 respectively, the positive pole of voltage stabilizing didoe D2, the source electrode of field effect transistor Q12, the other end of resistance R27, the positive pole of voltage stabilizing didoe D8, resistance R43, one end of resistance R9, the negative pole of voltage stabilizing didoe D1 and one end of electric capacity C6, the other end of described resistance R43 connects one end of electric capacity C12, and the other end of described resistance R9 connects the drain electrode of field effect transistor Q11, one end of the grid difference contact resistance R27 of described field effect transistor Q11, the negative pole of voltage stabilizing didoe D7 and one end of resistance R35, the 7th pin of described binding post J1 connects one end of inductance L 3, and the other end of described inductance L 3 connects the other end of electric capacity C6 respectively, the positive pole of voltage stabilizing didoe D1, the source electrode of field effect transistor Q11, the other end of resistance R26 and the positive pole of voltage stabilizing didoe D7.
Further technical scheme of the present utility model is: described current measurement module comprises resistance R3 in parallel, resistance R4, resistance R5, resistance R6, resistance R3, resistance R4, resistance R5, one end after resistance R6 parallel connection connects one end of inductance L 2, resistance R3, resistance R4, resistance R5, the other end after resistance R6 parallel connection is through inductance L 1 ground connection, and the other end of described inductance L 2 connects one end of electric capacity C1 respectively, one end of resistance R19 and one end of resistance R7, the other end of described resistance R19 connects one end of electric capacity C3 respectively, one end of resistance R18 and the 2nd pin of amplifier U1A, the other end of described resistance R18 connects first pin of amplifier U1A and one end of resistance R16 respectively, one end of the 3rd pin difference contact resistance R22 of amplifier U1A, one end of resistance R1 and one end of electric capacity C4, one end of the other end difference contact resistance R25 of described resistance R7, 6th pin of amplifier U1B and one end of electric capacity C5, the other end of described electric capacity C5 connects one end of electric capacity C23, one end of the 7th pin contact resistance R17 of described amplifier U1B, the other end of described resistance R25 connects one end of described resistance R17, one end of the 5th pin difference contact resistance R24 of described amplifier U1B, electric capacity C2 one end and resistance R8 one end.
Further technical scheme of the present utility model is: described MOSFET control module comprises resistance R23, and one end of described resistance R23 connects one end of electric capacity C22, and the other end of described resistance R23 connects the source electrode of field effect transistor Q2 respectively, the source electrode of field effect transistor Q7, the source electrode of field effect transistor Q8, the source electrode of field effect transistor Q9, the source electrode of field effect transistor Q10, the other end of described electric capacity C22 connects the source electrode of field effect transistor Q1 respectively, the source electrode of field effect transistor Q3, the source electrode of field effect transistor Q4, the source electrode of field effect transistor Q5, the source electrode of field effect transistor Q6, described field effect transistor Q1, field effect transistor Q3, field effect transistor Q4, field effect transistor Q5, field effect transistor Q6, field effect transistor Q2, field effect transistor Q7, field effect transistor Q8, field effect transistor Q9, the drain electrode of field effect transistor Q10 is connected to each other, and the source electrode of described field effect transistor Q6 also distinguishes the collector electrode of connecting triode Q17, the positive pole of voltage stabilizing didoe D14 and one end of resistance R77, one end of the grid contact resistance R61 of described field effect transistor Q1, one end of the grid contact resistance R62 of described field effect transistor Q3, one end of the grid contact resistance R63 of described field effect transistor Q4, one end of the grid contact resistance R64 of described field effect transistor Q5, one end of the grid contact resistance R65 of described field effect transistor Q6, described resistance R61, resistance R62, resistance R63, resistance R64, one end of the other end difference contact resistance R71 of resistance R65, the other end of described resistance R71 connects the emitter of described triode Q17 and the negative pole of diode D15 respectively, the other end of one end difference contact resistance R77 of resistance R2, the negative pole of voltage stabilizing didoe D14, the base stage of triode Q17 and the positive pole of diode D15, the collector electrode of the other end connecting triode Q19 of described resistance R2, the base stage contact resistance R83 and resistance R82 respectively of described triode Q19, the collector electrode of the other end connecting triode Q22 of described resistance R82, base stage one end of contact resistance R81 and one end of resistance R86 respectively of described triode Q22, one end of the grid contact resistance R70 of described field effect transistor Q2, one end of the grid contact resistance R69 of described field effect transistor Q7, one end of the grid contact resistance R68 of described field effect transistor Q8, one end of the grid contact resistance R67 of described field effect transistor Q9, one end of the grid contact resistance R66 of described field effect transistor Q10, described resistance R66, resistance R67, resistance R68, one end of the other end difference contact resistance R72 of resistance R69 and resistance R70, one end of the other end difference contact resistance R 79 of described resistance R72, the emitter of triode Q18 and the emitter of triode Q21, one end of resistance R87 connects the other end of described resistance R79 respectively, the base stage of triode Q18 and the base stage of triode Q21, other end one end of contact resistance R80 and the collector electrode of triode Q20 respectively of described resistance R87, base stage one end of contact resistance R85 and one end of resistance R78 respectively of described triode Q20.
Further technical scheme of the present utility model is: described RS485 interface module comprises chip U3, one end of the first pin contact resistance R21 of described chip U3, one end of the 3rd pin contact resistance R20 of described chip U3, 2nd pin of described chip U3 connects one end of electric capacity C24, 4th pin of described chip U3 connects one end of optocoupler U4 through resistance R88, other end one end of contact resistance R101 and the 4th pin of chip U7 respectively of optocoupler U4, one end of the 6th pin contact resistance R89 of described chip U3, the other end of described resistance R89 connects one end of optocoupler U5, the other end of described optocoupler U5 connects one end of electric capacity C42 respectively, one end of resistance R102 and the 2nd pin of chip U7 and the 3rd pin, one end of the 1st pin contact resistance R103 of described chip U7, the other end of described resistance R103 connects one end of optocoupler U, one end of the other end contact resistance R104 of described optocoupler U6, 5th pin one end of contact resistance R105 and the 2nd pin of chip U10 respectively of described chip U7, the 6th pin one end of contact resistance R107 and one end of resistance R106 respectively of described chip U7, one end of the 7th pin contact resistance R108 of described chip U7, the 8th pin other end of contact resistance R106 and one end of electric capacity C29 respectively of described chip U7, other end one end of contact resistance R109 and the 3rd pin of chip U10 respectively of described resistance R107, the other end of the 4th pin contact resistance R109 of described chip U10, 5th pin of described chip U10 connects one end of electric capacity C46 respectively, one end of electric capacity C28 and one end of inductance L 11, the other end of described inductance L 11 connects the 1st pin of binding post J3 and the 1st pin of binding post J2 respectively.
Further technical scheme of the present utility model is: described MCU module comprises chip U8, 1st pin of described chip U8 connects one end of electric capacity C25 respectively, one end of electric capacity C24, one end of resistance R110 and the 4th pin of binding post J4, the other end of described resistance R110 connects one end of electric capacity C47 and the 4th pin of binding post J4 respectively, 9th pin of described binding post J4 connects the other end of electric capacity C47, 7th pin of described binding post J4 connects the 8th pin of binding post J4 through resistance R111, one end of the 9th pin contact resistance R84 of described chip U8, the other end of described resistance R84 connects the grid of field effect transistor Q27, described field effect transistor Q27 drain electrode connect electric capacity C27 one end respectively, the positive pole of electric capacity C44 and the 1st pin of chip U9 and the 2nd pin, the source electrode of described field effect transistor Q27 connects the positive pole of electric capacity C45 and one end of electric capacity C30 respectively, the other end of described electric capacity C27 connects the negative pole of electric capacity C45 respectively, the other end of electric capacity C30, the negative pole of electric capacity C44, 3rd pin of chip U9 and the 4th pin, one end of electric capacity C26, the negative pole of electric capacity C43, the positive pole of voltage stabilizing didoe D16 and one end of electric capacity C41, 6th pin of described chip U9 is connected with the 7th pin, 8th pin of described chip U9 connects the other end of electric capacity C26 respectively, the positive pole of electric capacity C43 and the source electrode of field effect transistor Q26, the drain electrode contact resistance R98 respectively of described field effect transistor Q26, resistance R99, one end of resistance R100, one end of the grid contact resistance R97 of described field effect transistor Q26, the other end of described electric capacity C41 connects one end of inductance L 10, the other end contact resistance R97 respectively of described inductance L 10, resistance R98, resistance R99, the other end of resistance R100.
Further technical scheme of the present utility model is: described chip U8 adopts MSP430G2533PW28 chip; Described chip U9 adopts LP2951ACM-3.3 chip.
Further technical scheme of the present utility model is: what described Battery disposal chip U2 adopted is QB76PL536A chip.
Further technical scheme of the present utility model is: described chip U adopts NL27WZ16 chip; Described chip U7 adopts MAX485 chip; Chip U10 adopts NUP420IMR6T1 chip.
The beneficial effects of the utility model are: the circuit structure of control system of the present utility model accuracy that is simple, that measure is high, improves the precision of battery charge state estimation, improves the matching degree of systematic measurement error.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the control system of the battery SOC management system that the utility model embodiment provides;
Fig. 2 is the circuit diagram of the battery management module that the utility model embodiment provides;
Fig. 3 is the circuit diagram of the balance module that the utility model embodiment provides;
Fig. 4 is the circuit diagram of the current measurement module that the utility model embodiment provides
Fig. 5 is the circuit diagram of the MOSFET control module that the utility model embodiment provides
Fig. 6 is the circuit diagram of the RS485 interface module that the utility model embodiment provides
Fig. 7 is the circuit diagram of the MCU module that the utility model embodiment provides.
Embodiment
Reference numeral: 1-battery management module 2-MCU module 3-balance module 4-temperature sampling module 5-MOSFET control module 6-RS485 interface module 7-current measurement module 8-battery pack 9-power module.
Fig. 1-7 shows the control system of the battery SOC management system that the utility model provides, this control system comprises battery management module 1, balance module 3, current measurement module 7, MOSFET control module 5, RS485 interface module 6, MCU module 2, temperature sampling module 4, battery pack 8 and power module 9, the output of described battery management module 1 connects the input of described balance module 3 and the input of described temperature sampling module 4 respectively, described battery management module 1 input connects the both positive and negative polarity of described battery pack 8, the input of described battery management module 1 connects the output of described MCU module 2, the output of described MCU module 2 connects the input of described MOSFET control module 5 and the input of RS485 interface module 6 respectively, the output of described MOSFET control module 5 connects the input of described battery management module 5, the input of described MCU module 2 connects the output of described temperature sampling module 4 and the output of current measurement module 7 respectively, the input of described current measurement module 7 connects the negative pole of described battery pack 8, described power module 9 is electrically connected described battery management module 1 respectively, balance module 3, current measurement module 4, MOSFET control module 5, RS485 interface module 6, MCU module 2 and temperature sampling module 4.The circuit structure of control system of the present utility model accuracy that is simple, that measure is high, improves the precision of battery charge state estimation, improves the matching degree of systematic measurement error.
Described battery management module 1 comprises Battery disposal chip U2, 16th pin of described Battery disposal chip U2 connects one end of electric capacity C35, 17th pin of described Battery disposal chip U2 connects one end of electric capacity C31 and one end of electric capacity C18 respectively, 18th pin of described Battery disposal chip U2 connects one end of electric capacity C32 and one end of electric capacity C19 respectively, 19th pin of described Battery disposal chip U2 is through resistance R75 one end of contact resistance R73 and one end of electric capacity C36 respectively, the other end of described resistance R73 connects one end of thermistor NTC1, 20th pin of described Battery disposal chip U2 connects one end of described electric capacity C36, 31st pin of described Battery disposal chip U2 is through resistance R49 one end of contact resistance R32 and the grid of field effect transistor Q23 respectively, the other end of described resistance R32 connects the source electrode of described field effect transistor Q23, the drain electrode of described field effect transistor Q23 is through the negative pole of resistance R90 connecting luminous diode LED1, 32nd pin of described Battery disposal chip U2 connects one end of electric capacity C33 and one end of electric capacity C20 respectively, one end of the 38th pin contact resistance R92 of described Battery disposal chip U2, one end of the 39th pin contact resistance R93 of described Battery disposal chip U2, the 40th pin one end of contact resistance R94 and one end of resistance R42 respectively of described Battery disposal chip U2, one end of the 41st pin contact resistance R95 of described Battery disposal chip U2, the 42nd pin one end of contact resistance R96 and one end of resistance R41 respectively of described Battery disposal chip U2, the 45th pin one end of contact resistance R58 and one end of resistance R34 respectively of described Battery disposal chip U2, one end of the other end contact resistance R59 of described resistance R34, the other end of described resistance R59 connects the drain electrode of field effect transistor Q25, grid one end of contact resistance R57 and one end of resistance R33 respectively of described field effect transistor Q25, the other end of described resistance R58 connects the grid of field effect transistor Q24, the drain electrode of described field effect transistor Q24 is through the negative pole of resistance R91 connecting luminous diode LED2, one end of the 52nd pin resistance R60 of described Battery disposal chip U2, one end of the 53rd pin contact resistance R56 of described Battery disposal chip U2, the 54th pin one end of contact resistance R55 and one end of electric capacity C40 respectively of described Battery disposal chip U2, one end of the 55th pin contact resistance R54 of described Battery disposal chip U2, the 56th pin one end of contact resistance R53 and one end of electric capacity C39 respectively of described Battery disposal chip U2, the 57th pin one end of contact resistance R52 and one end of electric capacity C38 respectively of described Battery disposal chip U2, one end of the 58th pin contact resistance R51 of described Battery disposal chip U2, one end of the 59th pin contact resistance R50 of described Battery disposal chip U2, 60th pin of described Battery disposal chip U2 is through resistance R76 one end of contact resistance R74 and one end of electric capacity C37 respectively, the other end of described resistance R74 connects one end of thermistor NTC2, 64th pin of described Battery disposal chip U2 connects one end of electric capacity C21 and the negative pole of voltage stabilizing didoe D13 respectively.
In BQ76PL536 circuit, BQ76PL536 be TI release can the reserve battery processing IC of cascade, it is built-in supports 3 to 6 joint series-connected cells, comprise 14 high precision analogue change-over circuits of 9 road analog inputs, wherein, 6 tunnels process 6 crosstalk cell voltages, 2 tunnel treatment temperatures, 1 road general-purpose simulation input circuit; Its built-in SPI data communication interface, and without the need to the Stackable vertical joint of isolation between built-in device; The second protection circuit of its built-in programmable threshold value and programmable delay, to realize over-charge protective, Cross prevention, overheat protector indicating with special fault-signal; Its built-in balancing control circuit; The AUX of its built-in general-purpose IO and controlled output, the design's circuit is used to refer to the operating state of battery.
In this experimental design, the application of the manystage cascade connection and the Universal Die analog quantity that abandon BQ76PL536 input, in circuit, adopt 4 string/6 string variable solutions, if with 4 string schemes, so, the 5th string and the related device NC of the 6th equalizing circuit of going here and there, R15 Zero-ohm resistor is by just can be with since Vcell4 and Vcell6 short circuit.
Two-way temperature sensing circuit in circuit, a road is used for detecting the temperature of battery core, and another road is used for the temperature of testing circuit plate.
Described balance module 3 comprises binding post J1, the 1st pin one end of contact resistance R15 and one end of inductance L 9 respectively of described binding post J1, and the other end of described inductance L 9 connects one end of electric capacity C11 respectively, the negative pole of voltage stabilizing didoe D6, one end of resistance R14 and one end of resistance R48, the other end of described resistance R48 connects one end of electric capacity C17, and the other end of described resistance R14 connects the drain electrode of field effect transistor Q16, one end of the grid difference contact resistance R31 of described field effect transistor Q16, the negative pole of voltage stabilizing didoe D12 and one end of resistance R40, the 2nd pin of described binding post J1 connects one end of inductance L 8, and the other end of described inductance L 8 connects the other end of electric capacity C11 respectively, the positive pole of voltage stabilizing didoe D6, the source electrode of field effect transistor Q16, the other end of resistance R31, the positive pole of voltage stabilizing didoe D12, one end of resistance R47, one end of resistance R13, one end of voltage stabilizing didoe D5 and one end of electric capacity C10, the other end of described resistance R47 connects one end of electric capacity C16, and the other end of described resistance R13 connects the drain electrode of field effect transistor Q15, one end of the grid difference contact resistance R30 of described field effect transistor Q15, the negative pole of voltage stabilizing didoe D11 and one end of resistance R39, the 3rd pin of described binding post J1 connects the other end of described resistance R15 and one end of inductance L 7 respectively, and the other end of described inductance L 7 connects the other end of electric capacity C10 respectively, the positive pole of voltage stabilizing didoe D5, the source electrode of field effect transistor Q15, the other end of resistance R30, the positive pole of voltage stabilizing didoe D11, one end of resistance R46, one end of resistance R12, the negative pole of voltage stabilizing didoe D4, one end of electric capacity C9, the other end of described resistance R46 connects one end of electric capacity C15, and the other end of described resistance R12 connects the drain electrode of field effect transistor Q14, one end of the grid difference contact resistance R29 of described field effect transistor Q14, the negative pole of voltage stabilizing didoe D10 and one end of resistance R38, described binding post J1 the 4th pin connects one end of inductance L 6, and the other end of described inductance L 6 connects the other end of electric capacity C9 respectively, the positive pole of voltage stabilizing didoe D4, the source electrode of field effect transistor Q14, the other end of resistance R29, the positive pole of voltage stabilizing didoe D10, one end of resistance R45, one end of resistance R11, the negative pole of voltage stabilizing didoe D3 and one end of electric capacity C8, the other end of described resistance R45 connects one end of electric capacity C14, and the other end of described resistance R11 connects the drain electrode of field effect transistor Q13, one end of the grid difference contact resistance R28 of described field effect transistor Q13, the negative pole of voltage stabilizing didoe D9 and one end of resistance R37, the 5th pin of described binding post J1 connects one end of inductance L 5, and the other end of described inductance L 5 connects the other end of electric capacity C8 respectively, the positive pole of voltage stabilizing didoe D3, the source electrode of field effect transistor Q13, the other end of resistance R28, the positive pole of voltage stabilizing didoe D9, one end of resistance R44, one end of resistance R10, the negative pole of voltage stabilizing didoe D2 and one end of electric capacity C7, the other end of described resistance R44 connects one end of electric capacity C13, and the other end of described resistance R10 connects the drain electrode of field effect transistor Q12, one end of the grid difference contact resistance R27 of described field effect transistor Q12, the negative pole of voltage stabilizing didoe D8 and one end of resistance R36, the 6th pin of described binding post J1 connects one end of inductance L 4, and the other end of described inductance L 4 connects the other end of electric capacity C7 respectively, the positive pole of voltage stabilizing didoe D2, the source electrode of field effect transistor Q12, the other end of resistance R27, the positive pole of voltage stabilizing didoe D8, resistance R43, one end of resistance R9, the negative pole of voltage stabilizing didoe D1 and one end of electric capacity C6, the other end of described resistance R43 connects one end of electric capacity C12, and the other end of described resistance R9 connects the drain electrode of field effect transistor Q11, one end of the grid difference contact resistance R27 of described field effect transistor Q11, the negative pole of voltage stabilizing didoe D7 and one end of resistance R35, the 7th pin of described binding post J1 connects one end of inductance L 3, and the other end of described inductance L 3 connects the other end of electric capacity C6 respectively, the positive pole of voltage stabilizing didoe D1, the source electrode of field effect transistor Q11, the other end of resistance R26 and the positive pole of voltage stabilizing didoe D7.
In the circuit of balance module, by the built-in Balance route of BQ76PL536 CB1, CB2 ... CB6 respectively correspondence control Q11, Q12 ... Q16, so that the euqalizing current realizing about 100mA.
Described current measurement module 7 comprises resistance R3 in parallel, resistance R4, resistance R5, resistance R6, resistance R3, resistance R4, resistance R5, one end after resistance R6 parallel connection connects one end of inductance L 2, resistance R3, resistance R4, resistance R5, the other end after resistance R6 parallel connection is through inductance L 1 ground connection, and the other end of described inductance L 2 connects one end of electric capacity C1 respectively, one end of resistance R19 and one end of resistance R7, the other end of described resistance R19 connects one end of electric capacity C3 respectively, one end of resistance R18 and the 2nd pin of amplifier U1A, the other end of described resistance R18 connects first pin of amplifier U1A and one end of resistance R16 respectively, one end of the 3rd pin difference contact resistance R22 of amplifier U1A, one end of resistance R1 and one end of electric capacity C4, one end of the other end difference contact resistance R25 of described resistance R7, 6th pin of amplifier U1B and one end of electric capacity C5, the other end of described electric capacity C5 connects one end of electric capacity C23, one end of the 7th pin contact resistance R17 of described amplifier U1B, the other end of described resistance R25 connects one end of described resistance R17, one end of the 5th pin difference contact resistance R24 of described amplifier U1B, electric capacity C2 one end and resistance R8 one end.
In the circuit and charge-discharge control circuit of current measurement module, R3, R4, R5 and R6 are current sampling resistors, resistance after 4 parallel connections is 250 micro-ohms, through amplifying circuit U1A and U1B respectively current signal is amplified 27 times with 75 times, to realize the thick side of electric current and electric current accurate measurement, give A0 and the A3 of the MSP430G2533 of MCU, the A/D conversion accuracy of MSP430G2533 is 10 ADC.
Described MOSFET control module 5 comprises resistance R23, and one end of described resistance R23 connects one end of electric capacity C22, and the other end of described resistance R23 connects the source electrode of field effect transistor Q2 respectively, the source electrode of field effect transistor Q7, the source electrode of field effect transistor Q8, the source electrode of field effect transistor Q9, the source electrode of field effect transistor Q10, the other end of described electric capacity C22 connects the source electrode of field effect transistor Q1 respectively, the source electrode of field effect transistor Q3, the source electrode of field effect transistor Q4, the source electrode of field effect transistor Q5, the source electrode of field effect transistor Q6, described field effect transistor Q1, field effect transistor Q3, field effect transistor Q4, field effect transistor Q5, field effect transistor Q6, field effect transistor Q2, field effect transistor Q7, field effect transistor Q8, field effect transistor Q9, the drain electrode of field effect transistor Q10 is connected to each other, and the source electrode of described field effect transistor Q6 also distinguishes the collector electrode of connecting triode Q17, the positive pole of voltage stabilizing didoe D14 and one end of resistance R77, one end of the grid contact resistance R61 of described field effect transistor Q1, one end of the grid contact resistance R62 of described field effect transistor Q3, one end of the grid contact resistance R63 of described field effect transistor Q4, one end of the grid contact resistance R64 of described field effect transistor Q5, one end of the grid contact resistance R65 of described field effect transistor Q6, described resistance R61, resistance R62, resistance R63, resistance R64, one end of the other end difference contact resistance R71 of resistance R65, the other end of described resistance R71 connects the emitter of described triode Q17 and the negative pole of diode D15 respectively, the other end of one end difference contact resistance R77 of resistance R2, the negative pole of voltage stabilizing didoe D14, the base stage of triode Q17 and the positive pole of diode D15, the collector electrode of the other end connecting triode Q19 of described resistance R2, the base stage contact resistance R83 and resistance R82 respectively of described triode Q19, the collector electrode of the other end connecting triode Q22 of described resistance R82, base stage one end of contact resistance R81 and one end of resistance R86 respectively of described triode Q22, one end of the grid contact resistance R70 of described field effect transistor Q2, one end of the grid contact resistance R69 of described field effect transistor Q7, one end of the grid contact resistance R68 of described field effect transistor Q8, one end of the grid contact resistance R67 of described field effect transistor Q9, one end of the grid contact resistance R66 of described field effect transistor Q10, described resistance R66, resistance R67, resistance R68, one end of the other end difference contact resistance R72 of resistance R69 and resistance R70, one end of the other end difference contact resistance R 79 of described resistance R72, the emitter of triode Q18 and the emitter of triode Q21, one end of resistance R87 connects the other end of described resistance R79 respectively, the base stage of triode Q18 and the base stage of triode Q21, other end one end of contact resistance R80 and the collector electrode of triode Q20 respectively of described resistance R87, base stage one end of contact resistance R85 and one end of resistance R78 respectively of described triode Q20.
The circuit of MOSFET control module is with the main control loop of the N-channel MOS pipe of Q1 to Q10 composition, 5 Q1, Q3, Q4, Q5 and Q6 in parallel are the metal-oxide-semiconductor controlling charging, 5 Q2, Q7, Q8, Q9 and Q10 in parallel are the metal-oxide-semiconductor of controlled discharge, the drive circuit of triode Q18, Q20 and Q21 composition electric discharge metal-oxide-semiconductor, triode Q17, Q19, Q22 and diode D15 form the drive circuit of charging metal-oxide-semiconductor, such drive circuit, exactly in order to control loop metal-oxide-semiconductor break-make rapidly.
Described RS485 interface module 6 comprises chip U3, one end of the first pin contact resistance R21 of described chip U3, one end of the 3rd pin contact resistance R20 of described chip U3, 2nd pin of described chip U3 connects one end of electric capacity C24, 4th pin of described chip U3 connects one end of optocoupler U4 through resistance R88, other end one end of contact resistance R101 and the 4th pin of chip U7 respectively of optocoupler U4, one end of the 6th pin contact resistance R89 of described chip U3, the other end of described resistance R89 connects one end of optocoupler U5, the other end of described optocoupler U5 connects one end of electric capacity C42 respectively, one end of resistance R102 and the 2nd pin of chip U7 and the 3rd pin, one end of the 1st pin contact resistance R103 of described chip U7, the other end of described resistance R103 connects one end of optocoupler U, one end of the other end contact resistance R104 of described optocoupler U6, 5th pin one end of contact resistance R105 and the 2nd pin of chip U10 respectively of described chip U7, the 6th pin one end of contact resistance R107 and one end of resistance R106 respectively of described chip U7, one end of the 7th pin contact resistance R108 of described chip U7, the 8th pin other end of contact resistance R106 and one end of electric capacity C29 respectively of described chip U7, other end one end of contact resistance R109 and the 3rd pin of chip U10 respectively of described resistance R107, the other end of the 4th pin contact resistance R109 of described chip U10, 5th pin of described chip U10 connects one end of electric capacity C46 respectively, one end of electric capacity C28 and one end of inductance L 11, the other end of described inductance L 11 connects the 1st pin of binding post J3 and the 1st pin of binding post J2 respectively.
RS485 interface circuit adopts optically coupled circuit, its objective is in order to multimode connection in series-parallel, to reach the effect of isolation level.
Described MCU module 2 comprises chip U8, 1st pin of described chip U8 connects one end of electric capacity C25 respectively, one end of electric capacity C24, one end of resistance R110 and the 4th pin of binding post J4, the other end of described resistance R110 connects one end of electric capacity C47 and the 4th pin of binding post J4 respectively, 9th pin of described binding post J4 connects the other end of electric capacity C47, 7th pin of described binding post J4 connects the 8th pin of binding post J4 through resistance R111, one end of the 9th pin contact resistance R84 of described chip U8, the other end of described resistance R84 connects the grid of field effect transistor Q27, described field effect transistor Q27 drain electrode connect electric capacity C27 one end respectively, the positive pole of electric capacity C44 and the 1st pin of chip U9 and the 2nd pin, the source electrode of described field effect transistor Q27 connects the positive pole of electric capacity C45 and one end of electric capacity C30 respectively, the other end of described electric capacity C27 connects the negative pole of electric capacity C45 respectively, the other end of electric capacity C30, the negative pole of electric capacity C44, 3rd pin of chip U9 and the 4th pin, one end of electric capacity C26, the negative pole of electric capacity C43, the positive pole of voltage stabilizing didoe D16 and one end of electric capacity C41, 6th pin of described chip U9 is connected with the 7th pin, 8th pin of described chip U9 connects the other end of electric capacity C26 respectively, the positive pole of electric capacity C43 and the source electrode of field effect transistor Q26, the drain electrode contact resistance R98 respectively of described field effect transistor Q26, resistance R99, one end of resistance R100, one end of the grid contact resistance R97 of described field effect transistor Q26, the other end of described electric capacity C41 connects one end of inductance L 10, the other end contact resistance R97 respectively of described inductance L 10, resistance R98, resistance R99, the other end of resistance R100.
MCU adopts the internal resource of MSP430G2533IPW28, MSP430G2533 IPW28 to have: there is the Flash of 16KB in CODE space, the RAM of DATA space 512B, the ADC10 of 8 passages, 1 passage USCI A0/B0,24 I/O.
Described chip U8 adopts MSP430G2533PW28 chip; Described chip U9 adopts LP2951ACM-3.3 chip.
What described Battery disposal chip U2 adopted is QB76PL536A chip.
Described chip U adopts NL27WZ16 chip; Described chip U7 adopts MAX485 chip; Chip U10 adopts NUP420IMR6T1 chip.
The circuit of power module controls power supply using 10V as metal-oxide-semiconductor, and 3.3V is as the power supply of MCU.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all do within spirit of the present utility model and principle any amendment, equivalent to replace and improvement etc., all should be included within protection range of the present utility model.
Claims (10)
1. a control system for battery SOC management system, is characterized in that: this control system comprises battery management module, balance module, current measurement module, MOSFET control module, RS485 interface module, MCU module, temperature sampling module, battery pack and power module, the output of described battery management module connects the input of described balance module and the input of described temperature sampling module respectively, described battery management module input connects the both positive and negative polarity of described battery pack, the input of described battery management module connects the output of described MCU module, the output of described MCU module connects the input of described MOSFET control module and the input of RS485 interface module respectively, the output of described MOSFET control module connects the input of described battery management module, the input of described MCU module connects the described output of temperature sampling module and the output of current measurement module respectively, the input of described current measurement module connects the negative pole of described battery pack, and described power module is electrically connected described battery management module respectively, balance module, current measurement module, MOSFET control module, RS485 interface module, MCU module and temperature sampling module.
2. control system according to claim 1, it is characterized in that, described battery management module comprises Battery disposal chip U2, 16th pin of described Battery disposal chip U2 connects one end of electric capacity C35, 17th pin of described Battery disposal chip U2 connects one end of electric capacity C31 and one end of electric capacity C18 respectively, 18th pin of described Battery disposal chip U2 connects one end of electric capacity C32 and one end of electric capacity C19 respectively, 19th pin of described Battery disposal chip U2 is through resistance R75 one end of contact resistance R73 and one end of electric capacity C36 respectively, the other end of described resistance R73 connects one end of thermistor NTC1, 20th pin of described Battery disposal chip U2 connects one end of described electric capacity C36, 31st pin of described Battery disposal chip U2 is through resistance R49 one end of contact resistance R32 and the grid of field effect transistor Q23 respectively, the other end of described resistance R32 connects the source electrode of described field effect transistor Q23, the drain electrode of described field effect transistor Q23 is through the negative pole of resistance R90 connecting luminous diode LED1, 32nd pin of described Battery disposal chip U2 connects one end of electric capacity C33 and one end of electric capacity C20 respectively, one end of the 38th pin contact resistance R92 of described Battery disposal chip U2, one end of the 39th pin contact resistance R93 of described Battery disposal chip U2, the 40th pin one end of contact resistance R94 and one end of resistance R42 respectively of described Battery disposal chip U2, one end of the 41st pin contact resistance R95 of described Battery disposal chip U2, the 42nd pin one end of contact resistance R96 and one end of resistance R41 respectively of described Battery disposal chip U2, the 45th pin one end of contact resistance R58 and one end of resistance R34 respectively of described Battery disposal chip U2, one end of the other end contact resistance R59 of described resistance R34, the other end of described resistance R59 connects the drain electrode of field effect transistor Q25, grid one end of contact resistance R57 and one end of resistance R33 respectively of described field effect transistor Q25, the other end of described resistance R58 connects the grid of field effect transistor Q24, the drain electrode of described field effect transistor Q24 is through the negative pole of resistance R91 connecting luminous diode LED2, one end of the 52nd pin resistance R60 of described Battery disposal chip U2, one end of the 53rd pin contact resistance R56 of described Battery disposal chip U2, the 54th pin one end of contact resistance R55 and one end of electric capacity C40 respectively of described Battery disposal chip U2, one end of the 55th pin contact resistance R54 of described Battery disposal chip U2, the 56th pin one end of contact resistance R53 and one end of electric capacity C39 respectively of described Battery disposal chip U2, the 57th pin one end of contact resistance R52 and one end of electric capacity C38 respectively of described Battery disposal chip U2, one end of the 58th pin contact resistance R51 of described Battery disposal chip U2, one end of the 59th pin contact resistance R50 of described Battery disposal chip U2, 60th pin of described Battery disposal chip U2 is through resistance R76 one end of contact resistance R74 and one end of electric capacity C37 respectively, the other end of described resistance R74 connects one end of thermistor NTC2, 64th pin of described Battery disposal chip U2 connects one end of electric capacity C21 and the negative pole of voltage stabilizing didoe D13 respectively.
3. control system according to claim 2, it is characterized in that, described balance module comprises binding post J1, the 1st pin one end of contact resistance R15 and one end of inductance L 9 respectively of described binding post J1, and the other end of described inductance L 9 connects one end of electric capacity C11 respectively, the negative pole of voltage stabilizing didoe D6, one end of resistance R14 and one end of resistance R48, the other end of described resistance R48 connects one end of electric capacity C17, and the other end of described resistance R14 connects the drain electrode of field effect transistor Q16, one end of the grid difference contact resistance R31 of described field effect transistor Q16, the negative pole of voltage stabilizing didoe D12 and one end of resistance R40, the 2nd pin of described binding post J1 connects one end of inductance L 8, and the other end of described inductance L 8 connects the other end of electric capacity C11 respectively, the positive pole of voltage stabilizing didoe D6, the source electrode of field effect transistor Q16, the other end of resistance R31, the positive pole of voltage stabilizing didoe D12, one end of resistance R47, one end of resistance R13, one end of voltage stabilizing didoe D5 and one end of electric capacity C10, the other end of described resistance R47 connects one end of electric capacity C16, and the other end of described resistance R13 connects the drain electrode of field effect transistor Q15, one end of the grid difference contact resistance R30 of described field effect transistor Q15, the negative pole of voltage stabilizing didoe D11 and one end of resistance R39, the 3rd pin of described binding post J1 connects the other end of described resistance R15 and one end of inductance L 7 respectively, and the other end of described inductance L 7 connects the other end of electric capacity C10 respectively, the positive pole of voltage stabilizing didoe D5, the source electrode of field effect transistor Q15, the other end of resistance R30, the positive pole of voltage stabilizing didoe D11, one end of resistance R46, one end of resistance R12, the negative pole of voltage stabilizing didoe D4, one end of electric capacity C9, the other end of described resistance R46 connects one end of electric capacity C15, and the other end of described resistance R12 connects the drain electrode of field effect transistor Q14, one end of the grid difference contact resistance R29 of described field effect transistor Q14, the negative pole of voltage stabilizing didoe D10 and one end of resistance R38, described binding post J1 the 4th pin connects one end of inductance L 6, and the other end of described inductance L 6 connects the other end of electric capacity C9 respectively, the positive pole of voltage stabilizing didoe D4, the source electrode of field effect transistor Q14, the other end of resistance R29, the positive pole of voltage stabilizing didoe D10, one end of resistance R45, one end of resistance R11, the negative pole of voltage stabilizing didoe D3 and one end of electric capacity C8, the other end of described resistance R45 connects one end of electric capacity C14, and the other end of described resistance R11 connects the drain electrode of field effect transistor Q13, one end of the grid difference contact resistance R28 of described field effect transistor Q13, the negative pole of voltage stabilizing didoe D9 and one end of resistance R37, the 5th pin of described binding post J1 connects one end of inductance L 5, and the other end of described inductance L 5 connects the other end of electric capacity C8 respectively, the positive pole of voltage stabilizing didoe D3, the source electrode of field effect transistor Q13, the other end of resistance R28, the positive pole of voltage stabilizing didoe D9, one end of resistance R44, one end of resistance R10, the negative pole of voltage stabilizing didoe D2 and one end of electric capacity C7, the other end of described resistance R44 connects one end of electric capacity C13, and the other end of described resistance R10 connects the drain electrode of field effect transistor Q12, one end of the grid difference contact resistance R27 of described field effect transistor Q12, the negative pole of voltage stabilizing didoe D8 and one end of resistance R36, the 6th pin of described binding post J1 connects one end of inductance L 4, and the other end of described inductance L 4 connects the other end of electric capacity C7 respectively, the positive pole of voltage stabilizing didoe D2, the source electrode of field effect transistor Q12, the other end of resistance R27, the positive pole of voltage stabilizing didoe D8, resistance R43, one end of resistance R9, the negative pole of voltage stabilizing didoe D1 and one end of electric capacity C6, the other end of described resistance R43 connects one end of electric capacity C12, and the other end of described resistance R9 connects the drain electrode of field effect transistor Q11, one end of the grid difference contact resistance R27 of described field effect transistor Q11, the negative pole of voltage stabilizing didoe D7 and one end of resistance R35, the 7th pin of described binding post J1 connects one end of inductance L 3, and the other end of described inductance L 3 connects the other end of electric capacity C6 respectively, the positive pole of voltage stabilizing didoe D1, the source electrode of field effect transistor Q11, the other end of resistance R26 and the positive pole of voltage stabilizing didoe D7.
4. control system according to claim 3, is characterized in that, described current measurement module comprises resistance R3 in parallel, resistance R4, resistance R5, resistance R6, resistance R3, resistance R4, resistance R5, one end after resistance R6 parallel connection connects one end of inductance L 2, resistance R3, resistance R4, resistance R5, the other end after resistance R6 parallel connection is through inductance L 1 ground connection, and the other end of described inductance L 2 connects one end of electric capacity C1 respectively, one end of resistance R19 and one end of resistance R7, the other end of described resistance R19 connects one end of electric capacity C3 respectively, one end of resistance R18 and the 2nd pin of amplifier U1A, the other end of described resistance R18 connects first pin of amplifier U1A and one end of resistance R16 respectively, one end of the 3rd pin difference contact resistance R22 of amplifier U1A, one end of resistance R1 and one end of electric capacity C4, one end of the other end difference contact resistance R25 of described resistance R7, 6th pin of amplifier U1B and one end of electric capacity C5, the other end of described electric capacity C5 connects one end of electric capacity C23, one end of the 7th pin contact resistance R17 of described amplifier U1B, the other end of described resistance R25 connects one end of described resistance R17, one end of the 5th pin difference contact resistance R24 of described amplifier U1B, electric capacity C2 one end and resistance R8 one end.
5. control system according to claim 4, is characterized in that, described MOSFET control module comprises resistance R23, and one end of described resistance R23 connects one end of electric capacity C22, and the other end of described resistance R23 connects the source electrode of field effect transistor Q2 respectively, the source electrode of field effect transistor Q7, the source electrode of field effect transistor Q8, the source electrode of field effect transistor Q9, the source electrode of field effect transistor Q10, the other end of described electric capacity C22 connects the source electrode of field effect transistor Q1 respectively, the source electrode of field effect transistor Q3, the source electrode of field effect transistor Q4, the source electrode of field effect transistor Q5, the source electrode of field effect transistor Q6, described field effect transistor Q1, field effect transistor Q3, field effect transistor Q4, field effect transistor Q5, field effect transistor Q6, field effect transistor Q2, field effect transistor Q7, field effect transistor Q8, field effect transistor Q9, the drain electrode of field effect transistor Q10 is connected to each other, and the source electrode of described field effect transistor Q6 also distinguishes the collector electrode of connecting triode Q17, the positive pole of voltage stabilizing didoe D14 and one end of resistance R77, one end of the grid contact resistance R61 of described field effect transistor Q1, one end of the grid contact resistance R62 of described field effect transistor Q3, one end of the grid contact resistance R63 of described field effect transistor Q4, one end of the grid contact resistance R64 of described field effect transistor Q5, one end of the grid contact resistance R65 of described field effect transistor Q6, described resistance R61, resistance R62, resistance R63, resistance R64, one end of the other end difference contact resistance R71 of resistance R65, the other end of described resistance R71 connects the emitter of described triode Q17 and the negative pole of diode D15 respectively, the other end of one end difference contact resistance R77 of resistance R2, the negative pole of voltage stabilizing didoe D14, the base stage of triode Q17 and the positive pole of diode D15, the collector electrode of the other end connecting triode Q19 of described resistance R2, the base stage contact resistance R83 and resistance R82 respectively of described triode Q19, the collector electrode of the other end connecting triode Q22 of described resistance R82, base stage one end of contact resistance R81 and one end of resistance R86 respectively of described triode Q22, one end of the grid contact resistance R70 of described field effect transistor Q2, one end of the grid contact resistance R69 of described field effect transistor Q7, one end of the grid contact resistance R68 of described field effect transistor Q8, one end of the grid contact resistance R67 of described field effect transistor Q9, one end of the grid contact resistance R66 of described field effect transistor Q10, described resistance R66, resistance R67, resistance R68, one end of the other end difference contact resistance R72 of resistance R69 and resistance R70, one end of the other end difference contact resistance R 79 of described resistance R72, the emitter of triode Q18 and the emitter of triode Q21, one end of resistance R87 connects the other end of described resistance R79 respectively, the base stage of triode Q18 and the base stage of triode Q21, other end one end of contact resistance R80 and the collector electrode of triode Q20 respectively of described resistance R87, base stage one end of contact resistance R85 and one end of resistance R78 respectively of described triode Q20.
6. control system according to claim 5, it is characterized in that, described RS485 interface module comprises chip U3, one end of the first pin contact resistance R21 of described chip U3, one end of the 3rd pin contact resistance R20 of described chip U3, 2nd pin of described chip U3 connects one end of electric capacity C24, 4th pin of described chip U3 connects one end of optocoupler U4 through resistance R88, other end one end of contact resistance R101 and the 4th pin of chip U7 respectively of optocoupler U4, one end of the 6th pin contact resistance R89 of described chip U3, the other end of described resistance R89 connects one end of optocoupler U5, the other end of described optocoupler U5 connects one end of electric capacity C42 respectively, one end of resistance R102 and the 2nd pin of chip U7 and the 3rd pin, one end of the 1st pin contact resistance R103 of described chip U7, the other end of described resistance R103 connects one end of optocoupler U, one end of the other end contact resistance R104 of described optocoupler U6, 5th pin one end of contact resistance R105 and the 2nd pin of chip U10 respectively of described chip U7, the 6th pin one end of contact resistance R107 and one end of resistance R106 respectively of described chip U7, one end of the 7th pin contact resistance R108 of described chip U7, the 8th pin other end of contact resistance R106 and one end of electric capacity C29 respectively of described chip U7, other end one end of contact resistance R109 and the 3rd pin of chip U10 respectively of described resistance R107, the other end of the 4th pin contact resistance R109 of described chip U10, 5th pin of described chip U10 connects one end of electric capacity C46 respectively, one end of electric capacity C28 and one end of inductance L 11, the other end of described inductance L 11 connects the 1st pin of binding post J3 and the 1st pin of binding post J2 respectively.
7. control system according to claim 6, it is characterized in that, described MCU module comprises chip U8, 1st pin of described chip U8 connects one end of electric capacity C25 respectively, one end of electric capacity C24, one end of resistance R110 and the 4th pin of binding post J4, the other end of described resistance R110 connects one end of electric capacity C47 and the 4th pin of binding post J4 respectively, 9th pin of described binding post J4 connects the other end of electric capacity C47, 7th pin of described binding post J4 connects the 8th pin of binding post J4 through resistance R111, one end of the 9th pin contact resistance R84 of described chip U8, the other end of described resistance R84 connects the grid of field effect transistor Q27, described field effect transistor Q27 drain electrode connect electric capacity C27 one end respectively, the positive pole of electric capacity C44 and the 1st pin of chip U9 and the 2nd pin, the source electrode of described field effect transistor Q27 connects the positive pole of electric capacity C45 and one end of electric capacity C30 respectively, the other end of described electric capacity C27 connects the negative pole of electric capacity C45 respectively, the other end of electric capacity C30, the negative pole of electric capacity C44, 3rd pin of chip U9 and the 4th pin, one end of electric capacity C26, the negative pole of electric capacity C43, the positive pole of voltage stabilizing didoe D16 and one end of electric capacity C41, 6th pin of described chip U9 is connected with the 7th pin, 8th pin of described chip U9 connects the other end of electric capacity C26 respectively, the positive pole of electric capacity C43 and the source electrode of field effect transistor Q26, the drain electrode contact resistance R98 respectively of described field effect transistor Q26, resistance R99, one end of resistance R100, one end of the grid contact resistance R97 of described field effect transistor Q26, the other end of described electric capacity C41 connects one end of inductance L 10, the other end contact resistance R97 respectively of described inductance L 10, resistance R98, resistance R99, the other end of resistance R100.
8. control system according to claim 7, is characterized in that, described chip U8 adopts MSP430G2533PW28 chip; Described chip U9 adopts LP2951ACM-3.3 chip.
9. control system according to claim 8, is characterized in that, what described Battery disposal chip U2 adopted is QB76PL536A chip.
10. control system according to claim 8, is characterized in that, described chip U adopts NL27WZ16 chip; Described chip U7 adopts MAX485 chip; Chip U10 adopts NUP420IMR6T1 chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420767983.7U CN204290400U (en) | 2014-12-08 | 2014-12-08 | A kind of control system of battery SOC management system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420767983.7U CN204290400U (en) | 2014-12-08 | 2014-12-08 | A kind of control system of battery SOC management system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204290400U true CN204290400U (en) | 2015-04-22 |
Family
ID=52873529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420767983.7U Expired - Fee Related CN204290400U (en) | 2014-12-08 | 2014-12-08 | A kind of control system of battery SOC management system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204290400U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105576775A (en) * | 2016-03-06 | 2016-05-11 | 唐山工业职业技术学院 | Power lithium ion battery management system |
| CN106199433A (en) * | 2015-05-29 | 2016-12-07 | 丰田自动车株式会社 | The impairment grade computational methods of lithium rechargeable battery, control method and control device |
| CN107870306A (en) * | 2017-12-11 | 2018-04-03 | 重庆邮电大学 | A kind of lithium battery charge state prediction algorithm based under deep neural network |
| CN109878377A (en) * | 2019-04-19 | 2019-06-14 | 惠州市盛微电子有限公司 | Battery management system |
| CN110568365A (en) * | 2019-08-08 | 2019-12-13 | 深圳职业技术学院 | lithium battery monitoring system |
| CN110736418A (en) * | 2019-11-14 | 2020-01-31 | 深圳职业技术学院 | bridge expansion joint monitoring device |
-
2014
- 2014-12-08 CN CN201420767983.7U patent/CN204290400U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106199433A (en) * | 2015-05-29 | 2016-12-07 | 丰田自动车株式会社 | The impairment grade computational methods of lithium rechargeable battery, control method and control device |
| CN106199433B (en) * | 2015-05-29 | 2018-12-28 | 丰田自动车株式会社 | Impairment grade calculation method, control method and the control device of lithium ion secondary battery |
| CN105576775A (en) * | 2016-03-06 | 2016-05-11 | 唐山工业职业技术学院 | Power lithium ion battery management system |
| CN107870306A (en) * | 2017-12-11 | 2018-04-03 | 重庆邮电大学 | A kind of lithium battery charge state prediction algorithm based under deep neural network |
| CN109878377A (en) * | 2019-04-19 | 2019-06-14 | 惠州市盛微电子有限公司 | Battery management system |
| CN109878377B (en) * | 2019-04-19 | 2024-03-22 | 惠州市盛微电子有限公司 | Battery management system |
| CN110568365A (en) * | 2019-08-08 | 2019-12-13 | 深圳职业技术学院 | lithium battery monitoring system |
| CN110736418A (en) * | 2019-11-14 | 2020-01-31 | 深圳职业技术学院 | bridge expansion joint monitoring device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN204290400U (en) | A kind of control system of battery SOC management system | |
| CN103884993B (en) | The SOC on-line checkingi of lithium ion battery in process of charging and modification method | |
| CN112331941B (en) | Cloud auxiliary battery management system and method | |
| CN103887853B (en) | A kind of Li-ion batteries piles balance control method | |
| CN201360156Y (en) | Charging and discharging management system for improving safety and service life of series-connected battery set | |
| CN105489962A (en) | Recycling method for waste power lithium ion batteries | |
| CN111366864B (en) | Battery SOH on-line estimation method based on fixed voltage rise interval | |
| CN206742907U (en) | A kind of complete intelligent lithium titanate battery group management system | |
| CN102967831B (en) | On-line detection system and detection method of lead-acid storage battery performance | |
| Lin et al. | Battery management system with dual-balancing mechanism for LiFePO 4 battery module | |
| CN103178620B (en) | Mobile photovoltaic power generation and off-peak electricity energy storage control system for lithium batteries | |
| CN106655301A (en) | Power management system and method suitable for electric fork-lift truck | |
| CN113489094A (en) | Method, circuit and system for drive equalization of battery packs in BMS | |
| CN105161756A (en) | Lithium iron phosphate lithium-ion battery with electricity exhaustion early-warning function | |
| CN203951227U (en) | A kind of battery management control device with the moving equalization function of main quilt | |
| CN205246835U (en) | Lithium battery power management system based on DS2788 | |
| CN104953671A (en) | Power self-management device for agricultural tracked robot serving as mobile node of Internet of Things | |
| CN202631711U (en) | Consistency on-line monitoring device for motive power battery pack for electric automobile | |
| CN202432935U (en) | Rocket-borne data test system | |
| Wang et al. | Battery management system design for industrial manufacture | |
| CN214539355U (en) | Device for detecting thermal stability of battery material in situ | |
| CN2864701Y (en) | Modular for measuring thermistor in lithium-ion battery group protection circuit by using difference method | |
| CN104242358B (en) | A kind of electric automobile ferric phosphate lithium cell group tertiary management system | |
| CN207772912U (en) | Battery management system | |
| CN102680902A (en) | Consistency on-line monitoring device and method for motive power battery pack for electric automobile |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150422 Termination date: 20181208 |