CN204289448U - Array base palte and display unit - Google Patents
Array base palte and display unit Download PDFInfo
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- CN204289448U CN204289448U CN201420711074.1U CN201420711074U CN204289448U CN 204289448 U CN204289448 U CN 204289448U CN 201420711074 U CN201420711074 U CN 201420711074U CN 204289448 U CN204289448 U CN 204289448U
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Abstract
The utility model relates to Display Technique field, discloses a kind of array base palte and display unit.Holding wire on described array base palte comprises at least two conductive layers be electrically connected, described holding wire comprises grid line, data wire and common signal line, in described grid line, data wire and common signal line only one or arbitrarily two or three comprise at least two be electrically connected conductive layers.Described display unit comprises described array base palte.When fracture occurs a conductive layer of holding wire, can other conductive layer signal transmissions be passed through, improve the reliability that holding wire electrically conducts, and then improve the yield of display unit.Further, in the existing multiple conductive layer pattern manufacture craft of array base palte, form multiple conductive layers of holding wire simultaneously, thus do not need to make holding wire separately, simplify manufacture craft.
Description
Technical field
The utility model relates to Display Technique field, particularly relates to a kind of array base palte and display unit.
Background technology
Along with Display Technique development, the pixel of display unit is more and more higher, and resolution (PPI) is also more and more higher, but pixel aperture ratio still remains unchanged, and increases even to some extent.In order to meet the demand, more and more thinner for the holding wire to pixel cell signal transmission on array base palte, make in the course of processing at array base palte, fluctuate by manufacture craft and equipment, or environmental impact, cause holding wire often to rupture.
Utility model content
The utility model provides a kind of array base palte, comparatively thin in order to the width solved due to holding wire, and the problem of fracture easily occurs in manufacture craft.
The utility model also provides a kind of display unit, and it comprises above-mentioned array base palte, in order to provide the yield of display unit.
For solving the problems of the technologies described above, the utility model provides a kind of array base palte, comprises the holding wire for signal transmission, it is characterized in that, described holding wire comprises at least two conductive layers be electrically connected.
Array base palte as above, preferably, described array base palte is thin-film transistor array base-plate, comprises thin-film transistor;
Described holding wire comprises:
The grid line of cross-distribution and data wire, described grid line is connected with the gate electrode of thin-film transistor, and described data wire is connected with the source electrode of thin-film transistor;
Common signal line, for providing reference voltage;
In described grid line, data wire and common signal line only one or arbitrarily two or three comprise at least two be electrically connected conductive layers.
Array base palte as above, preferably, described array base palte also comprises pixel electrode;
Described at least two conductive layers be electrically connected comprise transparency conducting layer, and described transparency conducting layer and pixel electrode are same Rotating fields.
Array base palte as above, preferably, the width of described transparency conducting layer is greater than the width of other conductive layers.
Array base palte as above, preferably, described grid line, data wire and common signal line include at least two conductive layers be electrically connected.
Array base palte as above, preferably, described grid line, data wire and common signal line include two conductive layers be electrically connected.
Array base palte as above, preferably, described grid line comprises grid metal level and source and drain metal level, and the width of the source and drain metal level of described grid line is not more than the width of grid metal level, and the source and drain metal level of described grid line and data wire are same Rotating fields.
Array base palte as above, preferably, described data wire comprises source and drain metal level and grid metal level, and the width of the grid metal level of described data wire is not more than the width of source and drain metal level, and the grid metal level of described data wire and grid line are same Rotating fields.
Array base palte as above, preferably, described common signal line comprises grid metal level and source and drain metal level, and the grid metal level of described common signal line and grid line are same Rotating fields, and the source and drain metal level of described common signal line and data wire are same Rotating fields.
The utility model also provides a kind of display unit, comprises array base palte as above.
The beneficial effect of technique scheme of the present utility model is as follows:
In technique scheme, comprise at least two conductive layers be electrically connected by the holding wire arranged on array base palte, when fracture occurs a conductive layer, can other conductive layer signal transmissions be passed through, improve the reliability that holding wire electrically conducts, and then improve the yield of display unit.Further, in the existing multiple conductive layer pattern manufacture craft of array base palte, form multiple conductive layers of holding wire simultaneously, thus do not need to make holding wire separately, simplify manufacture craft.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 represents the structural representation of array base palte in prior art;
Fig. 2 represents the cutaway view of Fig. 1 along A-A;
Fig. 3 represents the structural representation one of array base palte in the utility model embodiment;
Fig. 4 represents the cutaway view of Fig. 3 along A-A;
Fig. 5 represents the structural representation two of array base palte in the utility model embodiment;
Fig. 6 represents the cutaway view of Fig. 5 along A-A;
Embodiment
In order to the width solved due to holding wire is thinner, the problem of fracture is easily there is in manufacture craft, the utility model provides a kind of array base palte, it comprises at least two conductive layers be electrically connected for the holding wire of signal transmission, when there is fracture in a conductive layer, can other conductive layer signal transmissions be passed through, improve the reliability that holding wire electrically conducts, and then improve the yield of display unit.
Correspondingly, the manufacture method of array base palte comprises:
Form the holding wire being used for signal transmission, described holding wire comprises at least two conductive layers be electrically connected.
For the thin-film transistor array base-plate of liquid crystal indicator, the holding wire on it comprises grid line, data wire and common signal line.For the array base palte of organic LED display device, the holding wire on it comprises grid line, data wire and driving power supply line.
Below in conjunction with drawings and Examples, embodiment of the present utility model is described in further detail.Following examples for illustration of the utility model, but are not used for limiting scope of the present utility model.
For the thin-film transistor array base-plate of liquid crystal indicator in the utility model embodiment, specifically introduce the technical solution of the utility model.
The agent structure of liquid crystal indicator is liquid crystal panel, and liquid crystal panel comprises color membrane substrates to box and array base palte.Wherein, as shown in Figure 1, thin-film transistor array base-plate comprises grid line 1 and the data wire 2 of cross-distribution, and for limiting pixel region, each pixel region comprises thin-film transistor 8 and pixel electrode 3.The drain electrode of pixel electrode and 3 thin-film transistors 8 is electrically connected.Grid line 1 is connected with the gate electrode of thin-film transistor 8, for transmitting sweep signal, opens the thin-film transistor 8 of often going line by line.Data wire 2 is connected with the source electrode of every row thin-film transistor 8, and for transmitting pixel data, when thin-film transistor 8 is opened, the pixel voltage on data wire 2 transfers to pixel electrode 3 by thin-film transistor 8.
Liquid crystal panel also comprises the public electrode be formed on array base palte or color membrane substrates, and is formed on array base palte, provides the common signal line (not shown) of reference voltage for public electrode.The angle preset of the electric field driven liquid crystal deflecting element that public electrode and pixel electrode 3 are formed, realizes display.
In prior art, shown in composition graphs 1 and Fig. 2, grid line 1 is formed by same grid metallic film with the gate electrode of thin-film transistor 8, is structure as a whole.Data wire 2 is formed by same source and drain metallic film with the source electrode of thin-film transistor 8, is structure as a whole.Common signal line can be formed by same grid metallic film with grid line 1, gate electrode, also can be formed by same source and drain metallic film with data wire 2, source electrode.
Only one or two or three comprise at least two conductive layers be electrically connected arbitrarily in the utility model embodiment in the grid line of array base palte, data wire and common signal line, comparatively thin in order to solve holding wire, often there is the problem of fracture.
Correspondingly, step array base palte forming holding wire comprises:
Form grid line 1 and the data wire 2 of cross-distribution, grid line 1 is connected with the gate electrode of thin-film transistor 8, and data wire 2 is connected with the source electrode of thin-film transistor 8;
Form common signal line, for providing reference voltage;
In grid line 1, data wire 2 and common signal line only one or arbitrarily two or three comprise at least two be electrically connected conductive layers.
Best mode arranges the grid line of array base palte, data wire and common signal line to include at least two conductive layers be electrically connected, and generally comprising two conductive layers be electrically connected can satisfy the demands, and technique is simple.
Preferably, one of them conductive layer of holding wire is transparency conducting layer, and described transparency conducting layer and pixel electrode are same Rotating fields (being formed by same transparent conductive film), does not need to be formed by independent manufacture craft, Simplified flowsheet.Concrete manufacture craft is:
Form transparent conductive film, patterning processes is carried out to described transparent conductive film, form pixel electrode, and the transparency conducting layer in described at least two conductive layers be electrically connected.
The material of described transparent conductive film can be ITO or IZO, described patterning processes comprises the coating of photoresist, exposure and development, and transparent conductive film is etched using photoresist as stop, form pixel electrode, and the transparency conducting layer in described at least two conductive layers be electrically connected.
Because transparency conducting layer can not affect pixel aperture ratio, the width of the transparency conducting layer of signalization line further can be greater than the width of other conductive layers, guarantee that transparency conducting layer can not be subject to manufacture craft and equipment fluctuation or environmental impact and rupture, ensure that the transmission performance of holding wire.Certainly, also the transparency conducting layer width of signalization line the width of other conductive layers can be not more than.
When one of them conductive layer of holding wire is transparency conducting layer, the grid line of thin-film transistor array base-plate can comprise grid metal level and transparency conducting layer two conductive layers, or grid metal level, transparency conducting layer and source and drain metal level three conductive layers.Data wire can comprise source and drain metal level and transparency conducting layer two conductive layers, or grid metal level, transparency conducting layer and source and drain metal level three conductive layers.Common signal line can comprise source and drain metal level and transparency conducting layer two conductive layers, grid metal level and transparency conducting layer two conductive layers, or grid metal level, transparency conducting layer and source and drain metal level three conductive layers.Wherein, the grid metal level of holding wire can be same Rotating fields with grid line, is formed by same grid metallic film.The source and drain metal level of holding wire can be same Rotating fields with data wire, is formed by same source and drain metallic film.Owing to forming multiple conductive layers of holding wire in existing multiple conductive layer pattern manufacture craft simultaneously, thus do not need to make holding wire separately, simplify the manufacture craft of array base palte.
In order to not affect pixel aperture ratio, when the newly-increased conductive layer of holding wire comprises opaque conductive layer, the width of the opaque conductive layer of signalization line is not more than the width of former conductive layer.
It should be noted that, in the utility model embodiment, the former conductive layer of holding wire refers to that conductive layer that in prior art, holding wire only comprises.Such as: the former conductive layer of grid line is grid metal level, the former conductive layer of data wire is source and drain metal level, and the former conductive layer of common signal line is data line layer or source and drain metal level.
In a concrete execution mode, the holding wire on array base palte includes two conductive layers, and another conductive layer of holding wire is not transparency conducting layer, and is formed by other materials film.Such as: grid line comprises grid metal level and source and drain metal level two conductive layers, data wire comprises grid metal level and source and drain metal level two conductive layers, and common signal line comprises grid metal level and source and drain metal level.Wherein, the source and drain metal level of grid line can be same Rotating fields with data wire, is formed by same source and drain metallic film.The grid metal level of data wire and grid line are same Rotating fields, are formed by same grid metallic film.The grid metal level of common signal line and grid line are same Rotating fields, are formed by same grid metallic film.The source and drain metal level of described common signal line and data wire are same Rotating fields, are formed by same source and drain metallic film.
Further, in order to not affect pixel aperture ratio, the width of the opaque conductive layer of signalization line is not more than the width of former conductive layer, namely, the width of the source and drain metal level of grid line is not more than the width of grid metal level, and the width of the grid metal level of data wire is not more than the width of source and drain metal level.
Then, the manufacture method of thin-film transistor array base-plate comprises:
Form grid metallic film, patterning processes is carried out to described grid metallic film, form the grid metal level of grid line, the grid metal level of data wire, and the grid metal level of common signal line;
Form source and drain metallic film, patterning processes is carried out to described source and drain metallic film, form the source and drain metal level of data wire, the source and drain metal level of grid line, and the source and drain metal level of common signal line.
Shown in composition graphs 3 and Fig. 4, a concrete structure of thin-film transistor array base-plate in the utility model embodiment, its manufacturing process is:
Step S1, provide a transparent substrates substrate 5, as: glass substrate, quartz base plate, organic resin substrate;
Step S2, formation gate electrode (not shown), grid line 1 and common signal line (not shown) on underlay substrate 5;
Wherein, gate electrode, grid line 1 and common signal line are formed by same grid metallic film, and the material of grid metallic film can be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, the alloy of the metals such as W and these metals, grid metal level can be single layer structure or sandwich construction, and sandwich construction is Cu Mo such as, Ti Cu Ti, Mo Al Mo etc.
Step S3, on the underlay substrate 5 of completing steps S2, form gate insulation layer 6;
The material of gate insulation layer 6 can select oxide, nitride or nitrogen oxide, can be individual layer, bilayer or sandwich construction.Particularly, gate insulation layer 6 can be SiNx, SiOx or Si (ON) x;
Step S4, on the underlay substrate 5 of completing steps S3, be formed with active layer pattern (not shown), the material of active layer can be Si semiconductor, also can be metal-oxide semiconductor (MOS);
Step S5, on the underlay substrate 5 of completing steps S4, form the transparency conducting layer 4 of pixel electrode 3 and data wire 2, wherein, pixel electrode 3 and transparency conducting layer 4 are formed by same transparent conductive film.The material of transparent conductive film can be ITO or IZO;
Step S6, on the underlay substrate 5 of completing steps S5, form source electrode and drain electrode, and the source and drain metal level of data wire 2;
Wherein, the source and drain metal level of source electrode, drain electrode and data wire 2 is formed by same source and drain metallic film.The material of source and drain metallic film can be the alloy of the metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and these metals.Source and drain metallic film can be single layer structure or sandwich construction, sandwich construction such as Cu Mo, Ti Cu Ti, Mo Al Mo etc.;
Step S7, on the underlay substrate 5 of completing steps S6, form passivation layer 7;
The material of passivation layer 7 can select oxide, nitride or nitrogen oxide, can be individual layer, bilayer or sandwich construction.Particularly, passivation layer 7 can be SiNx, SiOx or Si (ON) x.
Step S8, on the underlay substrate 5 of completing steps S7, form slit public electrode (not shown), be electrically connected by the via hole in passivation layer 7 and common signal line.
Described public electrode is formed by transparent conductive film.
In said structure, the driving electric field of liquid crystal panel is transverse electric field, and public electrode is formed on array base palte.Thin-film transistor array base-plate is bottom gate thin film transistor array base palte, and data wire 2 comprises source and drain metal level and transparency conducting layer 4, and wherein, transparency conducting layer 4 is positioned at below source and drain metal level, and the width of transparency conducting layer 4 is greater than the width of source and drain metal level.Shown in composition graphs 5 and Fig. 6, also can, by the reversed order of step S5 and step S6, the transparency conducting layer 4 of data wire 2 be made to be positioned at source and drain metal layer.
When the driving electric field of liquid crystal panel is longitudinal electric field, when public electrode is formed on color membrane substrates, only passivation layer 7 only cover film transistor 8 need be set.
When the grid line of array base palte and common signal line also comprise transparency conducting layer, while formation pixel electrode 3, the transparency conducting layer of grid line 1 and common signal line can be formed.
When the grid line 1 of array base palte and common signal line comprise source and drain metal level, while formation source electrode and drain electrode, the source and drain metal level of grid line 1 and common signal line can be formed.
When the data wire 2 of array base palte and common signal line comprise grid metal level, while formation gate electrode, the source and drain metal level of data wire 2 and common signal line can be formed.
The technical solution of the utility model is also applicable to top gate type thin film transistor array base palte, coplanar type thin-film transistor array base-plate.
When the technical solution of the utility model is applied to organic LED display device, manufacture craft and the thin-film transistor array base-plate of the newly-increased conductive layer of its holding wire are similar, are not described in detail in this.
Also provide a kind of display unit in the utility model embodiment, it comprises above-mentioned array base palte, thus improves the yield of product.
The technical solution of the utility model comprises at least two conductive layers be electrically connected by the holding wire arranged on array base palte, when there is fracture in a conductive layer, other conductive layer signal transmissions can be passed through, improve the reliability that holding wire electrically conducts, and then improve the yield of display unit.Further, in the existing multiple conductive layer pattern manufacture craft of array base palte, form multiple conductive layers of holding wire simultaneously, thus do not need to make holding wire separately, simplify manufacture craft.
The above is only preferred implementation of the present utility model; should be understood that; for those skilled in the art; under the prerequisite not departing from the utility model know-why; can also make some improvement and replacement, these improve and replace and also should be considered as protection range of the present utility model.
Claims (9)
1. an array base palte, comprises the holding wire for signal transmission, it is characterized in that, described holding wire comprises at least two conductive layers be electrically connected;
Described array base palte is thin-film transistor array base-plate, comprises thin-film transistor;
Described holding wire comprises:
The grid line of cross-distribution and data wire, described grid line is connected with the gate electrode of thin-film transistor, and described data wire is connected with the source electrode of thin-film transistor;
Common signal line, for providing reference voltage;
In described grid line, data wire and common signal line only one or arbitrarily two or three comprise at least two be electrically connected conductive layers.
2. array base palte according to claim 1, is characterized in that, described array base palte also comprises pixel electrode;
Described at least two conductive layers be electrically connected comprise transparency conducting layer, and described transparency conducting layer and pixel electrode are same Rotating fields.
3. array base palte according to claim 2, is characterized in that, the width of described transparency conducting layer is greater than the width of other conductive layers.
4. array base palte according to claim 1, is characterized in that, described grid line, data wire and common signal line include at least two conductive layers be electrically connected.
5. array base palte according to claim 4, is characterized in that, described grid line, data wire and common signal line include two conductive layers be electrically connected.
6. array base palte according to claim 5, it is characterized in that, described grid line comprises grid metal level and source and drain metal level, and the width of the source and drain metal level of described grid line is not more than the width of grid metal level, and the source and drain metal level of described grid line and data wire are same Rotating fields.
7. array base palte according to claim 5, it is characterized in that, described data wire comprises source and drain metal level and grid metal level, and the width of the grid metal level of described data wire is not more than the width of source and drain metal level, and the grid metal level of described data wire and grid line are same Rotating fields.
8. array base palte according to claim 5, it is characterized in that, described common signal line comprises grid metal level and source and drain metal level, and the grid metal level of described common signal line and grid line are same Rotating fields, and the source and drain metal level of described common signal line and data wire are same Rotating fields.
9. a display unit, comprises the array base palte described in any one of claim 1-8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420711074.1U CN204289448U (en) | 2014-11-24 | 2014-11-24 | Array base palte and display unit |
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| CN201420711074.1U CN204289448U (en) | 2014-11-24 | 2014-11-24 | Array base palte and display unit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104362155A (en) * | 2014-11-24 | 2015-02-18 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN111445801A (en) * | 2020-05-06 | 2020-07-24 | 京东方科技集团股份有限公司 | Display panel and display device |
-
2014
- 2014-11-24 CN CN201420711074.1U patent/CN204289448U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104362155A (en) * | 2014-11-24 | 2015-02-18 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| US9716112B2 (en) | 2014-11-24 | 2017-07-25 | Boe Technology Group Co., Ltd. | Array substrate, its manufacturing method and display device |
| CN104362155B (en) * | 2014-11-24 | 2017-12-08 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device |
| CN111445801A (en) * | 2020-05-06 | 2020-07-24 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2021223592A1 (en) * | 2020-05-06 | 2021-11-11 | 京东方科技集团股份有限公司 | Display panel and display device |
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