CN204287461U - The specified time delay detector of Intelligent substation merging unit - Google Patents
The specified time delay detector of Intelligent substation merging unit Download PDFInfo
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- CN204287461U CN204287461U CN201420744809.0U CN201420744809U CN204287461U CN 204287461 U CN204287461 U CN 204287461U CN 201420744809 U CN201420744809 U CN 201420744809U CN 204287461 U CN204287461 U CN 204287461U
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Abstract
The utility model discloses the specified time delay detector of a kind of Intelligent substation merging unit, comprise analogue collection module, it adopts independently high-speed dsp sampling, for gathering the analog quantity that conventional relay-protection tester exports and the accurate time of reception marking collection analog quantity, and transfer to CPU processing module; And digital data acquisition module, it adopts independently FPGA sampling, and for gathering the digital quantity that merge cells exports, and mark gathers the accurate time of reception of digital quantity, and transfers to CPU processing module; And CPU processing module, for recording ripple, storage and analytical sampling data, and convert sampled data to displayable waveform; And load module, it is connected with CPU processing module, starts record ripple for inputting and stops the order of record ripple; And gps clock module, for providing absolute time for analogue collection module, digital data acquisition module and CPU processing module.
Description
Technical field
The utility model relates to the specified time delay detector of a kind of Intelligent substation merging unit.
Background technology
Merge cells is in order to the physical location carrying out time correlation combination from the electric current of electronic mutual inductor two times transfer device and/or voltage data.Along with the expansion of electrical network intelligent substation Large scale construction, the importance of Intelligent substation merging unit is also more and more outstanding.The merge cells that current intelligent substation generally adopts, is input as analog quantity, exports as digital quantity.The constant time lag that primary current or voltage measured moment start delivery time to digital quantity is called the specified time delay of merge cells; if specified delayed setting mistake; be there is error in device samplings such as directly causing protection, metering, even cause protective device misoperation, thus cause major accident.
In intelligent substation on-the-spot test process, the measurement of the specified time delay of merge cells mainly contains two kinds of modes, and first kind of way is the markers utilizing hardware unit record merge cells input signal and output signal, by comparing calculation, draws the time delay of merge cells.For this mode, the zero crossing of merge cells input signal and signal output waveform, in the specified time delay of calculating, compares, thus calculates the specified time delay of merge cells by existing merge cells specified time delay detector.This method of testing have ignored the first cycle that merge cells exports sometimes, the merge cells accuracy of detection specified time delay being less than to 20ms (cycle) can meet the demands, but when the specified time delay of merge cells is equal to or greater than 20ms, this kind of detection method detect specified time delay be 0 or the testing result that provides be the numerical value being less than 20ms, can not correct result be provided.Such as: as merge cells time delay 20ms, detector judges that specified time delay is 0; As merge cells time delay 45ms, detector judges that specified time delay is 5ms.And having pertinent literature research to point out, it is large that this detection mode relates to data volume, and test result dispersion is large, is unfavorable for the judge to test result.The second way be utilize wave recording device contrast through merge cells transmission with the two paths of signals transmitted without merge cells between mistiming or phase differential to calculate the specified time delay of merge cells.The method needs to utilize fault wave recording device, and wiring is complicated, and fault wave recording device sample-synchronous and punctual precision directly will affect test result.
Utility model content
For solving the problem, the utility model provides the specified time delay detector of a kind of Intelligent substation merging unit, this detector can receive analog quantity and digital quantity simultaneously and have record wave energy, and the first cycle that energy accurate recording merge cells exports, thus accurately measure the specified time delay of merge cells, comprise the merge cells that specified time delay is equal to or greater than 20ms.
For achieving the above object, the utility model adopts following technical scheme:
The specified time delay detector of a kind of Intelligent substation merging unit, comprising:
Analogue collection module, it adopts independently high-speed dsp sampling, for gathering the analog quantity that conventional relay-protection tester exports and the accurate time of reception marking collection analog quantity, and transfers to CPU processing module; And
Digital data acquisition module, it adopts independently FPGA sampling, and for gathering the digital quantity that merge cells exports, and mark gathers the accurate time of reception of digital quantity, and transfers to CPU processing module; And
CPU processing module, for recording ripple, storage and analytical sampling data, and converts sampled data to displayable waveform; And
Load module, it is connected with CPU processing module, starts record ripple for inputting and stops the order of record ripple; And
Gps clock module, for providing absolute time for analogue collection module, digital data acquisition module and CPU processing module.
The beneficial effects of the utility model are:
(1) analogue collection module in the utility model and digital data acquisition module adopt independently plug-in unit, data-handling capacity is strong, and can effectively avoid producing interference between analog quantity and digital quantity, during by same clock signal pair, improve sampling accuracy, and add the versatility of device, make maintain and replace convenient;
(2) detector of the present utility model utilizes conventional relay-protection tester output analog quantity to test, and input merge cells analog quantity is same amount with the datum quantity for contrasting, and eliminates the influence factor of power source; Itself is without power source, and compact conformation, volume be little, lightweight, it is convenient to carry transportation safety, is simple and easy to use, practical;
(3) after the utility model adopts analog quantity and digital quantity sampling record ripple, waveform control methods calculates specified time delay, and first start record ripple when testing and starting, first cycle can be ensured to record, and test result is accurate and visual.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model;
Fig. 2 is the specified time delay schematic diagram of test merge cells of the present utility model.
Embodiment
Be further described the utility model below in conjunction with accompanying drawing, following examples only for clearly the technical solution of the utility model being described, and can not limit protection domain of the present utility model with this.
As shown in Figure 1, the specified time delay detector of a kind of Intelligent substation merging unit, comprising:
CPU processing module, for recording ripple, storage and analytical sampling data, and converts sampled data to displayable waveform; Analogue collection module, for gathering the analog quantity that conventional relay-protection tester exports, adopt independently high-speed dsp sampling, synchronous and store sample multi-analog data, the analog quantity of collection is marked upper accurate time of reception and carries out exchanges data with CPU processing module;
Digital data acquisition module, for gathering the digital quantity that merge cells exports, adopt independently FPGA sampling, described digital data acquisition module supports the reception of IEC61850-9-2 and FT3 format digital amount, the digital quantity of collection is marked upper accurate time of reception and carries out exchanges data with CPU processing module; Load module, it is connected with CPU processing module, starts record ripple for inputting and stops the order of record ripple;
The display module be connected with described CPU processing module, for showing the waveform of digital quantity and the analog quantity collected; Gps clock module, for providing absolute time for analogue collection module, digital data acquisition module and CPU processing module, ensure analog quantity and the sampling of digital quantity absolute synchronization, sampled data has absolute time mark.
Wherein, described analogue collection module adopts 32 high-speed floating point digital signal processors of American TI Company;
Described digital data acquisition module adopts the FPGA of Xilinx company;
Described gps clock module adopts Shijiazhuang to thunder the thunderous digital clock of Electronic Science and Technology Co., Ltd.'s research and development, this clock does not need master clock, do not need to erect a television antenna yet, but receive UNICOM CDMA time reference signal at secondary clock internal circuit, be traceable to the UTC time, namely CDMA digital clock all can be used to show the standard time in any place of UNICOM CDMA mobile phone that can use;
Described CPU processing module adopts 32 embedded CPU based on VxWorks embedded OS, can easily realize recording, store and draw the analog quantity and digital quantity waveform that gather.
The principle of work of the specified time delay detector of merge cells of the present utility model, as shown in Figure 2:
The first step: the identical analog quantity of two-way that conventional relay-protection tester is exported, tested merge cells is accessed on one road, the analogue collection module interface of the specified time delay detector of another road access merge cells, and the digital data acquisition module interface of the specified time delay detector of digital quantity access merge cells that merge cells is exported;
Second step: during test, the order of startup record ripple is sent to CPU processing module by load module, each sampled value collected all is marked an accurate absolute time tag by the analogue collection module of now merge cells specified time delay detector, equally, the digital quantity that each merge cells received exports also is stamped an accurate absolute time tag by digital data acquisition module;
3rd step: according to the absolute time tag of analog quantity and digital quantity, CPU processing module by these two groups of amount unifications to a transverse axis be absolute time coordinate axis on and be sent to display unit, and to show with wave form; Because the analog quantity being directly linked into the specified time delay detector of merge cells does not have time delay, and the digital quantity being linked into the specified time delay detector of merge cells after merge cells has time delay, this time delay is the specified time delay of merge cells, and namely first some mistiming on the horizontal scale of contrast two waveforms draws the specified time delay of tested merge cells;
When detection is complete, send the order of stopping record ripple by load module to CPU processing module.
By reference to the accompanying drawings embodiment of the present utility model is described although above-mentioned; but the restriction not to the utility model protection domain; one of ordinary skill in the art should be understood that; on the basis of the technical solution of the utility model, those skilled in the art do not need to pay various amendment or distortion that creative work can make still within protection domain of the present utility model.
Claims (2)
1. the specified time delay detector of Intelligent substation merging unit, is characterized in that, comprising:
CPU processing module, for recording ripple, storage and analytical sampling data, and converts sampled data to displayable waveform; And
Analogue collection module, it adopts independently high-speed dsp sampling, for gathering the analog quantity that conventional relay-protection tester exports and the accurate time of reception marking collection analog quantity, and transfers to CPU processing module; And
Digital data acquisition module, it adopts independently FPGA sampling, and for gathering the digital quantity that merge cells exports, and mark gathers the accurate time of reception of digital quantity, and transfers to CPU processing module; And
Gps clock module, for providing absolute time for analogue collection module, digital data acquisition module and CPU processing module.
2. the specified time delay detector of a kind of Intelligent substation merging unit as claimed in claim 1, it is characterized in that, CPU processing module is also connected with load module, and described load module starts record ripple for transmitting and stops the order of record ripple to CPU processing module.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420744809.0U CN204287461U (en) | 2014-12-01 | 2014-12-01 | The specified time delay detector of Intelligent substation merging unit |
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| CN201420744809.0U CN204287461U (en) | 2014-12-01 | 2014-12-01 | The specified time delay detector of Intelligent substation merging unit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106405293A (en) * | 2016-10-10 | 2017-02-15 | 许继集团有限公司 | System and method for testing secondary circuit on site in intelligent substation |
| CN106546854A (en) * | 2016-10-27 | 2017-03-29 | 许继电气股份有限公司 | A kind of combining unit for supporting to record wave energy |
| CN106841858A (en) * | 2017-01-03 | 2017-06-13 | 国家电网公司 | combining unit test device |
| CN107797052A (en) * | 2016-08-31 | 2018-03-13 | 南京南瑞继保电气有限公司 | String supplementary set Chinese style acquisition system protection act delay measurement system and method |
| CN109406866A (en) * | 2018-11-27 | 2019-03-01 | 北京锐创新智科技有限公司 | Signal validation apparatus and method |
-
2014
- 2014-12-01 CN CN201420744809.0U patent/CN204287461U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107797052A (en) * | 2016-08-31 | 2018-03-13 | 南京南瑞继保电气有限公司 | String supplementary set Chinese style acquisition system protection act delay measurement system and method |
| CN106405293A (en) * | 2016-10-10 | 2017-02-15 | 许继集团有限公司 | System and method for testing secondary circuit on site in intelligent substation |
| CN106546854A (en) * | 2016-10-27 | 2017-03-29 | 许继电气股份有限公司 | A kind of combining unit for supporting to record wave energy |
| CN106841858A (en) * | 2017-01-03 | 2017-06-13 | 国家电网公司 | combining unit test device |
| CN109406866A (en) * | 2018-11-27 | 2019-03-01 | 北京锐创新智科技有限公司 | Signal validation apparatus and method |
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Granted publication date: 20150422 Termination date: 20181201 |
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| CF01 | Termination of patent right due to non-payment of annual fee |