CN204272094U - The I/Q electrical mismatch detection circuit of low intermediate frequency receiver - Google Patents

Abstract

The utility model discloses a kind of I/Q electrical mismatch detection circuit of low intermediate frequency receiver, for detect Q channel signal relative to I channel signal or I channel signal relative to the amplitude mismatch of Q channel signal and phase mismatch, first signal is from I passage, and secondary signal is from Q passage.The I/Q electrical mismatch detection circuit of low intermediate frequency receiver of the present utility model comprises two accumulators, a multiply-accumulator, two squared accumulator, two squarers, a square root extractor, two dividers, two multipliers, three subtracters and three left shifter, these arithmetic units, by detection calculations formula forming circuit, obtain amplitude mismatch and phase mismatch according to the first signal and secondary signal.The utility model forms functional circuit by some arithmetic units by detection calculations formula, can obtain amplitude mismatch and phase mismatch fast, accurately, is beneficial to follow-up I/Q mismatch compensation operation.

Description

The I/Q electrical mismatch detection circuit of low intermediate frequency receiver

Technical field

The utility model relates to a kind of testing circuit, particularly relates to a kind of I/Q electrical mismatch detection circuit of low intermediate frequency receiver.

Background technology

In recent years, based on the use of quadrature down-conversion architecture, low intermediate frequency receiver is widely used, low intermediate frequency receiver has the advantage of superheterodyne receiver and zero intermediate frequency reciver, namely DC maladjustment interference is little, 1/f noise interference effect is little, but there is the problem of image signal interference in low intermediate frequency receiver.The signal received through antenna becomes inphase quadrature two paths of signals after frequency mixer quadrature frequency conversion, but because local oscillator accurately can not produce the signal of phase quadrature, the structure of the amplifier of mixing rear class and complex filter itself is asymmetric can cause I/Q two-way amplitude and phase mismatch equally, therefore, need to introduce I/Q mismatch compensation circuit in circuit.

A kind of compensation scheme adopts analogy method to eliminate, and before I/Q mismatch compensation circuit is placed in complex filter, utilizes ADC sampled signal to estimate I/Q mismatch value or directly in analog domain estimation mismatch value, utilize analog circuit to realize compensating.Although this kind of mode circuit structure is simple, but due to resistance and current source restriction, comparatively accurate offset can not be produced, along with the mismatch scope needing to compensate increases, circuit scale also inevitably increases, and for different technique, circuit parameter all needs to redesign, and adds design cycle and design cost.

The Chinese patent application " quadrature frequency conversion receiver I, Q channel signal mismatch calibration device " (application number 201110076268.X) of prior art adopts adjustable resistance and bias current sources to realize calibrating amplitude and phase mismatch at analog domain, its accessible amplitude calibration scope is ± 1.6dB, and calibration accuracy is 0.2dB; Phase alignment scope is ± 5 °, and calibration accuracy is 0.5 °.Though this calibrating installation has better simply circuit structure (see Fig. 1, each element in figure and symbol thereof can consult this patent application), but only there is calibration function, detection of mismatch function needs other circuit to realize, and calibration accuracy is poor, amplitude and phase mismatch less time can not correctly calibrate.

The Chinese patent application " a kind of orthogonal i/q signal phase imbalance correcting circuit " (application number 201210338612.2) of prior art utilizes the orthogonal property of i/q signal, Matrix coupling circuit is adopted to carry out phase imbalance correction, coupling coefficient determines correction amplitude size, phasing scope ± 7 ° can be reached, with the correction accuracy (this patent application can be consulted see each element in Fig. 2, figure and symbol thereof) of 0.04 °.This utility model correction accuracy is high, and integrated level is high, but can not correct amplitude mismatch, and along with the phase mismatch scope needing to correct increases, the scale of circuit also can increase.

The scheme of wide model application eliminates at numeric field, ADC and DSP is utilized to adopt multiple Baseband processing algorithm numeric field to eliminate, this kind of design can eliminate the asymmetric mismatch caused due to complex filter and amplifier simultaneously, but because higher image rejection ratio needs high-precision adc and high-speed dsp, this kind of design is for cost with cost and power consumption.

In I/Q mismatch compensation circuit, detection of mismatch function is most critical.Therefore, those skilled in the art is devoted to the I/Q electrical mismatch detection circuit developing a kind of low intermediate frequency receiver.

Utility model content

Because the above-mentioned defect of prior art, technical problem to be solved in the utility model is to provide a kind of I/Q electrical mismatch detection circuit of low intermediate frequency receiver, detects I/Q mismatch.

Suppose the signal I of ideally I/Q two passage after quadrature frequency conversion _iedaland Q _iedalbe respectively: I _iedal=cos (ω _ct), Q _iedal=sin (ω _ct).Due to the undesirable factor of the devices such as local oscillator self, suppose that the relative I passage of Q passage has amplitude mismatch α, phase mismatch β, then actual I/Q two channel signal I _realand Q _realbe respectively: I _real=cos (ω _ct), Q _real=α sin (ω _ct-β).Relation between two groups of signals is expressed as in the matrix form:

$\left[\begin{array}{c}{I}_{\mathrm{real}}\\ Q_{\mathrm{real}}\end{array}\right]=\left[\begin{array}{cc}1& 0\\ 0& \mathrm{\α}\end{array}\right]\left[\begin{array}{cc}1& 0\\ \sin (-\mathrm{\β})& \cos \left(\mathrm{\β}\right)\end{array}\right]\left[\begin{array}{c}{I}_{\mathrm{ideal}}\\ Q_{\mathrm{ideal}}\end{array}\right]$

When β ∈ [-10 °, 10 °], have sin (-β) ≈-β, cos (β) ≈ 1, therefore above formula can be reduced to:

$\left[\begin{array}{c}{I}_{\mathrm{real}}\\ Q_{\mathrm{real}}\end{array}\right]=\left[\begin{array}{cc}1& 0\\ 0& \mathrm{\α}\end{array}\right]\left[\begin{array}{cc}1& 0\\ -\mathrm{\β}& 1\end{array}\right]\left[\begin{array}{c}{I}_{\mathrm{ideal}}\\ Q_{\mathrm{ideal}}\end{array}\right]$

Obtain after above formula inverse transformation:

$\left[\begin{array}{c}{I}_{\mathrm{ideal}}\\ Q_{\mathrm{ideal}}\end{array}\right]=\left[\begin{array}{cc}1& 0\\ \sin \left(\mathrm{\β}\right)& 1\end{array}\right]\left[\begin{array}{cc}1& 0\\ 0& {\mathrm{\α}}^{,-1}\end{array}\right]\left[\begin{array}{c}{I}_{\mathrm{real}}\\ Q_{\mathrm{real}}\end{array}\right]---\left(1\right)$

I/Q detection of mismatch estimates the value of amplitude mismatch α in formula (1) and phase mismatch β exactly.

For achieving the above object, the utility model provides a kind of I/Q electrical mismatch detection circuit of low intermediate frequency receiver, for detecting Q passage relative to the amplitude mismatch of I passage and phase mismatch, first signal is from described I passage, secondary signal is from described Q passage, it is characterized in that, be made up of by detection calculations formula some arithmetic units; Described detection calculations formula is:

$\mathrm{Di}=\underset{n}{\overset{N}{\mathrm{\Σ}}}i\left(n\right)$

$\mathrm{Dq}=\underset{n}{\overset{N}{\mathrm{\Σ}}}q\left(n\right)$

$\mathrm{Xi}=\underset{n}{\overset{N}{\mathrm{\Σ}}}i{\left(n\right)}^2$

$\mathrm{Xq}=\underset{n}{\overset{N}{\mathrm{\Σ}}}q{\left(n\right)}^2;$

$\mathrm{Diq}=\underset{n}{\overset{N}{\mathrm{\Σ}}}i\left(n\right)\×q\left(n\right)$

$\mathrm{GAIN}\_\mathrm{MIS}={\mathrm{\α}}^{-1}=\sqrt{\frac{N\×\mathrm{Xi}-{\mathrm{Di}}^2}{N\×\mathrm{Xq}-{\mathrm{Dq}}^2}}$

$\mathrm{PHASE}\_\mathrm{MIS}=\sin (-\mathrm{\β})=\frac{N\×\mathrm{Diq}-\mathrm{Di}\×\mathrm{Dq}}{(N\×\mathrm{Xq}-{\mathrm{Dq}}^2)\×\mathrm{GAIN}\_\mathrm{MIS}}$

Wherein, 1≤n≤N; Described arithmetic unit accepts the sampled value i (n) of N number of described first signal and the sampled value q (n) of N number of described secondary signal, exports and is relevant to the signal GAIN_MIS of described amplitude mismatch and is relevant to the signal PHASE_MIS of described phase mismatch.

Further, described arithmetic unit comprises some accumulators, some squared accumulator, some squarers, some dividers, some multipliers, some subtracters, some shift units and square root extractor.

Further, described arithmetic unit comprises the first accumulator, the second accumulator, the first squared accumulator, the second squared accumulator, multiply-accumulator, the first squarer, the second squarer, square root extractor, the first divider, the second divider, the first multiplier, the second multiplier, the first subtracter, the second subtracter, the 3rd subtracter, the first left shifter, the second left shifter and the 3rd left shifter;

The input of described first accumulator accepts the sampled value i (n) of N number of described first signal, and its output is connected with an input of described first multiplier with the input of described first squarer;

The input of described first squared accumulator accepts the sampled value i (n) of N number of described first signal, and its output is connected with the input of described first left shifter;

The input of described second accumulator accepts the sampled value q (n) of N number of described secondary signal, and its output is connected with another input of described first multiplier with the input of described second squarer;

The input of described second squared accumulator accepts the sampled value q (n) of N number of described secondary signal, and its output is connected with the input of described second left shifter;

The input of described multiply-accumulator accepts the sampled value i (n) of N number of described first signal and the sampled value q (n) of N number of described secondary signal, and its output is connected with the input of described 3rd left shifter;

The output of described first squarer is connected with an input of described first subtracter, the output of described first left shifter is connected with another input of described first subtracter, and the output of described first subtracter is connected with an input of described first divider;

The output of described second squarer is connected with an input of described second subtracter, the output of described second left shifter is connected with another input of described second subtracter, the output of described second subtracter is connected with another input of described first divider, and the output of described second subtracter is also connected with an input of described second multiplier;

The output of described first divider is connected with the input of described square root extractor, and the output of described square root extractor is connected with another input of described second multiplier, and the output of described square root extractor exports described signal GAIN_MIS;

The output of described first multiplier is connected with an input of described 3rd subtracter, the output of described 3rd left shifter is connected with another input of described 3rd subtracter, and the output of described 3rd subtracter is connected with an input of described second divider;

The output of described second multiplier is connected with another input of described second divider, and the output of described second divider exports described signal PHASE_MIS.

The utility model additionally provides a kind of I/Q electrical mismatch detection circuit of low intermediate frequency receiver, for detecting I passage relative to the amplitude mismatch of Q passage and phase mismatch, first signal is from described I passage, secondary signal is from described Q passage, it is characterized in that, be made up of by detection calculations formula some arithmetic units; Described detection calculations formula is:

$\mathrm{Dq}=\underset{n}{\overset{N}{\mathrm{\Σ}}}q\left(n\right)$

$\mathrm{Di}=\underset{n}{\overset{N}{\mathrm{\Σ}}}i\left(n\right)$

$\mathrm{Xq}=\underset{n}{\overset{N}{\mathrm{\Σ}}}q{\left(n\right)}^2$

$\mathrm{Xi}=\underset{n}{\overset{N}{\mathrm{\Σ}}}i{\left(n\right)}^2;$

$\mathrm{Diq}=\underset{n}{\overset{N}{\mathrm{\Σ}}}i\left(n\right)\×q\left(n\right)$

$\mathrm{GAIN}\_\mathrm{MIS}={\mathrm{\α}}^{-1}=\sqrt{\frac{N\×\mathrm{Xq}-{\mathrm{Dq}}^2}{N\×\mathrm{Xi}-{\mathrm{Di}}^2}}$

$\mathrm{PHASE}\_\mathrm{MIS}=\sin (-\mathrm{\β})=\frac{N\×\mathrm{Diq}-\mathrm{Di}\×\mathrm{Dq}}{(N\×\mathrm{Xi}-{\mathrm{Di}}^2)\×\mathrm{GAIN}\_\mathrm{MIS}}$

Wherein, 1≤n≤N; Described arithmetic unit accepts the sampled value i (n) of N number of described first signal and the sampled value q (n) of N number of described secondary signal, exports and is relevant to the signal GAIN_MIS of described amplitude mismatch and is relevant to the signal PHASE_MIS of described phase mismatch.

As can be seen here, the I/Q electrical mismatch detection circuit of low intermediate frequency receiver of the present utility model forms functional circuit by some arithmetic units by detection calculations formula, can obtain amplitude mismatch and phase mismatch fast, accurately, is beneficial to follow-up I/Q mismatch compensation operation.

Be described further below with reference to the technique effect of accompanying drawing to design of the present utility model, concrete structure and generation, to understand the purpose of this utility model, characteristic sum effect fully.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of a kind of quadrature frequency conversion receiver I/Q channel signal mismatch calibration device of prior art.

Fig. 2 is the circuit diagram of a kind of I/Q mismatch phase correcting circuit of prior art.

Fig. 3 is in a preferred embodiment, the circuit diagram of low intermediate frequency receiver I/Q electrical mismatch detection circuit of the present utility model.

Embodiment

The electrical mismatch detection circuit adopted in this enforcement has some arithmetic units to form, and its function expresses based on the following arithmetic to formula (1):

$\mathrm{Di}=\frac{1}{N}\mathrm{\Σi}\left(n\right)$

$\mathrm{Dq}=\frac{1}{N}\mathrm{\Σq}\left(n\right)$

$\mathrm{Xi}=\frac{1}{N}\mathrm{\Σi}{\left(n\right)}^2$

$\mathrm{Xq}=\frac{1}{N}\mathrm{\Σq}{\left(n\right)}^2$

$\mathrm{Diq}=\frac{1}{N}\mathrm{\Σi}\left(n\right)\×q\left(n\right)$ $\mathrm{GAIN}\_\mathrm{MIS}={\mathrm{\α}}^{-1}=\sqrt{\frac{\mathrm{Xi}-{\mathrm{Di}}^2}{\mathrm{Xq}-{\mathrm{Dq}}^2}}$

$\mathrm{PHASE}\_\mathrm{MIS}=\sin (-\mathrm{\β})=\frac{\mathrm{Diq}-\mathrm{Di}\×\mathrm{Dq}}{\sqrt{(\mathrm{Xi}-{\mathrm{Di}}^2)(\mathrm{Xq}-{\mathrm{Dq}}^2)}}$

Further, for reducing loss of significance as much as possible, following distortion has been carried out to above formula:

$\mathrm{Di}=\underset{n}{\overset{N}{\mathrm{\Σ}}}i\left(n\right)$

$\mathrm{Dq}=\underset{n}{\overset{N}{\mathrm{\Σ}}}q\left(n\right)$

$\mathrm{Xi}=\underset{n}{\overset{N}{\mathrm{\Σ}}}i{\left(n\right)}^2$

$\mathrm{Xq}=\underset{n}{\overset{N}{\mathrm{\Σ}}}q{\left(n\right)}^2$

$\mathrm{Diq}=\underset{n}{\overset{N}{\mathrm{\Σ}}}i\left(n\right)\×q\left(n\right)$

$\mathrm{GAIN}\_\mathrm{MIS}={\mathrm{\α}}^{-1}=\sqrt{\frac{N\×\mathrm{Xi}-{\mathrm{Di}}^2}{N\×\mathrm{Xq}-{\mathrm{Dq}}^2}}$

$\mathrm{PHASE}\_\mathrm{MIS}=\sin (-\mathrm{\β})=\frac{N\×\mathrm{Diq}-\mathrm{Di}\×\mathrm{Dq}}{(N\×\mathrm{Xq}-{\mathrm{Dq}}^2)\×\mathrm{GAIN}\_\mathrm{MIS}}$

In above formula, i (n) represents the n-th sampled point of I channel signal, and q (n) represents Q channel signal n-th sampled point, and N is total sampling number.GAIN_MIS is relevant to amplitude mismatch α for output signal, and signal PHASE_MIS is relevant to phase mismatch β.

As shown in Figure 3, in a preferred embodiment, low intermediate frequency receiver I/Q electrical mismatch detection circuit of the present utility model comprises the first accumulator 110, second accumulator 210, first squared accumulator 121, second squared accumulator 221, multiply-accumulator 310, first squarer 120, second squarer 220, square root extractor 160, first divider 150, second divider 250, first multiplier 130, second multiplier 230, first subtracter 140, second subtracter 240, 3rd subtracter 340, first left shifter 131, second left shifter 231 and the 3rd left shifter 331.Wherein:

The input of the first accumulator 110 accepts the sampled value i (n) of N number of first signal, and its output is connected with an input of the first multiplier 130 with the input of the first squarer 120;

The input of the first squared accumulator 121 accepts the sampled value i (n) of N number of first signal, and its output is connected with the input of the first left shifter 131;

The input of the second accumulator 210 accepts the sampled value q (n) of N number of secondary signal, and its output is connected with another input of the first multiplier 130 with the input of the second squarer 220;

The input of the second squared accumulator 221 accepts the sampled value q (n) of N number of secondary signal, and its output is connected with the input of the second left shifter 231;

The input of multiply-accumulator 310 accepts the sampled value q (n) of N number of secondary signal and the sampled value q (n) of N number of secondary signal, and its output is connected with the input of the 3rd left shifter 331;

The output of the first squarer 120 is connected with an input of the first subtracter 140, the output of the first left shifter 131 is connected with another input of the first subtracter 140, and the output of the first subtracter 140 is connected with an input of the first divider 150;

The output of the second squarer 220 is connected with an input of the second subtracter 240, the output of the second left shifter 231 is connected with another input of the second subtracter 240, the output of the second subtracter 240 is connected with another input of the first divider 150, and the output of the second subtracter 240 is also connected with an input of the second multiplier 230;

The output of the first divider 150 is connected with the input of square root extractor 160, and the output of square root extractor 160 is connected with another input of the second multiplier 230, and the output of square root extractor 160 output signal GAIN_MIS;

The output of the first multiplier 130 is connected with an input of the 3rd subtracter 340, the output of the 3rd left shifter 331 is connected with another input of the 3rd subtracter 340, and the output of the 3rd subtracter 340 is connected with an input of the second divider 250;

The output of the second multiplier 230 is connected with another input of the second divider 250, the output output signal PHASE_MIS of the second divider 250.

Wherein, i (n) is admitted to the first accumulator 110 to obtain Di, and is admitted to the first squared accumulator 121 to obtain Xi; Q (n) is admitted to the second accumulator 210 to obtain Dq, and is admitted to the second squared accumulator 221 to obtain Xq; I (n) and q (n) is all admitted to the 3rd accumulator 310 to obtain Diq.Suppose amplitude mismatch value α ^-1∈ [0.875,1.15], then square root extractor 160 can be obtained by the Two-order approximation of Taylor expansion, namely x ∈ [-0.25,0.3225].Each left shifter carries out shift left operation to accumulated value, and the number of displacement is relevant with cumulative sampling number, and when per update cycle accumulated samples is counted as N, then the figure place that moves to left is log ₂(N), general selection N is the power series of 2.

More than describe preferred embodiment of the present utility model in detail.Should be appreciated that those of ordinary skill in the art just can make many modifications and variations according to design of the present utility model without the need to creative work.Therefore, all those skilled in the art according to design of the present utility model on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment, all should by the determined protection range of claims.

Claims (1)

1. the I/Q electrical mismatch detection circuit of a low intermediate frequency receiver, for detecting Q channel signal relative to the signal amplitude mismatch α of I passage and phase mismatch β, the first signal is from described I passage, and secondary signal is from described Q passage, it is characterized in that, be made up of some arithmetic units;

Described arithmetic unit accepts the sampled value i (n) of N number of described first signal and the sampled value q (n) of N number of described secondary signal, exports and is relevant to the signal GAIN_MIS of described amplitude mismatch α and is relevant to the signal PHASE_MIS of described phase mismatch β; GAIN_MIS=α ^-1, PHASE_MIS=sin (-β);

Described arithmetic unit comprises the first accumulator, the second accumulator, the first squared accumulator, the second squared accumulator, multiply-accumulator, the first squarer, the second squarer, square root extractor, the first divider, the second divider, the first multiplier, the second multiplier, the first subtracter, the second subtracter, the 3rd subtracter, the first left shifter, the second left shifter and the 3rd left shifter;

The input of described first accumulator accepts the sampled value i (n) of N number of described first signal, and its output is connected with an input of described first multiplier with the input of described first squarer;

The input of described first squared accumulator accepts the sampled value i (n) of N number of described first signal, and its output is connected with the input of described first left shifter;

The input of described second accumulator accepts the sampled value q (n) of N number of described secondary signal, and its output is connected with another input of described first multiplier with the input of described second squarer;

The input of described second squared accumulator accepts the sampled value q (n) of N number of described secondary signal, and its output is connected with the input of described second left shifter;

The input of described multiply-accumulator accepts the sampled value i (n) of N number of described first signal and the sampled value q (n) of N number of described secondary signal, and its output is connected with the input of described 3rd left shifter;

The output of described first squarer is connected with an input of described first subtracter, the output of described first left shifter is connected with another input of described first subtracter, and the output of described first subtracter is connected with an input of described first divider;

The output of described second squarer is connected with an input of described second subtracter, the output of described second left shifter is connected with another input of described second subtracter, the output of described second subtracter is connected with another input of described first divider, and the output of described second subtracter is also connected with an input of described second multiplier;

The output of described first divider is connected with the input of described square root extractor, and the output of described square root extractor is connected with another input of described second multiplier, and the output of described square root extractor exports described signal GAIN_MIS;

The output of described first multiplier is connected with an input of described 3rd subtracter, the output of described 3rd left shifter is connected with another input of described 3rd subtracter, and the output of described 3rd subtracter is connected with an input of described second divider;

The output of described second multiplier is connected with another input of described second divider, and the output of described second divider exports described signal PHASE_MIS.