CN204258784U - A kind of broadband buffer circuits - Google Patents
A kind of broadband buffer circuits Download PDFInfo
- Publication number
- CN204258784U CN204258784U CN201420720157.7U CN201420720157U CN204258784U CN 204258784 U CN204258784 U CN 204258784U CN 201420720157 U CN201420720157 U CN 201420720157U CN 204258784 U CN204258784 U CN 204258784U
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- China
- Prior art keywords
- triode
- resistance
- diode
- electric capacity
- voltage stabilizing
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Abstract
The utility model discloses a kind of broadband buffer circuits, comprise the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the first voltage stabilizing didoe, the second voltage stabilizing didoe, the first electric capacity, the second electric capacity, the 3rd electric capacity, the first diode, the second diode, the 3rd diode, the first triode, the second triode, the 3rd triode, the 4th triode.The utility model can effectively apply in high-speed sampling holding circuit, do not need phase compensation, the high frequency characteristics of signal is not repelled, and have that input impedance is high, the advantage of the fast and stable work in work of switching rate, meanwhile, circuit structure of the present utility model is simple, and components and parts used are few, reduce cost of manufacture, be conducive to promoting and using.
Description
Technical field
The utility model relates to a kind of high-speed sampling holding circuit, particularly relates to a kind of broadband buffer circuits.
Background technology
Along with wireless communication technology, making constant progress of the network communications technology, system is more and more higher for the requirement of receiving circuit, affect inbound pacing, an Important Circuit unit A/D conversion portion of performance just seems more and more important, and the sampling hold circuit of A/D conversion front end is directly connected to speed and the accuracy of A/D conversion, simultaneously, along with the development of broadband technology, Received signal strength band wide, change is fast, have higher requirement to the design of sampling system, require sampling hold circuit at a high speed, accomplish fast as far as possible to collect signal, its middle width strip buffer circuits is the emphasis in high-speed sampling holding circuit, the design of prior art middle width strip buffer adopts operational amplifier mostly, operational amplifier is adopted to need to carry out phase compensation, be unfavorable for that the sampling of high-frequency signal keeps, and add the stabilization time of signal.
Utility model content
The purpose of this utility model is just to provide a kind of broadband buffer circuits to solve the problem.
The utility model is achieved through the following technical solutions above-mentioned purpose:
The utility model comprises the first resistance, second resistance, 3rd resistance, 4th resistance, 5th resistance, first voltage stabilizing didoe, second voltage stabilizing didoe, first electric capacity, second electric capacity, 3rd electric capacity, first diode, second diode, 3rd diode, first triode, second triode, 3rd triode, 4th triode, the negative pole of described first voltage stabilizing didoe is positive source input, the positive pole of described first voltage stabilizing didoe simultaneously with the first end of described first electric capacity, the collector electrode of described first triode is connected with the collector electrode of described 3rd triode, second end ground connection of described first electric capacity, the emitter of described first triode is connected with the first end of described first resistance, the base stage of described first triode is connected with the emitter of described 3rd triode and the positive pole of described first diode simultaneously, the base stage of described 3rd triode is the signal input part of described broadband buffer circuits, second end of described first resistance is connected with the first end of described second resistance and the signal output part of described broadband buffer circuits simultaneously, second end of the resistance of described second is connected with the emitter of described second triode, the base stage of described second triode is connected with the collector electrode of described 4th triode and the first end of described 3rd resistance simultaneously, second end of described 3rd resistance is connected with the negative pole of described second diode, the positive pole of described second diode is connected with the negative pole of described first diode, the collector electrode of described second triode is connected with the first end of described second electric capacity and the negative pole of described second voltage stabilizing didoe simultaneously, second end ground connection of described second electric capacity, the positive pole of described second voltage stabilizing didoe simultaneously with described power cathode input, the first end of described 4th resistance is connected with the negative pole of described 3rd diode, second end of described 4th resistance is connected with the emitter of described 4th triode, the base stage of described 4th triode simultaneously with the positive pole of described 3rd diode, the first end of described 3rd electric capacity is connected with the first end of described 5th resistance, second end ground connection of described 3rd electric capacity, second end ground connection of described 5th resistance.
The beneficial effects of the utility model are:
The utility model can effectively apply in high-speed sampling holding circuit, do not need phase compensation, the high frequency characteristics of signal is not repelled, and have that input impedance is high, the advantage of the fast and stable work in work of switching rate, meanwhile, circuit structure of the present utility model is simple, and components and parts used are few, reduce cost of manufacture, be conducive to promoting and using.
Accompanying drawing explanation
Fig. 1 is circuit structure schematic diagram of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in further detail:
As shown in Figure 1: the utility model comprises the first resistance R1, second resistance R2, 3rd resistance R3, 4th resistance R4, 5th resistance R5, first voltage stabilizing didoe ZD1, second voltage stabilizing didoe ZD2, first electric capacity C1, second electric capacity C2, 3rd electric capacity C3, first diode D1, second diode D2, 3rd diode D3, first triode VT1, second triode VT2, 3rd triode VT3, 4th triode VT4, the negative pole of the first voltage stabilizing didoe ZD1 is positive source input+V, the positive pole of the first voltage stabilizing didoe ZD1 simultaneously with the first end of the first electric capacity C1, the collector electrode of the first triode VT1 is connected with the collector electrode of the 3rd triode VT3, the second end ground connection of the first electric capacity C1, the emitter of the first triode VT1 is connected with the first end of the first resistance R1, the base stage of the first triode VT1 is connected with the emitter of the 3rd triode VT3 and the positive pole of the first diode D1 simultaneously, the base stage of the 3rd triode VT3 is the signal input part IN of broadband buffer circuits, second end of the first resistance R1 is connected with the first end of the second resistance R2 and the signal output part OT of broadband buffer circuits simultaneously, second end of the resistance R2 of second is connected with the emitter of the second triode VT2, the base stage of the second triode VT2 is connected with the collector electrode of the 4th triode VT4 and the first end of the 3rd resistance R3 simultaneously, second end of the 3rd resistance R3 is connected with the negative pole of the second diode D2, the positive pole of the second diode D2 is connected with the negative pole of the first diode D1, the collector electrode of the second triode VT2 is connected with the first end of the second electric capacity C2 and the negative pole of the second voltage stabilizing didoe ZD2 simultaneously, the second end ground connection of the second electric capacity C2, the positive pole of the second voltage stabilizing didoe ZD2 simultaneously with power cathode input-V, the first end of the 4th resistance R4 is connected with the negative pole of the 3rd diode D3, second end of the 4th resistance R4 is connected with the emitter of the 4th triode VT4, the base stage of the 4th triode VT4 simultaneously with the positive pole of the 3rd diode D3, the first end of the 3rd electric capacity C3 is connected with the first end of the 5th resistance R5, the second end ground connection of the 3rd electric capacity C3, the second end ground connection of the 5th resistance R5.In the utility model, the first diode D1 and the second diode D2 is bias diode in circuit and plays the effect of temperature-compensating, wherein the first triode VT1 and the second triode VT2 forms complementary circuit, make spuing of electric current identical with absorbability, the first voltage stabilizing didoe ZD1 and the second voltage stabilizing didoe ZD2 is used for stabilizing circuit voltage and reduces the power consumption of the first triode VT1 and the second triode VT2.
Claims (1)
1. a broadband buffer circuits, it is characterized in that: comprise the first resistance, second resistance, 3rd resistance, 4th resistance, 5th resistance, first voltage stabilizing didoe, second voltage stabilizing didoe, first electric capacity, second electric capacity, 3rd electric capacity, first diode, second diode, 3rd diode, first triode, second triode, 3rd triode, 4th triode, the negative pole of described first voltage stabilizing didoe is positive source input, the positive pole of described first voltage stabilizing didoe simultaneously with the first end of described first electric capacity, the collector electrode of described first triode is connected with the collector electrode of described 3rd triode, second end ground connection of described first electric capacity, the emitter of described first triode is connected with the first end of described first resistance, the base stage of described first triode is connected with the emitter of described 3rd triode and the positive pole of described first diode simultaneously, the base stage of described 3rd triode is the signal input part of described broadband buffer circuits, second end of described first resistance is connected with the first end of described second resistance and the signal output part of described broadband buffer circuits simultaneously, second end of the resistance of described second is connected with the emitter of described second triode, the base stage of described second triode is connected with the collector electrode of described 4th triode and the first end of described 3rd resistance simultaneously, second end of described 3rd resistance is connected with the negative pole of described second diode, the positive pole of described second diode is connected with the negative pole of described first diode, the collector electrode of described second triode is connected with the first end of described second electric capacity and the negative pole of described second voltage stabilizing didoe simultaneously, second end ground connection of described second electric capacity, the positive pole of described second voltage stabilizing didoe simultaneously with described power cathode input, the first end of described 4th resistance is connected with the negative pole of described 3rd diode, second end of described 4th resistance is connected with the emitter of described 4th triode, the base stage of described 4th triode simultaneously with the positive pole of described 3rd diode, the first end of described 3rd electric capacity is connected with the first end of described 5th resistance, second end ground connection of described 3rd electric capacity, second end ground connection of described 5th resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420720157.7U CN204258784U (en) | 2014-11-26 | 2014-11-26 | A kind of broadband buffer circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420720157.7U CN204258784U (en) | 2014-11-26 | 2014-11-26 | A kind of broadband buffer circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204258784U true CN204258784U (en) | 2015-04-08 |
Family
ID=52963047
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420720157.7U Expired - Fee Related CN204258784U (en) | 2014-11-26 | 2014-11-26 | A kind of broadband buffer circuits |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204258784U (en) |
-
2014
- 2014-11-26 CN CN201420720157.7U patent/CN204258784U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150408 Termination date: 20151126 |