CN204216776U - A kind of three-level inverter harmonic compensation device - Google Patents
A kind of three-level inverter harmonic compensation device Download PDFInfo
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- CN204216776U CN204216776U CN201420625963.6U CN201420625963U CN204216776U CN 204216776 U CN204216776 U CN 204216776U CN 201420625963 U CN201420625963 U CN 201420625963U CN 204216776 U CN204216776 U CN 204216776U
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Abstract
Three-level inverter harmonic compensation device of the present utility model, comprises main control module, neutral-point-clamped three-level topology module; Main control module comprises first processor, the second processor, the 3rd processor, programmable logic device, output current iS testing circuit, load current iL testing circuit, IGBT drive circuit, power converting circuit.Main control module Real-Time Monitoring bus capacitor voltage, output voltage, output current and load current, the data according to monitoring carry out active stepless compensation, compensate for system negative sequence component, improve three-phase imbalance, avoid the electric current superposition of Zero-pharse harmonic on center line.
Description
[technical field]
This patent relates to field of electrical equipment, is specifically related in power transmission and distribution technical field, the inverter harmonic compensation arrangement formed with the topological structure of neutral-point-clamped three level.
[background technology]
Power electronic technology brings convenience, and while efficient huge interests, its non-linear, impact and imbalance electrical characteristics, cause severe contamination also to the power supply quality of utility network, inject a large amount of harmonic waves and reactive power to utility network.On the other hand, along with the popularization and application of a large amount of sensitive equipments taking computer as representative, people require more and more higher to the power supply quality of utility network, propose stricter requirement to the power factor of the harmonic content in electrical network and power consumption equipment.
Power quality problem can produce many harm, such as cause equipment operation irregularity, produce waste product, computer resets, loss of data, energy efficiency of equipment reduces, the lost of life, overheated, burn, capacitor breakdown damages, power factor declines, place capacity declines, power consumption increases, and pays more electricity charge etc.
[summary of the invention]
In view of this, this patent provides a kind of three-level inverter harmonic compensation device.
This patent adopts following technical scheme, and structure three-level inverter harmonic compensation device, comprises main control module, neutral-point-clamped three-level topology module; Main control module comprises first processor, the second processor, the 3rd processor, programmable logic device, output current iS testing circuit, load current iL testing circuit, IGBT drive circuit, power converting circuit; Output current iS testing circuit is used for detecting the current i S being supplied to load, and this detected value is exported to first processor, the second processor, the 3rd processor, and its output connects the I/O pin of first processor, the second processor, the 3rd processor respectively; Load current iL testing circuit is used for detection and flows through load current iL, and this detected value is exported to first processor, the second processor, the 3rd processor, and its output connects the I/O pin of first processor, the second processor, the 3rd processor respectively; IGBT drive circuit is supplied to each IGBT grid PWM drive singal of neutral-point-clamped three-level topology module, and its output connects each IGBT grid in neutral-point-clamped three-level topology module, and its input connects programmable logic device; First processor respectively with the second processor, the 3rd processor is connected with programmable logic device; Programmable logic device, receives the control command of first processor and control command is exported to corresponding circuit, or the logic output order according to self gives corresponding circuit, and the transformation results of the 3rd processor is inputed to the second processor; Power-switching circuit, for the conversion by external power source, it exports the power input connecting other circuit of main control module.Neutral-point-clamped three-level topology module is by identical with harmonic amplitude in load current for the control output according to main control module, but the offset current that phase place is contrary.
Preferably, three-level inverter harmonic compensation device also comprises input and connects load current iL testing circuit, and output connects the load current over-current detection circuit of programmable logic device.
Preferably, three-level inverter harmonic compensation device also comprises the bus capacitor voltage detecting circuit that output connects first processor.
Preferably, three-level inverter harmonic compensation device also comprises input and is connected with bus capacitor voltage detecting circuit, the bus capacitor electric voltage over press testing circuit that output is connected with programmable logic device.
Preferably, three-level inverter harmonic compensation device also comprises the zero sequence voltage detection circuit that output is connected with first processor.
The Advantageous Effects of this patent is:
1. the neutral-point-clamped three-level inverter of high speed, has switching frequency high, the advantages such as voltage stress is little, thus substantially reduces device passive device and overall volume, improve the power density of equipment; Main control module Real-Time Monitoring bus capacitor voltage, output voltage, output current and load current, the data according to monitoring carry out active stepless compensation, compensate for system negative sequence component, improve three-phase imbalance, avoid the electric current superposition of Zero-pharse harmonic on center line.
2. this compensation arrangement adopts inverter compensation harmonic electric current and reactive power, does not need the energy-storage travelling wave tube of traditional capacitor and so on, only need low capacity inductance to meet the demands, decrease the supplementary load loss of the energy during compensation harmonic electric current during compensating power.
3. the impact by electric network impedance is little, can not with electric network impedance generation resonance.
4. this device volume is little, and can be combined into other capacity according to demand, Capacity Selection is simple, and equipment and system is in parallel; install fast and convenient, there is input voltage abnormal, overheated; accessory power supply fault, the defencive functions such as bus overvoltage, provide the reliability of plant running.
[accompanying drawing explanation]
Fig. 1 compensation work schematic diagram;
Three-level inverter harmonic compensation device circuit structure block diagram in Fig. 2 embodiment one;
Main control module circuit structure block diagram in Fig. 3 embodiment one;
Output current iS testing circuit figure in Fig. 4 embodiment one;
IGBT drive circuit figure in Fig. 5 embodiment one;
Load voltage VL testing circuit figure in Fig. 6 embodiment one;
Load current over-current detection circuit figure in Fig. 7 embodiment one;
Bus capacitor voltage detecting circuit figure in Fig. 8 embodiment one;
Bus capacitor electric voltage over press testing circuit figure in Fig. 9 embodiment one;
Working temperature testing circuit figure in Figure 10 embodiment one;
Fan drive circuit figure in Figure 11 embodiment one;
Fan failure detection circuit figure in Figure 12 embodiment one;
Zero sequence voltage detection circuit figure in Figure 13 embodiment one;
CAN communicating circuit figure in Figure 14 embodiment one;
485 communicating circuit figure in Figure 15 embodiment one;
Power-switching circuit figure in Figure 16 embodiment one.
[embodiment]
First summarize harmonic compensation principle: current transformer is detected that load current calculates, calculate load current fundametal compoment, harmonic wave, idle, unbalanced component, then produce amplitude with harmonic wave, idle, unbalanced component is identical, phase place and harmonic wave, the electric current that idle, unbalanced component is contrary, this electric current and harmonic wave, idle, unbalanced component offset, thus obtain the net current of only remaining fundametal compoment.Its operation principle as shown in Figure 1, wherein:
Is=iL+iC, wherein iL is load current, the non-offset current of iC;-----------(1)
] iL=iLf+iLh, wherein iLf is the fundametal compoment of load current, and iLh is the harmonic wave in load current, idle, unsymmetrical current component;-----------(2)
iC＝-iLh；-----------(3)
By formula (1), (2), (3) draw:
is＝iLf+iLh+iC＝iLf+iLh+(-iLh)＝iLf
In order to make the technical solution of the utility model and technique effect clearly, be described in detail below in conjunction with the embodiment of drawings and Examples to this patent.
Embodiment one:
As Fig. 2, the three-level inverter harmonic compensation device in the present embodiment, comprises main control module, neutral-point-clamped three-level topology module; In main control module, the PWM output of following IGBT drive circuit connects the grid of each IGTB of neutral-point-clamped three-level topology module.Neutral-point-clamped three-level topology module is by identical with harmonic amplitude for the control output according to main control module, but the offset current that phase place is contrary.
As Fig. 3, main control module comprises first processor, second processor, 3rd processor, programmable logic device, output current iS testing circuit, load current iL testing circuit, IGBT drive circuit, load voltage VL testing circuit, load current over-current detection circuit, bus capacitor voltage detecting circuit, bus capacitor electric voltage over press testing circuit, working temperature testing circuit, zero sequence voltage detection circuit, fan failure detection circuit, fan drive circuit, first CAN communicating circuit, second CAN communicating circuit, 3rd CAN communicating circuit, one 485 communicating circuit, 2 485 communicating circuit, 3 485 communicating circuit, watchdog circuit, power converting circuit.
Output current iS testing circuit is used for detecting the current i S being supplied to load, and this detected value is exported to first processor, the second processor, the 3rd processor, and its output connects the I/O pin of first processor, the second processor, the 3rd processor respectively.Output current detection circuit is as Fig. 4, and this circuit is the circuit of a certain phase in three-phase current, and the testing circuit of other phases is identical with this circuit.The electric current of current transformer, through resistance Rr2 current limliting, after first order operational amplifier U24 input resistant matching, then exports to first processor, the second processor after the adder that second level operational amplifier U25 or U26 or U27 is formed, and the 3rd processor.
Load current iL testing circuit is used for detection and flows through load current iL, and this detected value is exported to first processor, the second processor, the 3rd processor, and its output connects the I/O pin of first processor, the second processor, the 3rd processor.Load current iL testing circuit is identical with the circuit of output current iS testing circuit, and just current sensor is connected in each phase line of load.
IGBT drive circuit is supplied to each IGBT grid PWM drive singal of neutral-point-clamped three-level topology module, and its output connects each IGBT grid in neutral-point-clamped three-level topology module, and its input connects programmable logic device.Neutral-point-clamped three-level topology module often has 4 IGBT mutually, and each IGBT drive circuit of three-phase is all identical, as Fig. 5.Qq1, U50, Qq2, Qq3 form push-pull circuit, and the pwm signal exported by programmable logic device amplifies exports to IGBT.
Load voltage VL testing circuit is used for detecting the effect compensated, and detects the voltage at load two ends, and it exports termination first processor and the 3rd processor.Load voltage VL is carried out fast Fourier transform by the 3rd processor.When harmonic wave in circuit is compensated, the voltage waveform being embodied in load two ends will without harmonic wave.The circuit of load voltage VL testing circuit is as Fig. 6, and its operation principle is identical with foregoing detection circuit.
Load current over-current detection circuit, its input is connected with load current iL testing circuit, and its output is connected with programmable logic device.When load current iL absolute value exceedes the preset value of load current over-current detection circuit; load current over-current detection circuit output overcurrent guard signal is to programmable logic device; the outputting circuit for relay that programmable logic device is connected with load according to overcurrent protection signal controlling; control this relay to disconnect, thus protection load.The circuit of load current over-current detection circuit is as Fig. 7; the first order amplifier of load current iL testing circuit exports and is connected with the input of load current over-current detection circuit; compare with the reversal value preset; as load current iL absolute value exceed the absolute value of preset value time; the output level of comparator LF353MX overturns, i.e. load current overcurrent, and programmable logic device receives overcurrent protection signal; the relay that note controls to be connected with load disconnects, thus protection load.
Electric capacity C1 and C2 that the DC side of neutral-point-clamped three-level topology module adopts two parameters identical is as energy-storage travelling wave tube, and the inverter formed for IGBT provides direct voltage to support.In order to ensure that inverter is not damaged, the voltage at electric capacity C1 and C2 two ends need in safe range.Bus capacitor voltage detecting circuit is used for detecting the voltage at C1 and C2 two ends, the magnitude of voltage of detection is exported to first processor and bus capacitor electric voltage over press testing circuit.The testing circuit of two capacitance voltages is as Fig. 8, electric capacity both end voltage is through resistance current limliting, first order operational amplifier input resistant matching, exports to first processor after the operational amplifier add operation of the second level, and wherein first order operational amplifier also exports to bus capacitor electric voltage over press testing circuit.
Bus capacitor electric voltage over press testing circuit compares magnitude of voltage and the preset value at electric capacity two ends, if exceeded, the overvoltage of electric capacity both end voltage is described, overvoltage signal is exported to programmable logic device.Overvoltage protection signal is exported to the outputting circuit for relay be connected with electric capacity by programmable logic device according to the logic of self, control this relay and disconnect.Bus capacitor electric voltage over press testing circuit is as Fig. 9, as long as have the voltage at two ends to exceed preset value in two electric capacity, the level of comparator will overturn, thus the output of the level of NPN type three collector collector electrode is overturn.Programmable logic device exported to by this triode, and the relay that programmable logic device controls to be connected with electric capacity disconnects, thus protection electric capacity is not damaged by high electrical breakdown.
IGBT in three-level inverter harmonic compensation device is high power device, have distributing of heat, therefore working temperature testing circuit and fan radiating is increased, the output of working temperature testing circuit connects the I/O pin of first processor, fan drive circuit is used for driving blower fan at different capacity, the input of fan drive circuit connects the I/O pin of programmable logic device, its output connecting fan, programmable logic device gives blower fan different rotating speeds according to different operating temperature, when temperature is higher, rotating speed is fast; Otherwise rotating speed is slow, maximized saves energy, fan failure detection circuit, when fan trouble being detected and working temperature testing circuit detects that compensation arrangement working temperature is too high, gives overheat protector simultaneously.Working temperature testing circuit is as Figure 10, and fan drive circuit is as Figure 11, and fan failure detection circuit is as Figure 12.
Being used for of zero sequence voltage detection circuit detects residual voltage, and its output connects the I/O pin of first processor, so that first processor calculates unbalanced component, circuit is as Figure 13.The voltage that three-phase type voltage transformer secondary side records is through resistance current limliting, and the impedance matching of first order operational amplifier, exports to first processor after the operational amplifier add operation of the second level.
First CAN communicating circuit is connected with first processor, second CAN communicating circuit is connected with the second processor, 3rd CAN communicating circuit is connected with the 3rd processor, each CAN communicating circuit, so that external object understands the running status of whole compensation arrangement in real time, obtains real time data.Circuit is as Figure 14.
So that with the outside communication apparatus with RS485 communicaton protocol is compatible, the one 485 communicating circuit, the 2 485 communicating circuit, the 3 485 communicating circuit is all connected with programmable logic device, also can be the communicating circuit of RS232 communications protocol.I/O number of pin as first processor, the second processor, the 3rd processor is enough, and the one 485 communicating circuit, the 2 485 communicating circuit, the 3 485 communicating circuit also can be connected with first processor, the second processor, the 3rd processor respectively.The circuit of the one 485 communicating circuit, the 2 485 communicating circuit, the 3 485 communicating circuit is identical, as Figure 15.
The output current iS of input and load current iL is carried out fast connect (hereinafter referred to as FFT) conversion by the 3rd processor, and transformation results is exported to programmable logic device.The model of the 3rd processor is TMS320F2808PZA.
Programmable logic device, receives the control command of first processor and control command is exported to corresponding circuit, or the logic output order according to self gives corresponding circuit, and the transformation results of the 3rd processor is inputed to the second processor.The model of programmable logic device is EPM570F256C5N.
Second processor calculates the fundametal compoment of load current iL, each harmonic component, idle and multiple order components, and compare with the identical sampling number certificate of iS, thus judge compensate type and compensate size, calculate the driving logic of IGBT, the driving logic of IGBT is exported to first processor.The model of the second processor is TMS320F2808PZA.
First processor respectively with the second processor, 3rd processor, programmable logic device connects, and first processor is according to the running status of this compensation arrangement, compensation arrangement at normal operating condition time, by from the second processor IGBT drive logic export to programmable logic device; Maybe the temperature protection signal calculated and zero sequence imbalance compensation signal are exported to programmable logic device.The model of first processor is TMS320F2808PZA.
Work as first processor, the second processor, the deal with data of the 3rd processor is too much, and during insufficient memory, can increase first memory respectively and be connected with first processor, second memory is connected with the second processor, and the 3rd memory is connected with the 3rd processor.
The output of watchdog circuit and first processor, the second processor, the 3rd processor, the resetting pin of programmable logic device is connected, and to avoid first processor, the second processor, the 3rd processor, deadlock phenomenon appears in the operation of programmable logic device.Watchdog circuit is optional gets watchdog circuit of the prior art.
External power source is converted to the power supply that in main control module, other circuit need by power-switching circuit, is connected with the power input of other circuit.As Figure 16, outside 15V power supply exports 3.3V voltage through chip U17 voltage stabilizing, and outside 15V power supply exports 5V voltage through chip U22 voltage stabilizing, and 3.3V voltage exports 1.8V voltage through chip U16 voltage stabilizing again.
The foregoing is only the preferred embodiment of this patent, be not limited to this patent, for a person skilled in the art, this patent can have various modifications and variations.Within all spirit at this patent and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in this patent.
Claims (5)
1. a three-level inverter harmonic compensation device, comprises main control module, neutral-point-clamped three-level topology module;
Main control module comprises first processor, the second processor, the 3rd processor, programmable logic device, output current iS testing circuit, load current iL testing circuit, IGBT drive circuit, power converting circuit;
Output current iS testing circuit is used for detecting the current i S being supplied to load, and this detected value is exported to first processor, the second processor, the 3rd processor, and its output connects the I/O pin of first processor, the second processor, the 3rd processor respectively;
Load current iL testing circuit is used for detection and flows through load current iL, and this detected value is exported to first processor, the second processor, the 3rd processor, and its output connects the I/O pin of first processor, the second processor, the 3rd processor respectively;
IGBT drive circuit is supplied to each IGBT grid PWM drive singal of neutral-point-clamped three-level topology module, and its output connects each IGBT grid in neutral-point-clamped three-level topology module, and its input connects programmable logic device;
First processor respectively with the second processor, the 3rd processor is connected with programmable logic device;
Programmable logic device, receives the control command of first processor and control command is exported to corresponding circuit, or the logic output order according to self gives corresponding circuit, and the transformation results of the 3rd processor is inputed to the second processor;
Power-switching circuit, for the conversion by external power source, it exports the power input connecting other circuit in main control module;
Neutral-point-clamped three-level topology module is by identical with harmonic amplitude in load current for the control output according to main control module, but the offset current that phase place is contrary.
2. three-level inverter harmonic compensation device as claimed in claim 1, it is characterized in that: three-level inverter harmonic compensation device also comprises input and connects load current iL testing circuit, and output connects the load current over-current detection circuit of programmable logic device.
3. three-level inverter harmonic compensation device as claimed in claim 1, is characterized in that: three-level inverter harmonic compensation device also comprises the bus capacitor voltage detecting circuit that output connects first processor.
4. three-level inverter harmonic compensation device as claimed in claim 1, it is characterized in that: three-level inverter harmonic compensation device also comprises input and is connected with bus capacitor voltage detecting circuit, the bus capacitor electric voltage over press testing circuit that output is connected with programmable logic device.
5. three-level inverter harmonic compensation device as claimed in claim 1, is characterized in that: three-level inverter harmonic compensation device also comprises the zero sequence voltage detection circuit that output is connected with first processor.
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| CN201420625963.6U CN204216776U (en) | 2014-10-27 | 2014-10-27 | A kind of three-level inverter harmonic compensation device |
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| CN201420625963.6U CN204216776U (en) | 2014-10-27 | 2014-10-27 | A kind of three-level inverter harmonic compensation device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788050A (en) * | 2016-12-23 | 2017-05-31 | 广东高标电子科技有限公司 | Power device control and overheat protector system and method for electric machine controller |
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- 2014-10-27 CN CN201420625963.6U patent/CN204216776U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788050A (en) * | 2016-12-23 | 2017-05-31 | 广东高标电子科技有限公司 | Power device control and overheat protector system and method for electric machine controller |
| CN106788050B (en) * | 2016-12-23 | 2023-06-20 | 广东高标电子科技有限公司 | Power device control and over-temperature protection system and method for motor controller |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150318 Termination date: 20191027 |
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| CF01 | Termination of patent right due to non-payment of annual fee |