CN204190718U - A kind of double buffering triggering system based on symmetric set electric pole type - Google Patents
A kind of double buffering triggering system based on symmetric set electric pole type Download PDFInfo
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- CN204190718U CN204190718U CN201420629555.8U CN201420629555U CN204190718U CN 204190718 U CN204190718 U CN 204190718U CN 201420629555 U CN201420629555 U CN 201420629555U CN 204190718 U CN204190718 U CN 204190718U
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- inverting amplifier
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- oscillating circuit
- crystal oscillating
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Abstract
The utility model discloses a kind of double buffering triggering system based on symmetric set electric pole type, primarily of mutually redundant host buffer crystal oscillating circuit and secondary buffered crystal oscillating circuit composition, it is characterized in that, also be provided with the symmetric set electric pole type circuits for triggering be connected with secondary buffered crystal oscillating circuit with this host buffer crystal oscillating circuit, described symmetric set electric pole type circuits for triggering are by transistor Q1, transistor Q2, one end is connected with the collector electrode of transistor Q1, the resistance R1 that the other end is connected with the base stage of transistor Q1 after diode D1, the compositions such as the electric capacity C3 be in parallel with resistance R1.The utility model overall structure is comparatively simple, and it makes and very easy to use.Meanwhile, the utility model takes full advantage of the nonlinear characteristic of symmetric set electric pole type circuits for triggering, can reduce power consumption significantly.
Description
Technical field
The utility model relates to a kind of triggering system, specifically refers to a kind of double buffering triggering system based on symmetric set electric pole type.
Background technology
Trigger is component basic in digital integrated circuit, and they decide the performance comprising the circuit such as power consumption, delay, area, reliability.But all adopt positive pulse to trigger when using trigger at current most circuit, the circuit structure design of these triggers is comparatively complicated in addition, therefore its power consumption is comparatively large, is unfavorable for extensive promotion and application.
Utility model content
The purpose of this utility model is that the circuit structure overcome existing for current trigger is complicated, and the defect that power consumption is larger provides a kind of structure simple, effectively can reduce the double buffering triggering system based on symmetric set electric pole type of power consumption.
The purpose of this utility model is achieved through the following technical solutions: a kind of double buffering triggering system based on symmetric set electric pole type, primarily of mutually redundant host buffer crystal oscillating circuit and secondary buffered crystal oscillating circuit composition, simultaneously, also be provided with the symmetric set electric pole type circuits for triggering be connected with secondary buffered crystal oscillating circuit with this host buffer crystal oscillating circuit, described symmetric set electric pole type circuits for triggering are by transistor Q1, transistor Q2, one end is connected with the collector electrode of transistor Q1, the resistance R1 that the other end is connected with the base stage of transistor Q1 after diode D1, the electric capacity C3 be in parallel with resistance R1, one end is connected with the collector electrode of transistor Q2, the resistance R2 that the other end is connected with the base stage of transistor Q2 after diode D2, the electric capacity C4 be in parallel with resistance R2, tie point and the diode D2 of one end and diode D1 and resistance R1 are connected with the tie point of resistance R2 simultaneously, the resistance R3 of the external+6V voltage of the other end forms, described host buffer crystal oscillating circuit and resistance R1 are in parallel, and secondary buffered crystal oscillating circuit and resistance R2 are in parallel.
Further, described host buffer crystal oscillating circuit is by inverting amplifier U2, the inverting amplifier U3 that input is connected with the output of inverting amplifier U2, positive pole is connected with the input of inverting amplifier U2, negative pole in turn through the tunable capacitor C2 that inductance L 1 is connected with the output of inverting amplifier U2 after inductance L 2, and the quartz oscillator X2 that one end is connected with the input of inverting amplifier U2, the other end is connected with the tie point of inductance L 2 with inductance L 1 forms; The output of described inverting amplifier U3 is connected with the collector electrode of transistor Q2; The positive pole of tunable capacitor C2 is then connected with the tie point of resistance R2 with the tie point of diode D1 and resistance R1 and diode D2 respectively.
Described secondary buffered crystal oscillating circuit is by inverting amplifier U1, the inverting amplifier U4 that input is connected with the output of inverting amplifier U1, positive pole is connected with the input of inverting amplifier U1, negative pole in turn through the tunable capacitor C1 that inductance L 3 is connected with the output of inverting amplifier U1 after inductance L 4, and the quartz oscillator X1 that one end is connected with the input of inverting amplifier U1, the other end is connected with the tie point of inductance L 4 with inductance L 3 forms; The output of described inverting amplifier U4 is connected with the collector electrode of transistor Q1; The positive pole of tunable capacitor C1 is then connected with the tie point of resistance R2 with the tie point of diode D1 and resistance R1 and diode D2 respectively.
The utility model comparatively prior art is compared, and has the following advantages and beneficial effect:
(1) the utility model overall structure is comparatively simple, and it makes and very easy to use.
(2) the utility model takes full advantage of the nonlinear characteristic of symmetric set electric pole type circuits for triggering, can reduce power consumption significantly.
(3) host buffer crystal oscillating circuit of the present utility model and secondary buffered crystal oscillating circuit backup each other, and therefore when any one buffered crystal oscillating circuit is malfunctioning, all can not affect the normal work of whole trigger.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present utility model.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but execution mode of the present utility model is not limited thereto.
Embodiment
As shown in Figure 1, the utility model primarily of mutually redundant host buffer crystal oscillating circuit and secondary buffered crystal oscillating circuit, and forms with the symmetric set electric pole type circuits for triggering that this host buffer crystal oscillating circuit is connected with secondary buffered crystal oscillating circuit.
Wherein, symmetric set electric pole type circuits for triggering are by transistor Q1, and transistor Q2, resistance R1, resistance R2, resistance R3, electric capacity C3, electric capacity C4 and diode D1 and diode D2 form.During connection, one end of resistance R1 is connected with the collector electrode of transistor Q1, its other end is connected with the base stage of transistor Q1 after diode D1, and electric capacity C3 and resistance R1 is in parallel.For guaranteeing effect, the P pole of this diode D1 must be connected with the base stage of transistor Q1, and its N pole is then connected with the negative pole of electric capacity C3.
One end of resistance R2 is connected with the collector electrode of transistor Q2, and its other end is connected with the base stage of transistor Q2 after diode D2, and electric capacity C4 and resistance R2 is in parallel.For guaranteeing effect, the P pole of this diode D2 must be connected with the base stage of transistor Q2, and its N pole is then connected with the negative pole of electric capacity C4.Tie point and the diode D2 of one end of resistance R3 and diode D1 and resistance R1 are connected with the tie point of resistance R2 simultaneously, the external+6V voltage of its other end.
Described host buffer crystal oscillating circuit is by inverting amplifier U2, and inverting amplifier U3, inductance L 1, inductance L 2, tunable capacitor C2 and quartz oscillator X2 forms.During connection, the input of inverting amplifier U3 is connected with the output of inverting amplifier U2; The positive pole of tunable capacitor C2 is connected with the input of inverting amplifier U2, and its negative pole is connected with the output of inverting amplifier U2 after inductance L 2 through inductance L 1 in turn; One end of quartz oscillator X2 is connected with the input of inverting amplifier U2, and its other end is connected with the tie point of inductance L 1 with inductance L 2.The output of described inverting amplifier U3 is connected with the collector electrode of transistor Q2, and the positive pole of tunable capacitor C2 is then connected with the tie point of resistance R2 with the tie point of diode D1 and resistance R1 and diode D2 respectively.
Described secondary buffered crystal oscillating circuit is by inverting amplifier U1, and inverting amplifier U4, inductance L 3, inductance L 4, quartz oscillator X1 and tunable capacitor C1 forms.During connection, the input of inverting amplifier U4 is connected with the output of inverting amplifier U1; The positive pole of tunable capacitor C1 is connected with the input of inverting amplifier U1, and its negative pole is connected with the output of inverting amplifier U1 after inductance L 4 through inductance L 3 in turn; One end of quartz oscillator X1 is connected with the input of inverting amplifier U1, and its other end is connected with the tie point of inductance L 3 with inductance L 4.The output of described inverting amplifier U4 is connected with the collector electrode of transistor Q1, and the positive pole of tunable capacitor C1 is then connected with the tie point of resistance R2 with the tie point of diode D1 and resistance R1 and diode D2 respectively.
As mentioned above, just the utility model can well be realized.
Claims (3)
1. the double buffering triggering system based on symmetric set electric pole type, primarily of mutually redundant host buffer crystal oscillating circuit and secondary buffered crystal oscillating circuit composition, it is characterized in that, also be provided with the symmetric set electric pole type circuits for triggering be connected with secondary buffered crystal oscillating circuit with this host buffer crystal oscillating circuit, described symmetric set electric pole type circuits for triggering are by transistor Q1, transistor Q2, one end is connected with the collector electrode of transistor Q1, the resistance R1 that the other end is connected with the base stage of transistor Q1 after diode D1, the electric capacity C3 be in parallel with resistance R1, one end is connected with the collector electrode of transistor Q2, the resistance R2 that the other end is connected with the base stage of transistor Q2 after diode D2, the electric capacity C4 be in parallel with resistance R2, tie point and the diode D2 of one end and diode D1 and resistance R1 are connected with the tie point of resistance R2 simultaneously, the resistance R3 of the external+6V voltage of the other end forms, described host buffer crystal oscillating circuit and resistance R1 are in parallel, and secondary buffered crystal oscillating circuit and resistance R2 are in parallel.
2. a kind of double buffering triggering system based on symmetric set electric pole type according to claim 1, it is characterized in that, described host buffer crystal oscillating circuit is by inverting amplifier U2, the inverting amplifier U3 that input is connected with the output of inverting amplifier U2, positive pole is connected with the input of inverting amplifier U2, negative pole is in turn through tunable capacitor C2 that inductance L 1 is connected with the output of inverting amplifier U2 after inductance L 2, and one end is connected with the input of inverting amplifier U2, the quartz oscillator X2 that the other end is connected with the tie point of inductance L 2 with inductance L 1 forms, the output of described inverting amplifier U3 is connected with the collector electrode of transistor Q2, the positive pole of tunable capacitor C2 is then connected with the tie point of resistance R2 with the tie point of diode D1 and resistance R1 and diode D2 respectively.
3. a kind of double buffering triggering system based on symmetric set electric pole type according to claim 2, it is characterized in that, described secondary buffered crystal oscillating circuit is by inverting amplifier U1, the inverting amplifier U4 that input is connected with the output of inverting amplifier U1, positive pole is connected with the input of inverting amplifier U1, negative pole is in turn through tunable capacitor C1 that inductance L 3 is connected with the output of inverting amplifier U1 after inductance L 4, and one end is connected with the input of inverting amplifier U1, the quartz oscillator X1 that the other end is connected with the tie point of inductance L 4 with inductance L 3 forms, the output of described inverting amplifier U4 is connected with the collector electrode of transistor Q1, the positive pole of tunable capacitor C1 is then connected with the tie point of resistance R2 with the tie point of diode D1 and resistance R1 and diode D2 respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420629555.8U CN204190718U (en) | 2014-10-28 | 2014-10-28 | A kind of double buffering triggering system based on symmetric set electric pole type |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420629555.8U CN204190718U (en) | 2014-10-28 | 2014-10-28 | A kind of double buffering triggering system based on symmetric set electric pole type |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204190718U true CN204190718U (en) | 2015-03-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420629555.8U Expired - Fee Related CN204190718U (en) | 2014-10-28 | 2014-10-28 | A kind of double buffering triggering system based on symmetric set electric pole type |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204190718U (en) |
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2014
- 2014-10-28 CN CN201420629555.8U patent/CN204190718U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150304 Termination date: 20151028 |
|
| EXPY | Termination of patent right or utility model |