CN204177961U - -kind based on the S mode secondary radar demoder of FPGA - Google Patents
-kind based on the S mode secondary radar demoder of FPGA Download PDFInfo
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- CN204177961U CN204177961U CN201420682250.3U CN201420682250U CN204177961U CN 204177961 U CN204177961 U CN 204177961U CN 201420682250 U CN201420682250 U CN 201420682250U CN 204177961 U CN204177961 U CN 204177961U
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Abstract
The utility model relates to a kind of S mode secondary radar demoder based on FPGA, comprise power phases treatment circuit, its input end is connected with three tunnel intermediate-freuqncy signal output terminals of receiver, its output terminal is connected with the input end of pulse processing circuit, the output terminal of pulse processing circuit is connected with the input end of S mode decoding circuit, secondary radar normal mode decoding circuit respectively, and the output terminal of S mode decoding circuit, secondary radar normal mode decoding circuit is all connected with an input end for flight path processing device.The all module of the utility model all completes in a slice programmable gate array FPGA controller, makes full use of the feature of FPGA controller high speed, high-performance, parallel processing, improves the efficiency of radar process, there is compact conformation, stability is high, and processing speed is fast, realizes the advantages such as flexible.
Description
Technical field
The utility model relates to airway traffic control surveillance radar technical field, especially a kind of S mode secondary radar demoder based on FPGA.
Background technology
S mode secondary radar, monitors and data link ability for airway traffic control (ATC) provides.The aircraft identification code (A code) of conventional secondary radar only has 4096 can distribute, and S mode aircraft is by the aircraft geocoding one-tenth of 24
individual code, efficiently solves the problem of aircraft code resource shortage.Every airplane all distributes 24 unique bit address, when inquiring by calling the roll, aircraft answering machine will carry out address consistency desired result, just response is made when only having Asking About The Address identical with answering machine address, so that the transponder pulse of aircraft is not overlapping, effectively reduce synchronous crosstalk (GARBLE) thus.
Current S mode secondary radar scrambler mainly adopts the scheme of FPGA+DSP, and FPGA does the pre-service of S mode decoding, then needs data to be imported into DSP and does further process.FPGA device has significant progress in performance, density and power consumption, has been widely used in various signal transacting field, and make the digital information processing system constructed can keep the dirigibility of the solution based on software, cost advantage is obvious compared with DSP.S mode secondary radar codec can complete completely in FPGA, without using expensive dsp chip.
Utility model content
The purpose of this utility model is to provide the characteristic of the low and stable performance of a kind of high speed, parallel processing, cost making full use of FPGA, without the need to DSP, and decreases the S mode secondary radar demoder based on FPGA of the transceiver interface module between FPGA and DSP.
For achieving the above object, the utility model have employed following technical scheme: a kind of S mode secondary radar demoder based on FPGA, comprise power phases treatment circuit, its input end is connected with three tunnel intermediate-freuqncy signal output terminals of receiver, its output terminal is connected with the input end of pulse processing circuit, the output terminal of pulse processing circuit is connected with the input end of S mode decoding circuit, secondary radar normal mode decoding circuit respectively, and the output terminal of S mode decoding circuit, secondary radar normal mode decoding circuit is all connected with an input end for flight path processing device.
Described power phases treatment circuit comprises the △ intermediate frequency exported for receiving receiver respectively, ∑ intermediate frequency, first of Ω intermediate-freuqncy signal, two, three Digital Down Converts, first, two, the output terminal of three Digital Down Converts is respectively with first, two, the input end that three power phases produce circuit is connected, first power phases produces the output terminal anti-STC compensating circuit with first respectively of circuit, second input end of amplitude and phase correction circuit is connected, second power phases produces the output terminal anti-STC compensating circuit with second respectively of circuit, the four-input terminal of amplitude and phase correction circuit is connected, 3rd power phases produces the output terminal anti-STC compensating circuit with the 3rd respectively of circuit, 6th input end of amplitude and phase correction circuit is connected, first, two, the output terminal of three anti-STC compensating circuits respectively with first of amplitude and phase correction circuit, three, five input ends are connected.
Described S mode decoding circuit comprises the leading identification circuit of S mode, its input end is connected with the first output terminal of pulse processing circuit, its output terminal suppresses the input end of circuit to be connected with the first secondary lobe TTC, first secondary lobe TTC suppresses the output terminal of circuit to be connected with the input end of decoding circuit, the output terminal of decoding circuit is connected with the input end of S mode error correction circuit, the output terminal of S mode error correction circuit is connected with the input end of the asynchronous suppression circuit of S mode, the output terminal of the asynchronous suppression circuit of S mode is connected with the input end of S mode code instrumentation circuit, the output terminal of S mode code instrumentation circuit is connected with the input end of the first original response report generation circuit, the output terminal of the first original response report generation circuit is connected with an input end for flight path processing device.
Described secondary radar normal mode decoding circuit comprises S and replys filtering circuit, its input end is connected with the second output terminal of pulse processing circuit, its output terminal is connected with the input end of framework identification circuit, the output terminal of framework identification circuit suppresses the input end of circuit to be connected with the second secondary lobe TTC, second secondary lobe TTC suppresses the output terminal of circuit to be connected with the input end of degree of confidence treatment circuit, the output terminal of degree of confidence treatment circuit is connected with the input end of overlapping bursts treatment circuit, output terminal and the phantom of overlapping bursts treatment circuit suppress the input end of circuit to be connected, phantom suppresses the output terminal of circuit to be connected with the input end of asynchronous suppression circuit, the output terminal of asynchronous suppression circuit is connected with the input end of code instrumentation circuit, the output terminal of code instrumentation circuit is connected with the input end of the second original response report generation circuit, the output terminal of the second original response report generation circuit is connected with an input end for flight path processing device.
Described pulse processing circuit respectively with buffer FIFO, DPRAM internal memory both-way communication.
First output terminal of described amplitude and phase correction circuit respectively with the first input end of phase detector, the first input end of pulse processing circuit is connected, second output terminal of amplitude and phase correction circuit is connected with the second input end of phase detector, the output terminal of phase detector is connected with the second input end of pulse processing circuit, the 3rd output terminal of amplitude and phase correction circuit respectively with the first squelch and 6dB testing circuit, the first input end of RSLS circuit, the four-input terminal of pulse processing circuit is connected, the 4th output terminal of amplitude and phase correction circuit respectively with the second squelch and 6dB testing circuit, second input end of RSLS circuit, 6th input end of pulse processing circuit is connected, the 5th output terminal of amplitude and phase correction circuit respectively with the 3rd squelch and 6dB testing circuit, 3rd input end of RSLS circuit, 8th input end of pulse processing circuit is connected, and first, two, the output terminal of three squelch and 6dB testing circuit respectively with the 3rd of pulse processing circuit, five, nine input ends are connected, and the output terminal of described RSLS circuit is connected with the 7th input end of pulse processing circuit.
As shown from the above technical solution, all module of the utility model all completes in a slice programmable gate array FPGA controller, makes full use of the feature of FPGA controller high speed, high-performance, parallel processing, improves the efficiency of radar process; Owing to having given up the mode casting out FPGA+DSP, not only cost-saving, and system decreases transceiver interface module between FPGA controller and dsp processor, and structure is simpler.In a word, S mode decoding process of the present utility model all completes in FPGA controller, and can be achieved by Programmable Logic Device, have compact conformation, stability is high, and processing speed is fast, realizes the advantages such as flexible.
Accompanying drawing explanation
Fig. 1 is system architecture diagram of the present utility model.
Embodiment
A kind of S mode secondary radar demoder based on FPGA, comprise power phases treatment circuit 1, its input end is connected with three tunnel intermediate-freuqncy signal output terminals of receiver, its output terminal is connected with the input end of pulse processing circuit 2, the output terminal of pulse processing circuit 2 respectively with S mode decoding circuit 3, the input end of secondary radar normal mode decoding circuit 4 is connected, S mode decoding circuit 3, the output terminal of secondary radar normal mode decoding circuit 4 is all connected with an input end for flight path processing device, as shown in Figure 1, described pulse processing circuit 2 respectively with buffer FIFO, DPRAM internal memory both-way communication.
As shown in Figure 1, described power phases treatment circuit 1 comprises the △ intermediate frequency exported for receiving receiver respectively, ∑ intermediate frequency, first of Ω intermediate-freuqncy signal, two, three Digital Down Converts, first, two, the output terminal of three Digital Down Converts is respectively with first, two, the input end that three power phases produce circuit is connected, first power phases produces the output terminal anti-STC compensating circuit with first respectively of circuit, second input end of amplitude and phase correction circuit is connected, second power phases produces the output terminal anti-STC compensating circuit with second respectively of circuit, the four-input terminal of amplitude and phase correction circuit is connected, 3rd power phases produces the output terminal anti-STC compensating circuit with the 3rd respectively of circuit, 6th input end of amplitude and phase correction circuit is connected, first, two, the output terminal of three anti-STC compensating circuits respectively with first of amplitude and phase correction circuit, three, five input ends are connected.
As shown in Figure 1, described S mode decoding circuit 3 comprises the leading identification circuit of S mode, its input end is connected with the first output terminal of pulse processing circuit 2, its output terminal suppresses the input end of circuit to be connected with the first secondary lobe TTC, first secondary lobe TTC suppresses the output terminal of circuit to be connected with the input end of decoding circuit, the output terminal of decoding circuit is connected with the input end of S mode error correction circuit, the output terminal of S mode error correction circuit is connected with the input end of the asynchronous suppression circuit of S mode, the output terminal of the asynchronous suppression circuit of S mode is connected with the input end of S mode code instrumentation circuit, the output terminal of S mode code instrumentation circuit is connected with the input end of the first original response report generation circuit, the output terminal of the first original response report generation circuit is connected with an input end for flight path processing device.
As shown in Figure 1, described secondary radar normal mode decoding circuit 4 comprises S and replys filtering circuit, its input end is connected with the second output terminal of pulse processing circuit 2, its output terminal is connected with the input end of framework identification circuit, the output terminal of framework identification circuit suppresses the input end of circuit to be connected with the second secondary lobe TTC, second secondary lobe TTC suppresses the output terminal of circuit to be connected with the input end of degree of confidence treatment circuit, the output terminal of degree of confidence treatment circuit is connected with the input end of overlapping bursts treatment circuit, output terminal and the phantom of overlapping bursts treatment circuit suppress the input end of circuit to be connected, phantom suppresses the output terminal of circuit to be connected with the input end of asynchronous suppression circuit, the output terminal of asynchronous suppression circuit is connected with the input end of code instrumentation circuit, the output terminal of code instrumentation circuit is connected with the input end of the second original response report generation circuit, the output terminal of the second original response report generation circuit is connected with an input end for flight path processing device.
As shown in Figure 1, the first output terminal of described amplitude and phase correction circuit respectively with the first input end of phase detector, the first input end of pulse processing circuit 2 is connected, second output terminal of amplitude and phase correction circuit is connected with the second input end of phase detector, the output terminal of phase detector is connected with the second input end of pulse processing circuit 2, the 3rd output terminal of amplitude and phase correction circuit respectively with the first squelch and 6dB testing circuit, the first input end of RSLS circuit, the four-input terminal of pulse processing circuit 2 is connected, the 4th output terminal of amplitude and phase correction circuit respectively with the second squelch and 6dB testing circuit, second input end of RSLS circuit, 6th input end of pulse processing circuit 2 is connected, the 5th output terminal of amplitude and phase correction circuit respectively with the 3rd squelch and 6dB testing circuit, 3rd input end of RSLS circuit, 8th input end of pulse processing circuit 2 is connected, and first, two, the output terminal of three squelch and 6dB testing circuit respectively with the 3rd of pulse processing circuit 2, five, nine input ends are connected, and the output terminal of described RSLS circuit is connected with the 7th input end of pulse processing circuit 2.
Below in conjunction with Fig. 1, the utility model is further described.
From the ∑ intermediate frequency that receiver receives, △ intermediate frequency, Ω intermediate frequency three tunnel simulating signal is sent into FPGA controller and is carried out S mode secondary radar decoding process after AD sampling: first through Digital Down Convert, power is asked to ask phase place, anti-STC, width/correct mutually, then squelch and 6dB detect, phase place is differentiated, secondary lobe suppresses (RSLS), pulse pre-service, high-density power identification, amplitude threshold able to programme controls (TTC), raw data is packed, then to ∑ video, △ video, Ω vision signal carries out S mode decoding process and the conventional A/C mode treatment of secondary radar.
The utility model adopts has anti-STC compensating circuit, avoids the fluctuating of transponder pulse signal amplitude to cause answer signal to lose.Sensitivity time control (STC) be solve receiver dynamic range saturated and arrange adjustable attenuation, arrange by far away and adjustable attenuation that is nearly lifting step by step within the scope of radar maximum detectable range, when the pulse of same answer signal is in different distance segment, because damping capacity is different, the amplitude of pulse will change, so the correlativity of paired pulses has an impact.
There is amplitude threshold able to programme and control (TTC) function, threshold value can be set to any sector, there are 5 controling parameters such as starting orientation, end orientation, the distance that starts, end Distance geometry STC value each sector, distance increment is minimum reaches 7.5 meters, minimum fan peak width is 1.4 °, to reach the object of inhibitory reflex and other interference noises.
From the △ intermediate frequency that receiver is come, ∑ intermediate frequency, this three roads signal of Ω intermediate frequency sends into the decoding process that fpga chip carries out S mode secondary radar after being adopted by high-speed AD: first three tunnel intermediate-freuqncy signals are through Digital Down Convert, produce I/Q quadrature digital signal, then power asked to I/Q and ask phase place; Anti-STC compensating circuit compensates power LOG, and the size of compensation rate depends on that the anti-saturation of receiver in front end arranges STC damping capacity; Amplitude and phase correction circuit is for benchmark with Σ passage, the amplitude of △ passage and phase place are corrected, correct the amplitude of Ω passage, the correction of amplitude can correctly calculate and differ from ratio, and the correction of phase place correctly can estimate that orientation departs from the Left or right of beam axis.
Phase detector carries out phase demodulation by the ∑ phase place after amplitude and phase correction circuit and △ phase place, produces and represents that target departs from the left of beam center or axis instruction BI (2) on right side; △ passage after width/mutually corrects, ∑ passage, the power of Ω passage gives squelch and 6dB testing circuit, produces the signal Q representing transponder pulse half-amplitude point width, represents the existence of transponder pulse; Secondary lobe suppresses circuit to represent that response is the RSLS mark from secondary lobe direction or main lobe direction by producing the comparison of ∑, △ and Ω tri-video amplitude; Pulse processing circuit 2 produces the signal LE in indicating impulse forward position according to the Q signal duration of pulse; The Q signal of ∑ passage produces the signal PF_PHD representing S mode response message bit length in pulse processing circuit 2; Pulse processing circuit 2, by the power of ∑ passage and comparing of TTC thresholding, produces higher than the label L E_TTC still lower than thresholding; Finally 39 bit data after previous processed are packed, be sent to S mode decoding circuit 3, secondary radar normal mode decoding circuit 4 respectively.
For normal mode SSR, first carry out S and reply filtering, filter the interference of S mode response to SSR response decoding, then be framework identification, secondary lobe suppresses and TTC suppresses process, DISCHARGE PULSES EXTRACTION and to calculate ∑ video and △ video and difference suppresses than SDR, overlapping bursts analysis (marking front overlapping or overlapping afterwards), phantom and the filtering of asynchronous interference, last code instrumentation obtains normal mode reply data.For S mode, first leading identification is carried out, secondly secondary lobe suppresses process and TTC process, then S mode decoding is carried out, ∑ video and △ video are calculated and differed from than SDR simultaneously, and carry out the judgement of code and degree of confidence, carry out error-detection error-correction according to degree of confidence subsequently, last code instrumentation process, produces original response report.
In sum, all module of the utility model all completes in a slice programmable gate array FPGA controller, makes full use of the feature of FPGA controller high speed, high-performance, parallel processing, improves the efficiency of radar process; Owing to having given up the mode casting out FPGA+DSP, not only cost-saving, and system decreases transceiver interface module between FPGA controller and dsp processor, and structure is simpler.In a word, S mode decoding process of the present utility model all completes in FPGA controller, and can be achieved by Programmable Logic Device, have compact conformation, stability is high, and processing speed is fast, realizes the advantages such as flexible.
Claims (6)
1. the S mode secondary radar demoder based on FPGA, it is characterized in that: comprise power phases treatment circuit (1), its input end is connected with three tunnel intermediate-freuqncy signal output terminals of receiver, its output terminal is connected with the input end of pulse processing circuit (2), the output terminal of pulse processing circuit (2) is connected with the input end of S mode decoding circuit (3), secondary radar normal mode decoding circuit (4) respectively, and the output terminal of S mode decoding circuit (3), secondary radar normal mode decoding circuit (4) is all connected with an input end for flight path processing device.
2. the S mode secondary radar demoder based on FPGA according to claim 1, it is characterized in that: described power phases treatment circuit (1) comprises the △ intermediate frequency exported for receiving receiver respectively, ∑ intermediate frequency, first of Ω intermediate-freuqncy signal, two, three Digital Down Converts, first, two, the output terminal of three Digital Down Converts is respectively with first, two, the input end that three power phases produce circuit is connected, first power phases produces the output terminal anti-STC compensating circuit with first respectively of circuit, second input end of amplitude and phase correction circuit is connected, second power phases produces the output terminal anti-STC compensating circuit with second respectively of circuit, the four-input terminal of amplitude and phase correction circuit is connected, 3rd power phases produces the output terminal anti-STC compensating circuit with the 3rd respectively of circuit, 6th input end of amplitude and phase correction circuit is connected, first, two, the output terminal of three anti-STC compensating circuits respectively with first of amplitude and phase correction circuit, three, five input ends are connected.
3. the S mode secondary radar demoder based on FPGA according to claim 1, it is characterized in that: described S mode decoding circuit (3) comprises the leading identification circuit of S mode, its input end is connected with the first output terminal of pulse processing circuit (2), its output terminal suppresses the input end of circuit to be connected with the first secondary lobe TTC, first secondary lobe TTC suppresses the output terminal of circuit to be connected with the input end of decoding circuit, the output terminal of decoding circuit is connected with the input end of S mode error correction circuit, the output terminal of S mode error correction circuit is connected with the input end of the asynchronous suppression circuit of S mode, the output terminal of the asynchronous suppression circuit of S mode is connected with the input end of S mode code instrumentation circuit, the output terminal of S mode code instrumentation circuit is connected with the input end of the first original response report generation circuit, the output terminal of the first original response report generation circuit is connected with an input end for flight path processing device.
4. the S mode secondary radar demoder based on FPGA according to claim 1, it is characterized in that: described secondary radar normal mode decoding circuit (4) comprises S and replys filtering circuit, its input end is connected with the second output terminal of pulse processing circuit (2), its output terminal is connected with the input end of framework identification circuit, the output terminal of framework identification circuit suppresses the input end of circuit to be connected with the second secondary lobe TTC, second secondary lobe TTC suppresses the output terminal of circuit to be connected with the input end of degree of confidence treatment circuit, the output terminal of degree of confidence treatment circuit is connected with the input end of overlapping bursts treatment circuit, output terminal and the phantom of overlapping bursts treatment circuit suppress the input end of circuit to be connected, phantom suppresses the output terminal of circuit to be connected with the input end of asynchronous suppression circuit, the output terminal of asynchronous suppression circuit is connected with the input end of code instrumentation circuit, the output terminal of code instrumentation circuit is connected with the input end of the second original response report generation circuit, the output terminal of the second original response report generation circuit is connected with an input end for flight path processing device.
5. the S mode secondary radar demoder based on FPGA according to claim 1, is characterized in that: described pulse processing circuit (2) respectively with buffer FIFO, DPRAM internal memory both-way communication.
6. the S mode secondary radar demoder based on FPGA according to claim 2, it is characterized in that: the first output terminal of described amplitude and phase correction circuit respectively with the first input end of phase detector, the first input end of pulse processing circuit (2) is connected, second output terminal of amplitude and phase correction circuit is connected with the second input end of phase detector, the output terminal of phase detector is connected with the second input end of pulse processing circuit (2), 3rd output terminal of amplitude and phase correction circuit respectively with the first squelch and 6dB testing circuit, the first input end of RSLS circuit, the four-input terminal of pulse processing circuit (2) is connected, 4th output terminal of amplitude and phase correction circuit respectively with the second squelch and 6dB testing circuit, second input end of RSLS circuit, 6th input end of pulse processing circuit (2) is connected, 5th output terminal of amplitude and phase correction circuit respectively with the 3rd squelch and 6dB testing circuit, 3rd input end of RSLS circuit, 8th input end of pulse processing circuit (2) is connected, first, two, the output terminal of three squelch and 6dB testing circuit respectively with the 3rd of pulse processing circuit (2), five, nine input ends are connected, the output terminal of described RSLS circuit is connected with the 7th input end of pulse processing circuit (2).
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104330774A (en) * | 2014-11-15 | 2015-02-04 | 安徽四创电子股份有限公司 | FPGA (Field Programmable Gate Array)-based S-mode secondary radar decoder and testing and error correction method thereof |
| CN104977572A (en) * | 2015-06-27 | 2015-10-14 | 安徽四创电子股份有限公司 | Multi-functional S-mode secondary radar test bench and test method thereof |
| CN109270520A (en) * | 2018-10-18 | 2019-01-25 | 四川九洲空管科技有限责任公司 | The processing method of secondary radar response target identities code is obtained based on amplitude information |
| CN112763983A (en) * | 2020-12-25 | 2021-05-07 | 四川九洲空管科技有限责任公司 | Pairing device for secondary radar channel signals |
-
2014
- 2014-11-15 CN CN201420682250.3U patent/CN204177961U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104330774A (en) * | 2014-11-15 | 2015-02-04 | 安徽四创电子股份有限公司 | FPGA (Field Programmable Gate Array)-based S-mode secondary radar decoder and testing and error correction method thereof |
| CN104330774B (en) * | 2014-11-15 | 2017-01-25 | 安徽四创电子股份有限公司 | FPGA (Field Programmable Gate Array)-based S-mode secondary radar decoder |
| CN104977572A (en) * | 2015-06-27 | 2015-10-14 | 安徽四创电子股份有限公司 | Multi-functional S-mode secondary radar test bench and test method thereof |
| CN109270520A (en) * | 2018-10-18 | 2019-01-25 | 四川九洲空管科技有限责任公司 | The processing method of secondary radar response target identities code is obtained based on amplitude information |
| CN112763983A (en) * | 2020-12-25 | 2021-05-07 | 四川九洲空管科技有限责任公司 | Pairing device for secondary radar channel signals |
| CN112763983B (en) * | 2020-12-25 | 2022-04-26 | 四川九洲空管科技有限责任公司 | Pairing device for secondary radar channel signals |
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