CN204168006U - A kind of hardware structure of the power automatic device based on LVDS switching system - Google Patents
A kind of hardware structure of the power automatic device based on LVDS switching system Download PDFInfo
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- CN204168006U CN204168006U CN201420627295.0U CN201420627295U CN204168006U CN 204168006 U CN204168006 U CN 204168006U CN 201420627295 U CN201420627295 U CN 201420627295U CN 204168006 U CN204168006 U CN 204168006U
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Abstract
The utility model discloses a kind of hardware structure of the power automatic device based on LVDS switching system, comprise CPU board and multiple chip card plate, coupled by bus board between chip card plate and CPU board, CPU board is used for the logic control of power monitoring and processes chip card plate data; CPU board and at least part of chip card plate comprise FPGA, and each FPGA has all general LVDS interface of different intelligent card, and described chip card plate end and described CPU board end group carry out exchanges data in bus board by the LVDS interface at two ends; Based on general LVDS interface, different chip card plates can be configured according to user's request.Based on hardware structure of the present utility model, when power automatic device uses, user changes the chip card plate of difference in functionality, chip card plate event notice will be changed to CPU by human-computer interaction interface, because the LVDS interface of exchanges data is general, economize complicated Interface design, add flexibility and the versatility of use, and ensure that system real time.
Description
Technical field
The utility model relates to power automation, particularly relates to a kind of hardware structure of the power automatic device based on LVDS switching system.
Background technology
The intelligent substation of China is the digital transformer substation based on IEC61850 standard working-out, and it requires that power automatic device and internal plug plate thereof have stronger interchangeability.The networking mode that each transformer station is different, and the difference of electrical wiring mode in the station that causes of various economic and technological factor, require the power automatic device realizing identical core controlling functions possess multiple can select electrically and communication interface.Such as: DI/DO (output of data input/data) both by traditional weak-current cable, also can pass through IEC61850-Goose communication message, and carry out monitoring and controlling; Namely various AC/DC analog quantity can pass through cable, also can be obtained by IEC61850-SMV communication message.
Due to Intelligent transformer station electrical secondary system (electrical secondary system: to be controlled by relaying protection, safety automation, system that system communication, dispatching automation, DCS automatic control system etc. form; realize contacting of people and primary system to monitor, control; run with making primary system energy safety economy) variation; and consider IEC61850 standard still in constantly changing; propose a kind ofly to meet power automatic device requirement and the cheap hardware designs framework of implementation cost, there is very high value.
The exemplary hardware framework of the automation equipment of current intelligent substation as shown in Figure 1, together with core inserter plate (i.e. CPU board) and other feature card plate are coupled in by bus board 100 ', other feature card plate described comprises conventional inserts plate and chip card plate, on bus board 100 ', there is multiple slot, described CPU board, chip card plate and conventional inserts plate are inserted in slot one by one, realize exchanges data by bus board, thus form a set of power automatic device: various power monitoring logic and core data handling process are realized by CPU board.Described conventional inserts plate refers to the feature board being mainly used in various strong and weak electricity function and having transformed, the connection of itself and CPU board is realized by fixing line, so relative position is generally fixing, namely the conventional inserts plate of difference in functionality can only be inserted in corresponding slot, changes slot and cannot realize causing the function of this conventional inserts plate; Described chip card plate requires to be configured according to the intelligent functions of power automatic device, and the exchanges data of itself and described CPU board needs by specific communication interface, so position can change.But existing power automatic device internal plug plate connected mode exists some shortcomings: 1) RS485 or RS422 bus connects, this kind connects employing polling mechanism, and exchanges data rate is low; Any plate contact fault can cause entire system to be collapsed; 2) fieldbus such as canbus connects, and data bandwidth 100kbps ~ number Mbps, cannot meet the requirement of digital transformer substation data transfer bandwidth; And due to shared bus bandwidth, the transfer of data of more than 90% needs to adopt polling mode; 3) self-defining secondary bus---by hardware buffer and register logical chip, cpu bus is extended to bus board: immunity to interference is low; Be only suitable for the application operating mode that the data volumes such as DI, DO are lower; 4) SPI is adopted to connect: immunity to interference is low; Adopt polling mode, and have strict demand to the response speed of each function plate.
Summary of the invention
Main purpose of the present utility model is the hardware structure proposing a kind of power automatic device based on LVDS switching system, to solve the use limitation problem caused because chip card plate and the interface communicated between CPU board are not general that existing hardware structure exists.
The technical solution of the utility model is as follows:
A kind of hardware structure of the power automatic device based on LVDS switching system, comprise CPU board and multiple chip card plate, coupled by bus board between described chip card plate and described CPU board, described CPU board is used for the logic control of power monitoring and processes the data of described chip card plate; Described CPU board and at least part of described chip card plate have included FPGA, each FPGA has all general LVDS interface of different intelligent card, described chip card plate end and described CPU board end group, in described bus board, dock to form data exchange channel by described LVDS interface mutually.The hardware structure that this programme provides, can configure different chip card plates according to user's request, the interface carrying out exchanges data between chip card plate and CPU board is general, and completely by FPGA hardware implementing.Thus, when CPU board conducts interviews to chip card plate, the data of the functional module of chip card plate are by the LVDS interface on chip card plate, the LVDS interface in CPU board is arrived through bus board, be transferred to CPU again, this kind of access is transparent, namely directly access, the direct-connected function plate traditional with access is distinguished without operating, without the need to considering the implementation procedure of communication, thus bring following advantage: in power automatic device use procedure, when user changes the chip card plate of difference in functionality, chip card plate event notice will be changed to CPU by human-computer interaction interface, because the LVDS interface of exchanges data is general, without the need to carrying out redefining of interface, economize complicated Interface design, add flexibility and the versatility of use, and ensure that system real time.
Preferably, also comprise multiple conventional inserts plate, be coupled to described CPU board by described bus board, for completing strong and weak electricity conversion and/or signal conversion.
Preferably, also comprise power panel, be coupled to described bus board, provide power supply to described CPU board, described chip card plate and described conventional inserts plate by described bus board.
Preferably, described LVDS interface adopts full-duplex communication, and described LVDS interface comprises LVDS transceiver, and described LVDS transceiver has receiving terminal and transmitting terminal simultaneously.
Preferably, build-out resistor is parallel with to avoid signal reflex between the differential lines of described receiving terminal.
Preferably, described build-out resistor is 100 ohm.
To sum up, the hardware structure of the power automatic device based on LVDS switching system that the utility model provides, by all designing FPGA in CPU board and chip card plate (i.e. the two ends of transfer of data), the general-purpose interface of exchanges data between CPU board and each chip card plate is realized by the LVDS Interface design of FPGA, in hardware link, CPU board and chip card plate carry out data interaction and are through CPU module in CPU board, fpga chip, again to the fpga chip on chip card plate, functional module, namely be the LVDS interface by FPGA between CPU board and chip card plate, and be that communication bridge carries out exchanges data with bus board, therefore compared to existing technology, at least there is following beneficial effect: after achieving general LVDS interface by this programme, CPU end and chip card plate end all have general LVDS interface, the LVDS interface communication at two ends is transparent for CPU, then without the need to going the specific implementation process paying close attention to LVDS communication, namely the general LVDS interface designed based on FPGA does not affect data exchange process, do not increase data processing link, the more important thing is, the position of chip card plate on bus board can arbitrarily be changed but does not affect use, the replacing of chip card plate is without the need to carrying out defining again of interface, really achieve " a bite is multiplex ".
Separately, adopt the card connected mode based on LVDS Fabric Interface, have the following advantages:
1) the transmission data bandwidth of master control plug-in unit and feature card is met: the wall of Intelligent transformer station and process layer networking adopt 100Mbps fiber optic Ethernet, wherein the highest with the occupied bandwidth of analog quantity message SMV, in order to ensure the real-time of Ethernet, on-the-spot application bandwidth all controls within 20%.Consider the reliability of device and the independence of each functional module, the Ethernet interface number of every block plug-in unit is within the scope of 4 ~ 6, and therefore data bandwidth is within the scope of 200Mbps.And LVDS is at 19 inch standard cabinets, as long as PCB meets the isometric cabling requirement of simple difference, the transmission bandwidth of more than 400Mbps can be reached.
2) differential signal transmission antijamming capability is strong: the bus board of Automation of Electric Systems device inevitably exists various alternating current-direct current analog signal, LVDS differential signal has stronger antijamming capability relative to SPI, PCI etc. based on the bus of DC level signal, makes device more easily meet the electromagnetic compatibility immunity index of power industry.
3) particular/special requirement be there is no to bus board connector: the bus board of power automatic device generally adopts welded type DIN connector, for the power equipment enterprise produced based on multiple types small batch, can drop into and other production cost by ACU, and to be proven the analog signal transmission larger to loop current be favourable.For current relatively ripe RapidIO system, it is because transmission rate is up to 2.5Gbps, it all has high requirements in bus board design, connector type selecting and cold-press process, and assessment and checking are also needed, so and be not suitable for power equipment manufacturing to the transmission impact of analog quantity.
Accompanying drawing explanation
Fig. 1 is the exemplary hardware Organization Chart of existing power automatic device;
Fig. 2 is the hardware structure figure of a kind of power automatic device based on LVDS switching system that the utility model specific embodiment provides;
Fig. 3 is the hardware designs figure of LVDS in the hardware structure of Fig. 2;
Fig. 4 is a kind of LVDS interface hardware circuitry figure of full duplex.
Embodiment
Below contrast accompanying drawing and combine preferred embodiment the utility model is described in further detail.
The hardware structure of a kind of power automatic device based on LVDS switching system that specific embodiment of the utility model provides, for carrying out the Automated condtrol of electric power system in Intelligent transformer station.As shown in Figure 2, described hardware structure comprises CPU board 200 and multiple chip card plate 300,400,500 etc., also can comprise conventional inserts plate (not shown in Fig. 2), described chip card plate (the chip card plate 300,400,500 etc. as in Fig. 2) and as described in coupled by bus board 100 between CPU board 200, described CPU board 200 is for the logic control of power monitoring and process the data of each described chip card plate, each described conventional inserts plate, described CPU board 200 and at least part of described chip card plate are provided with a FPGA (Field-Programmable Gate Array separately, field programmable gate array) chip, each FPGA has all general LVDS (the Low-Voltage Differential Signaling of different intelligent card, low-voltage differential signal) interface, when each described chip card plate and CPU board 200 carry out data interaction, data arrive CPU board 200 through fpga chip by the bus of LVDS interface through bus board 100 of this fpga chip from the functional module of chip card plate, LVDS interface through the fpga chip of CPU board 200 is transferred to CPU, transmitting data from CPU to chip card plate is then the backward of aforementioned transmission.Described chip card plate end and described CPU board end group, in described bus board, carry out exchanges data by the described LVDS interface of two ends (i.e. CPU board end and chip card plate end); Based on general LVDS interface, different chip card plates can be configured according to user's request.
For Fig. 2: be provided with a fpga chip 202 in CPU board 200, the CPU module 201 of CPU board 200 is made to carry out data interaction by fpga chip 202 and other feature card plates; Chip card plate 300,400,500 etc. is also respectively equipped with a fpga chip, for chip card plate 300, between the functional module (such as, having the functional module 301 of function 1) of chip card plate 300 and CPU board 200, data interaction also will pass through fpga chip 302.On the fpga chip 202,302 at two ends, all have LVDS interface, the hardware designs of LVDS interface as shown in Figure 3, because the hardware designs of each LVDS interface is substantially identical, is therefore described for fpga chip 302 below:
As shown in Figure 3, fpga chip 302 has LVDS transceiver, for full-duplex communication, LVDS transceiver comprises receiving interface 3021 and transmission interface 3022, and receiving interface 3021 and transmission interface 3022 are all such as communicate with CPU board, then receiving interface 3021 is coupled to the transmitting terminal 202a of the fpga chip 202 of CPU board 200, and transmission interface 3022 is then coupled to the receiving terminal 202b of fpga chip 202.When CPU module 201 accesses chip card plate 300, the functional module of chip card plate 300, the data of such as functional module 301 pass through the transmission interface 3022 of fpga chip 302 with Low Voltage Differential Signal txout+, txout-is sent by the bus on bus board 100, Low Voltage Differential Signal rxin+ is received at the receiving terminal 202b of the fpga chip 202 of CPU board, rxin-, fpga chip 202 again by signal transmission to CPU module 201, in order to avoid the signal reflex at Received signal strength place, build-out resistor R in parallel between two differential signal lines at receiving terminal 202b place, the value of R can be set to 100 ohm, also can be other resistances, this build-out resistor is determined as the case may be with the characteristic impedance on transmission line, as long as avoid receiving end signal to reflect the design of object all in protection range of the present utility model by arranging build-out resistor to reach.And if CPU board 200 transmits data to chip card plate 300, then data export Low Voltage Differential Signal txout+, txout-from CPU module 201 through the transmitting terminal 202a of fpga chip 202, sent by the bus on bus board 200, Low Voltage Differential Signal rxin+, rxin-is received at receiving interface 3021 place of the fpga chip 302 of chip card plate 300, fpga chip 302 again by signal transmission to functional module 301 etc., equally, between two differential signal lines at receiving interface 3021 place, be also parallel with build-out resistor R, be correspondingly set to 100 ohm.
The hardware circuit of the LVDS interface shown in Fig. 3 can be as shown in Figure 4, what show in Fig. 4 is that each FPGA has two groups of receptions and two groups of transmissions simultaneously, in figure, Tx_P is equivalent to aforesaid txout+, Tx_N is equivalent to aforesaid txout-, Rx_P is equivalent to aforesaid rxin+, Rx_N and is equivalent to aforesaid rxin-.Utilize the LVDS interface of FPGA to transmit, its transmission rate can reach 640Mbit/s, full-duplex communication.Certainly, also can be half-duplex operation; The form of transfer of data can be parallel or serial.As shown in Figure 3, be provided with characteristic impedance R1 ~ R4 (resistance 50 ohm) on the transmission line, in actual hardware equipment, be the copper cash on pcb board.Therefore, be provided with aforesaid build-out resistor R, reach impedance matching effect.
Based on the aforementioned hardware structure provided, in the use procedure of power automatic device, user can be different according to actual user demand flexible configuration chip card plate, such as: user is for being replaced by the chip card plate of network interface expanded function by the existing chip card plate possessing video display function, only the chip card plate that video shows need be extracted, then the chip card plate of network interface expansion is inserted, again at the man-machine interaction end of power automatic device, the notice corresponding slot place of CPU has been replaced by the chip card plate of network interface expansion, so, data interaction can be carried out between the chip card plate of network interface expansion and CPU board.If desired increase new chip card plate, the bus on bus board can be expanded, increase new slot, as long as be also designed with FPGA on new chip card plate, design LVDS interface as shown in Figure 3 and Figure 4 simultaneously.
In the aforementioned hardware structure provided, by power panel and bus board being coupled, then by the power supply requirement of bus board according to each plate, can provide power supply, power panel provides corresponding power supply can to CPU board, chip card plate and conventional inserts plate.Such as: the power outlet of power panel is connected to bus board, on bus board, according to the voltage requirements of each module to be powered, corresponding voltage transformation module is set, thus provides power supply respectively.
Above content is in conjunction with concrete preferred implementation further detailed description of the utility model, can not assert that concrete enforcement of the present utility model is confined to these explanations.For the utility model person of ordinary skill in the field; without departing from the concept of the premise utility; some equivalent to substitute or obvious modification can also be made, and performance or purposes identical, all should be considered as belonging to protection range of the present utility model.
Claims (6)
1. the hardware structure based on the power automatic device of LVDS switching system, comprise CPU board and multiple chip card plate, it is characterized in that: coupled by bus board between described chip card plate and described CPU board, described CPU board is used for the logic control of power monitoring and processes the data of described chip card plate; Described CPU board and at least part of described chip card plate include FPGA, each FPGA has all general LVDS interface of different intelligent card, described chip card plate and described CPU board, based on described bus board, dock to form data exchange channel by described LVDS interface mutually.
2. hardware structure as claimed in claim 1, is characterized in that: also comprise multiple conventional inserts plate, be coupled to described CPU board by described bus board, for completing strong and weak electricity conversion and/or signal conversion.
3. hardware structure as claimed in claim 2, is characterized in that: also comprise power panel, is coupled to described bus board, provide power supply to described CPU board, described chip card plate and described conventional inserts plate by described bus board.
4. hardware structure as claimed in claim 3, is characterized in that: described LVDS interface adopts full-duplex communication, and described LVDS interface comprises LVDS transceiver, and described LVDS transceiver has receiving terminal and transmitting terminal simultaneously.
5. hardware structure as claimed in claim 4, is characterized in that: be parallel with build-out resistor between the differential lines of described receiving terminal to avoid signal reflex.
6. hardware structure as claimed in claim 5, is characterized in that: described build-out resistor is 100 ohm.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109240960A (en) * | 2018-10-26 | 2019-01-18 | 天津光电通信技术有限公司 | A kind of power board circuit and its implementation based on VPX framework |
| CN113726009A (en) * | 2021-08-27 | 2021-11-30 | 中国南方电网有限责任公司超高压输电公司柳州局 | Intelligent monitoring system of intelligent substation |
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2014
- 2014-10-24 CN CN201420627295.0U patent/CN204168006U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109240960A (en) * | 2018-10-26 | 2019-01-18 | 天津光电通信技术有限公司 | A kind of power board circuit and its implementation based on VPX framework |
| CN109240960B (en) * | 2018-10-26 | 2023-11-24 | 天津光电通信技术有限公司 | Exchange board circuit based on VPX architecture and implementation method thereof |
| CN113726009A (en) * | 2021-08-27 | 2021-11-30 | 中国南方电网有限责任公司超高压输电公司柳州局 | Intelligent monitoring system of intelligent substation |
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