CN204166875U - Liquid crystal panel time-sequence control module - Google Patents
Liquid crystal panel time-sequence control module Download PDFInfo
- Publication number
- CN204166875U CN204166875U CN201420652025.5U CN201420652025U CN204166875U CN 204166875 U CN204166875 U CN 204166875U CN 201420652025 U CN201420652025 U CN 201420652025U CN 204166875 U CN204166875 U CN 204166875U
- Authority
- CN
- China
- Prior art keywords
- liquid crystal
- crystal panel
- voltage
- control module
- sequence control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The utility model relates to a kind of control module, particularly a kind of for driving the liquid crystal panel time-sequence control module of liquid crystal sequential control; Its input interface, power circuit, fpga chip and N number of FPC connector form; The utility model adopts FPGA as the design proposal of main control chip, and dirigibility is very high, can compatible different manufacturers very flexibly, different process, the liquid crystal panel of different size, has extraordinary versatility, and the R&D cycle is short, drop into little, the advantages such as production controllability is good, and risk is low.Can substitute most liquid crystal time-sequence control module on the market drives liquid crystal panel normally to work.
Description
Technical field
The utility model relates to a kind of control module, particularly a kind of for driving the liquid crystal panel time-sequence control module of liquid crystal sequential control.
Background technology
Traditional liquid crystal time-sequence control module often adopts ASIC as main control chip, design for a kind of liquid crystal panel, very flexible, be difficult at different manufacturers, different process, general on the liquid crystal panel of different size, if and when carrying out targeted design, there is again the R&D cycle long, have high input, the problem that risk is high.Meanwhile, LCD Interface agreement is numerous, and scan mode is also different, adopts ASIC to be difficult to compatible numerous interface protocol flexibly.
Utility model content
Technical problem to be solved in the utility model be to provide a kind of R&D cycle short, drop into little, compatible good liquid crystal panel time-sequence control module.
For solving the problems of the technologies described above, the utility model realizes as follows: liquid crystal panel time-sequence control module described in the utility model forms by by input interface, power circuit, fpga chip and N number of FPC connector; Described input interface is electrically connected with fpga chip composition data; Fpga chip forms with power circuit and is electrically connected; Input interface forms with power circuit and is electrically connected; The output interface that N number of FPC connector is provided with is electrically connected with power circuit and fpga chip composition data respectively
Described fpga chip is also connected with DRAM storer, and is electrically connected with DRAM storer composition data; Fpga chip is provided with TDO, TDI, TMS, TCK pin and is used as jtag interface.
Described input interface, on the one hand for liquid crystal panel time-sequence control module is powered, is liquid crystal panel time-sequence control module input LVDS video data on the other hand.
The digital circuits section that described power circuit is liquid crystal panel provides magnitude of voltage to be one in 3.3V or 2.5V; For liquid crystal panel thin film field-effect pipe (TFT) grid provides cut-in voltage value to be 20V ~ 38V; For liquid crystal panel TFT grid provides closedown magnitude of voltage to be-4V ~-9V; Artificial circuit part for liquid crystal panel provides magnitude of voltage to be 13V ~ 20V; For liquid crystal panel provides 8 ~ 16 GAMMA voltages, magnitude of voltage between 0 volt to artificial circuit part magnitude of voltage with the formal distribution of GAMMA curve; For liquid crystal panel provides VCOM voltage, magnitude of voltage is 0.25 ~ 0.75 times of liquid crystal panel artificial circuit part magnitude of voltage; For liquid crystal panel provides boosting voltage.
Described power circuit provides the single-ended IO voltage of FPGA for fpga chip, and magnitude of voltage is 3.3V or 2.5V; For fpga chip provides FPGA difference IO voltage, magnitude of voltage is 0.9V ~ 3.3V; For fpga chip provides core voltage value to be 1.2V.
Described fpga chip is the one in XC6SLX4, XC6SLX9, XC3S200A, XC3S400A of EP2C5T144, EP4CE6F17, EP2C8Q208, EP3C5F256, EP3C10F256 or Xilinx company of altera corp.
Described DRAM storer is SDR SDRAM, DDR SDRAM or DDR2SDRAM.
Each output signal of liquid crystal panel time-sequence control module is connected to liquid crystal panel by FPC flat flexible line by described FPC connector, and FPC connector output signal comprises differential data signals, row-field scanning signal, liquid crystal panel digital voltage, liquid crystal panel analog voltage, liquid crystal panel VGH voltage, liquid crystal panel GAMMA voltage, liquid crystal panel VGL voltage, liquid crystal panel VCOM voltage and boosting voltage.
Described fpga chip is made up of LVDS decoder module, scanning sequency control module, scanner uni data outputting module, dram controller module; LVDS decoder module and scanning sequency control module, scanner uni data outputting module respectively composition data are electrically connected; Scanning sequency control module is electrically connected with scanner uni data outputting module composition data; Scanning sequency control module is electrically connected with dram controller module composition data; LVDS decoder module is provided with LVDS input signal pin; Scanner uni data outputting module is provided with differential data signals output pin and row-field scanning signal output pin; Dram controller module is provided with DRAM and controls pin.
Good effect of the present utility model is: the utility model adopts FPGA as the design proposal of main control chip, dirigibility is very high, can compatible different manufacturers very flexibly, different process, the liquid crystal panel of different size, has extraordinary versatility, and the R&D cycle is short, drop into little, the advantages such as production controllability is good, and risk is low.Can substitute most liquid crystal time-sequence control module on the market drives liquid crystal panel normally to work.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, not paying under the laborious prerequisite of creation, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the utility model structural representation
Fig. 2 is the utility model application structure schematic diagram
Fig. 3 is the utility model application structure schematic diagram
Fig. 4 is the utility model fpga chip structural representation
1 input interface 2 power circuit 3FPGA chip in figure
4 output signal interface 5DRAM storer 6FPC connectors
31LVDS decoder module 32 scanning sequency control module
33 scanner uni data outputting module 34DRAM controller modules
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearly understand, below in conjunction with embodiment and accompanying drawing, the utility model is described in further details.At this, exemplary embodiment of the present utility model and illustrating for explaining the utility model, but not as to restriction of the present utility model.
Liquid crystal panel time-sequence control module described in the utility model is made up of input interface 1, power circuit 2, fpga chip 3 and N number of FPC connector 6; Described input interface 1 is electrically connected with fpga chip 3 composition data; Fpga chip 3 forms with power circuit 2 and is electrically connected; Input interface 1 forms with power circuit 2 and is electrically connected; Output signal interface on N number of FPC connector 6 is electrically connected with power circuit 2 and fpga chip 3 composition data respectively
Described fpga chip 3 is also connected with DRAM storer 5, and is electrically connected with DRAM storer 5 composition data; Fpga chip 3 is provided with TDO, TDI, TMS, TCK pin and is used as jtag interface.
Described input interface 1 one aspect is that liquid crystal panel time-sequence control module is powered, and is liquid crystal panel time-sequence control module input LVDS video data on the other hand.
The digital circuits section that described power circuit 2 is liquid crystal panel provides magnitude of voltage to be one in 3.3V or 2.5V; For liquid crystal panel thin film field-effect pipe (TFT) grid provides cut-in voltage value to be 20V ~ 38V; For liquid crystal panel TFT grid provides closedown magnitude of voltage to be-4V ~-9V; Artificial circuit part for liquid crystal panel provides magnitude of voltage to be 13V ~ 20V; For liquid crystal panel provides 8 ~ 16 GAMMA voltages, magnitude of voltage between 0 volt to artificial circuit part magnitude of voltage with the formal distribution of GAMMA curve; For liquid crystal panel provides VCOM voltage, magnitude of voltage is 0.25 ~ 0.75 times of liquid crystal panel artificial circuit part magnitude of voltage; For liquid crystal panel provides boosting voltage.
Described power circuit 2 provides the single-ended IO voltage of FPGA for fpga chip 3, and magnitude of voltage is 3.3V or 2.5V; For fpga chip 3 provides FPGA difference IO voltage, magnitude of voltage is 0.9V ~ 3.3V; For fpga chip provides core voltage value to be 1.2V.
Described fpga chip 3 is the one in XC6SLX4, XC6SLX9, XC3S200A, XC3S400A of EP2C5T144, EP4CE6F17, EP2C8Q208, EP3C5F256, EP3C10F256 or Xilinx company of altera corp.
Described DRAM storer 5 is SDR SDRAM, DDR SDRAM or DDR2SDRAM.
Each output signal of liquid crystal panel time-sequence control module is connected to liquid crystal panel by FPC connector 6 flat flexible line by described FPC connector 6, and FPC connector output signal comprises differential data signals, row-field scanning signal, liquid crystal panel digital voltage, liquid crystal panel analog voltage, liquid crystal panel VGH voltage, liquid crystal panel GAMMA voltage, liquid crystal panel VGL voltage, liquid crystal panel VCOM voltage and boosting voltage.
Described fpga chip 3 is made up of LVDS decoder module 31, scanning sequency control module 32, scanner uni data outputting module 33, dram controller module 34; LVDS decoder module 31 and scanning sequency control module 32, scanner uni data outputting module 33 respectively composition data are electrically connected; Scanning sequency control module 32 is electrically connected with scanner uni data outputting module 33 composition data; Scanning sequency control module 32 is electrically connected with dram controller module 34 composition data; LVDS decoder module 31 is provided with LVDS input signal pin; Scanner uni data outputting module 33 is provided with differential data signals output pin and row-field scanning signal output pin; Dram controller module 34 is provided with DRAM and controls pin.
Embodiment one:
As shown in Figure 2, fpga chip 3 adopts the EP2C5T144C8 of altera corp, input interface 1 input signal is two groups of LVDS signals, be respectively E0+E0-~ E3+E3-and O0+O0-~ O3+O3-, the former is for inputting the odd point of liquid crystal panel, the latter is for inputting the even number point of liquid crystal panel, EC+EC-and OC+OC-is respectively the clock signal of two groups of LVDS signals.TDO, TDI, TMS, the TCK at input interface 1 place are the jtag interfaces of fpga chip 3, for debugging and downloading.Output signal interface 4 place output signal in this example and have AB two groups of differential data signals and CTRL0 ~ CTRL4 five panel scan signals.It is 6 right for often organizing differential signal, and namely A0+A0-~ A5+A5-and B0+B0-~ B5+B5-, AC+AC-and BC+BC-are respectively the clock signal of two groups of differential signals.Differential data signals, panel scan signal are connected with liquid crystal panel by the FPC connector 6 of a 80P with liquid crystal panel each road operating voltage.
Example 2
As shown in Figure 3, fpga chip 3 adopts the EP4CE6F17C8 of altera corp, input signal is equally also two groups of LVDS signals, be respectively E0+E0-~ E3+E3-and O0+O0-~ O3+O3-, the former is for inputting the odd point of liquid crystal panel, the latter is for inputting the even number point of liquid crystal panel, EC+EC-and OC+OC-is respectively the clock signal of two groups of LVDS signals.TDO, TDI, TMS, the TCK at input interface 1 place are the jtag interfaces of fpga chip, for debugging and downloading.This example output interface 4 output signal has ABCD tetra-groups of differential data signals and CTRL0 ~ CTRL4 five panel scan signals.It is 6 right for often organizing differential signal, and namely A0+A0-~ A5+A5-, B0+B0-~ B5+B5-, C0+C0-~ C5+C5-and D0+D0-~ D5+D5-, AC+AC-, BC+BC-, CC+CC-and DC+DC-are respectively the clock signal of two groups of differential signals.Differential data signals, panel scan signal are connected with liquid crystal panel by the FPC connector 6 of two 80P with liquid crystal panel each road operating voltage.Also comprise the DRAM storer 5 of two panels 2MX32bit in this example, model is MT48LC2M32B2P.The effect of DRAM storer 5 is got off by the whole buffer memory of field picture data, and then send according to the scanning sequency of liquid crystal panel.
Except the way of realization described by example 1 and example 2, this programme also has other implementation a variety of.
Input interface 1 part, for the liquid crystal panel of low resolution, only needs one group of LVDS signal, and for the liquid crystal panel of more high resolving power or higher refresh rate, then needs four groups of LVDS signals.If input data are 18 looks, then one group of LVDS signal is three pairs of signal wires, if input data are 24 looks, then one group of LVDS signal is four pairs of signal wires, if input data are 30 looks, then one group of LVDS signal is five pairs of signal wires.
Fpga chip 3 part, except the EP4CE6F17C8 used in the EP2C5T144C8 used in example 1 and example 2, also have chip much of the same type can complete identical function, as EP2C8Q208C8, EP3C5F256C8, EP3C10F256C8 of altera corp, XC6SLX4, XC6SLX9, XC3S200A, XC3S400A etc. of Xilinx company.Except altera corp and Xilinx company, also have some companies to produce fpga chip as Lattic company and Actel company, the fpga chip that they produce also can complete the function described by this programme.
FPC connector 6 part, because the size of liquid crystal panel is different with structure, the signal of FPC connector 6 also has a great difference.For the liquid crystal panel of some low resolution, one group of differential data signals only needs 3, for some liquid crystal panels with clock recovery circuitry, does not need to provide clock signal, and some differentiates the liquid crystal panel of superelevation, then need nearly 8 groups of differential data signals.
DRAM storer 5 part, many times, the DRAM storer 5 in this programme is omissible, as shown in example 1.The DRAM used in example 2 is SDRSDRAM, and speed is faster, and the DDR SDRAM that cost is lower and DDR2 SDRAM all can complete identical function.
Claims (9)
1. a liquid crystal panel time-sequence control module, is characterized in that: be made up of input interface (1), power circuit (2), fpga chip (3) and N number of FPC connector (6); Described input interface (1) is electrically connected with fpga chip (3) composition data; Fpga chip (3) forms with power circuit (2) and is electrically connected; Input interface (1) forms with power circuit (2) and is electrically connected; Output signal interface on N number of FPC connector (6) is electrically connected with power circuit (2) and fpga chip (3) composition data respectively.
2. a kind of liquid crystal panel time-sequence control module according to claim 1, is characterized in that: described fpga chip (3) is also connected with DRAM storer (5), and is electrically connected with DRAM storer (5) composition data; Fpga chip (3) is provided with TDO, TDI, TMS, TCK pin and is used as jtag interface.
3. a kind of liquid crystal panel time-sequence control module according to claim 1, it is characterized in that: described input interface (1), on the one hand for liquid crystal panel time-sequence control module is powered, is liquid crystal panel time-sequence control module input LVDS video data on the other hand.
4. a kind of liquid crystal panel time-sequence control module according to claim 1, is characterized in that: the digital circuits section that described power circuit (2) is liquid crystal panel provides magnitude of voltage to be one in 3.3V or 2.5V; For liquid crystal panel thin film field-effect pipe (TFT) grid provides cut-in voltage value to be 20V ~ 38V; For liquid crystal panel TFT grid provides closedown magnitude of voltage to be-4V ~-9V; Artificial circuit part for liquid crystal panel provides magnitude of voltage to be 13V ~ 20V; For liquid crystal panel provides 8 ~ 16 GAMMA voltages, magnitude of voltage between 0 volt to artificial circuit part magnitude of voltage with the formal distribution of GAMMA curve; For liquid crystal panel provides VCOM voltage, magnitude of voltage is 0.25 ~ 0.75 times of liquid crystal panel artificial circuit part magnitude of voltage; For liquid crystal panel provides boosting voltage.
5. a kind of liquid crystal panel time-sequence control module according to claim 1, is characterized in that: described power circuit (2) provides the single-ended IO voltage of FPGA for fpga chip (3), and magnitude of voltage is 3.3V or 2.5V; For fpga chip (3) provides FPGA difference IO voltage, magnitude of voltage is 0.9V ~ 3.3V; For fpga chip provides core voltage value to be 1.2V.
6. a kind of liquid crystal panel time-sequence control module according to claim 1, is characterized in that: the one in XC6SLX4, XC6SLX9, XC3S200A, the XC3S400A of EP2C5T144, EP4CE6F17, EP2C8Q208, EP3C5F256, EP3C10F256 or Xilinx company that described fpga chip (3) is altera corp.
7. a kind of liquid crystal panel time-sequence control module according to claim 2, is characterized in that: described DRAM storer (5) is SDR SDRAM, DDR SDRAM or DDR2 SDRAM.
8. a kind of liquid crystal panel time-sequence control module according to claim 1, it is characterized in that: each output signal of liquid crystal panel time-sequence control module is connected to liquid crystal panel by FPC connector (6) flat flexible line by described FPC connector (6), FPC connector output signal comprises differential data signals, row-field scanning signal, liquid crystal panel digital voltage, liquid crystal panel analog voltage, liquid crystal panel VGH voltage, liquid crystal panel GAMMA voltage, liquid crystal panel VGL voltage, liquid crystal panel VCOM voltage and boosting voltage.
9. a kind of liquid crystal panel time-sequence control module according to claim 1, is characterized in that: described fpga chip (3) is made up of LVDS decoder module (31), scanning sequency control module (32), scanner uni data outputting module (33), dram controller module (34); LVDS decoder module (31) and scanning sequency control module (32), scanner uni data outputting module (33) respectively composition data are electrically connected; Scanning sequency control module (32) is electrically connected with scanner uni data outputting module (33) composition data; Scanning sequency control module (32) is electrically connected with dram controller module (34) composition data; LVDS decoder module (31) is provided with LVDS input signal pin; Scanner uni data outputting module (33) is provided with differential data signals output pin and row-field scanning signal output pin; Dram controller module (34) is provided with DRAM and controls pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420652025.5U CN204166875U (en) | 2014-02-27 | 2014-11-04 | Liquid crystal panel time-sequence control module |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2014200853423 | 2014-02-27 | ||
| CN201420085342 | 2014-02-27 | ||
| CN201420652025.5U CN204166875U (en) | 2014-02-27 | 2014-11-04 | Liquid crystal panel time-sequence control module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204166875U true CN204166875U (en) | 2015-02-18 |
Family
ID=52540540
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420652025.5U Expired - Fee Related CN204166875U (en) | 2014-02-27 | 2014-11-04 | Liquid crystal panel time-sequence control module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204166875U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103794189A (en) * | 2014-02-27 | 2014-05-14 | 刘兴宾 | Liquid crystal display panel sequential control module |
| CN113593498A (en) * | 2021-07-30 | 2021-11-02 | 惠科股份有限公司 | Programmable module, time sequence control chip and display device |
-
2014
- 2014-11-04 CN CN201420652025.5U patent/CN204166875U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103794189A (en) * | 2014-02-27 | 2014-05-14 | 刘兴宾 | Liquid crystal display panel sequential control module |
| CN113593498A (en) * | 2021-07-30 | 2021-11-02 | 惠科股份有限公司 | Programmable module, time sequence control chip and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103680636B (en) | Shift register cell, gate driver circuit and display device | |
| CN109949749A (en) | Shift register, gate driving circuit, display device and grid drive method | |
| CN102456335B (en) | Liquid crystal display device and driving method of the same | |
| CN104517575A (en) | Shifting register and level-transmission gate drive circuit | |
| CN105206238B (en) | The display device of gate driving circuit and the application circuit | |
| CN105405381B (en) | Shift register and its driving method, drive circuit and array base palte | |
| CN106782374A (en) | GOA circuits | |
| CN101976581B (en) | Shift register circuit | |
| CN103871388B (en) | Display panel, gate driver and control method | |
| CN103700354A (en) | Grid electrode driving circuit and display device | |
| CN104599657B (en) | Drive circuit, method, display panel and the display device of double grid dot structure | |
| KR102051846B1 (en) | Display driving circuit and display device having them | |
| CN106128348A (en) | Scan drive circuit | |
| CN108597470A (en) | Display device drive system and method and display device | |
| CN105931595A (en) | Shift register unit, driving method, grid drive circuit, and display device | |
| CN103971656B (en) | Display panel and gate driver | |
| CN105976751A (en) | Scan drive circuit and planar display device provided with same | |
| CN104751810A (en) | Liquid Crystal Display and Method for Driving the Same | |
| CN103745696A (en) | Gate drive circuit | |
| CN103426415A (en) | Drive circuit of liquid crystal display panel and waveform driving approach | |
| CN105161063A (en) | Grid drive circuit of liquid crystal display apparatus | |
| CN204166875U (en) | Liquid crystal panel time-sequence control module | |
| CN103794189A (en) | Liquid crystal display panel sequential control module | |
| CN104123922A (en) | Grid driving circuit and driving system and display device utilizing grid driving circuit | |
| CN103778881B (en) | A kind of data drive circuit, display device and driving method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20160608 Address after: 510000, Guangdong, Guangzhou, Panyu District Dashi international 1, 513 Patentee after: Guangzhou crystal reach Electronic Technology Co., Ltd. Address before: 510000 No. 104 Tianhe Road, Guangzhou, Guangdong, Tianhe District Patentee before: Liu Xingbin |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150218 Termination date: 20181104 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |