CN204156960U - A kind of electronic police high-definition camera with high light inhibit feature - Google Patents

A kind of electronic police high-definition camera with high light inhibit feature Download PDF

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Publication number
CN204156960U
CN204156960U CN201420686325.5U CN201420686325U CN204156960U CN 204156960 U CN204156960 U CN 204156960U CN 201420686325 U CN201420686325 U CN 201420686325U CN 204156960 U CN204156960 U CN 204156960U
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decoding chip
video decoding
signal
high light
electronic police
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CN201420686325.5U
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陈乙周
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Pengcheng, Shenzhen transportation network incorporated company
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LINRUN INDUSTRY Co Ltd
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Abstract

The utility model discloses a kind of electronic police high-definition camera with high light inhibit feature, comprise interconnective video acquisition unit and image procossing and control unit, described video acquisition unit comprises video decoding chip, be provided with output format control module and the carrier chrominance signal processing module connected successively, luminance signal processing module, separated in synchronization module, clock generating module in described video decoding chip, described video decoding chip inside is also provided with I2C bus.The utility model can input the luminance signal of standard to difference and carrier chrominance signal processes, and control in the sheet realizing brightness, colourity and saturation, the sophisticated functionss such as analog-to-digital conversion, automatic clamping, automatic growth control, clock generating, multi-modulation scheme decoding are all focused in video decoding chip, convenient debugging, also simpler in structure, also improve the reliability that video camera high light suppresses simultaneously, thus provide great convenience for Real-time Image Collecting System.

Description

A kind of electronic police high-definition camera with high light inhibit feature
Technical field
The utility model relates to field of cameras, relates in particular to a kind of electronic police high-definition camera with high light inhibit feature.
Background technology
As the video camera of electronic police, common camera is worked at night irradiation car plate, it is more difficult for taking clear and legible license plate number, except the speed of driving, automobile headlamp often forms very large interference to the video camera irradiating car plate, and the reflective function of automobile board is very high, this just requires that video camera has high light inhibit feature, otherwise the image taken can be too strong and smudgy because of light.The process for high light of existing video camera is all generally come by a few chip block, the step realizing high light inhibit feature be separated in different chip and carry out, so just make total complicated, volume is excessive, be inconvenient to debug, and also reduce the reliability of camera performance.
Utility model content
The purpose of this utility model is, for the problems referred to above, provides a kind of by within the function i ntegration of many complexity to chip piece, makes structure simple, is convenient to the electronic police high-definition camera with high light inhibit feature debugged.
For achieving the above object, the utility model adopts following technical scheme:
A kind of electronic police high-definition camera with high light inhibit feature, comprise interconnective video acquisition unit and image procossing and control unit, described video acquisition unit comprises video decoding chip, be provided with output format control module and the carrier chrominance signal processing module connected successively, luminance signal processing module, separated in synchronization module and clock generating module in described video decoding chip, described video decoding chip inside is provided with I2C bus.
Further, described video acquisition unit also comprises CCD camera, and the front end of described CCD camera is provided with double glazing, and described CCD camera obtains analog signal and inputs to described video decoding chip.
Further, described image procossing and control unit comprise FPGA, dual port RAM and DSP, described video decoding chip converts described analog signal to digital signal and exports described FPGA to, described FPGA produces the address signal of specifying and passes to described dual port RAM and store, and the signal that described DSP reads in described dual port RAM processes.
Further, a quartz oscillator is connected with between the XTAL pin of described video decoding chip and XTALI pin.
Further, described digital signal comprises field sync signal VREF, line synchronizing signal HREF, parity field signal RTS0, pixel clock signal LLC2.
Further, also LED light supplement lamp is comprised.Described LED light supplement lamp centered by CCD camera around setting.
Implement the utility model and there is following beneficial effect:
1, the luminance signal of standard can be inputted to difference and carrier chrominance signal processes, and control in the sheet realizing brightness, colourity and saturation, the sophisticated functionss such as analog-to-digital conversion, automatic clamping, automatic growth control, clock generating, multi-modulation scheme decoding are all focused in video decoding chip, convenient debugging, also simpler in structure, also improve the reliability that video camera high light suppresses simultaneously, thus provide great convenience for Real-time Image Collecting System;
2, LED light supplement lamp annular arrangement is adopted to carry out light filling, visible ray coverage is large, and environmentally can carry out the adjustment of brightness power, night is reducible color effect also, have advanced BLC function, photosensitive sensitivity is adjustable, and light is opened and closed automatically, camera lens front end adopts unique two Glass Design, produces halation and hot spot phenomenon when can effectively avoid fill-in light to open.
Accompanying drawing explanation
fig. 1 is theory diagram of the present utility model;
Fig. 2 is the functional block diagram of video decoding chip of the present utility model;
Fig. 3 is the circuit diagram of video decoding chip of the present utility model;
Fig. 4 is the partial enlarged drawing of video decoding chip of the present utility model.
In figure: 1, video acquisition unit; 2, image procossing and control unit; 3, CCD camera; 4, video decoding chip; 5, FPGA; 6, dual port RAM; 7, DSP; 8, carrier chrominance signal processing module; 9, luminance signal processing module; 10, separated in synchronization module; 11, clock generating module; 12, output format control module; 13, I2C bus.
Embodiment
Embodiment of the present utility model is described in detail below in conjunction with accompanying drawing.
A kind of electronic police high-definition camera with high light inhibit feature, as shown in Figure 1, comprise interconnective video acquisition unit 1 and image procossing and control unit 2, video acquisition unit 1 is by CCD camera 3 acquisition of image data, around circle or a multi-turn LED light supplement lamp around CCD camera 3, light sensitivity is adjustable, and camera lens front end adopts two Glass Design, produces halation and hot spot phenomenon when can effectively avoid fill-in light to open.But be all analog signal from the vision signal that the electrooptical device of CCD camera 3 obtains, analog signal being become digital signal will through mould/number (A/D) transfer process, this process completes in video decoding chip 4, and video decoding chip 4 of the present utility model adopts SAA711A.As shown in Figure 2, video processing module is provided with in video decoding chip 4, video processing module comprises again carrier chrominance signal processing module 8, luminance signal processing module 9, separated in synchronization module 10 and clock generating module 11, analog signal can be isolated field sync signal VREF, line synchronizing signal HREF, parity field signal RES0 and pixel clock signal LLC2, as shown in Figure 4, these signals are drawn all respectively from pin corresponding to SAA711A, output format control module 12 is also provided with in video decoding chip 4, convert analog signal to digital signal and export FPGA5 to, video decoding chip 4 inside is also provided with I2C bus 13, the setting of its working method is all complete in I2C bus 13.Image procossing and control unit 2 comprise FPGA5, dual port RAM 6 and DSP7, FPGA according to the digital signal that receives produce data store required for chip selection signal and read/write control signals and the address signal of specifying, the memory cell of specifying in dual port RAM 6 is stored into, for DSP7 process by collecting view data.
As shown in Figure 3, AT11 is as video input interface, the electric capacity C1 of connection 22 μ F and the resistance R2 of 47 Ω resistance R1 and 27 Ω is needed at this video input interface, a quartz oscillator is connected with between the XTAL pin of video decoding chip 4 and XTALI pin, for generation of the work clock required for system, then drive generation row locked clock LLC, LLC2 and clock reference signal CREF by external clock.The generation of clock is also subject to the impact of chip selection signal CE, and only have when CE is that high level is just effective, during low level, SAA7111A is reset, and this pin does not produce periodic signal.In addition, in order to make system works stablize, will digitally VDDD0-5 and VDDA0-2 in analog divide out, centre connects with inductance, in order to reduce the ripple interference of power supply, adding filter capacitor at the input of each power pins, and analog power and digital power have been powered respectively.
The utility model is not limited to above-mentioned embodiment; anyone can draw other various forms of products under enlightenment of the present utility model; above-mentioned embodiment is only schematic; instead of it is restrictive; those of ordinary skill in the art is under enlightenment of the present utility model; do not departing under the ambit that the utility model aim and claim protect, also can make a lot of form, these all belong within protection of the present utility model.

Claims (6)

1. an electronic police high-definition camera with high light inhibit feature, comprise interconnective video acquisition unit (1) and image procossing and control unit (2), it is characterized in that: described video acquisition unit (1) comprises video decoding chip (4), the carrier chrominance signal processing module (8) being provided with output format control module (12) in described video decoding chip (4) and connecting successively, luminance signal processing module (9), separated in synchronization module (10) and clock generating module (11), described video decoding chip (4) inside is provided with I2C bus (13).
2. a kind of electronic police high-definition camera with high light inhibit feature according to claim 1, it is characterized in that: described video acquisition unit (1) also comprises CCD camera (3), the front end of described CCD camera (3) is provided with double glazing, and described CCD camera (3) obtains analog signal and inputs to described video decoding chip (4).
3. a kind of electronic police high-definition camera with high light inhibit feature according to claim 2, it is characterized in that: described image procossing and control unit (2) comprise FPGA(5), dual port RAM (6) and DSP(7), described video decoding chip (4) converts described analog signal to digital signal and exports described FPGA(5 to), described FPGA(5) produce the address signal of specifying and pass to described dual port RAM (6) and store, described DSP(7) signal read in described dual port RAM (6) processes.
4. a kind of electronic police high-definition camera with high light inhibit feature according to claim 1, is characterized in that: be connected with a quartz oscillator between the XTAL pin of described video decoding chip (4) and XTALI pin.
5. a kind of electronic police high-definition camera with high light inhibit feature according to claim 3, is characterized in that: described digital signal comprises field sync signal VREF, line synchronizing signal HREF, parity field signal RTS0, pixel clock signal LLC2.
6. a kind of electronic police high-definition camera with high light inhibit feature according to claim 1, is characterized in that: also comprise LED light supplement lamp, described LED light supplement lamp centered by CCD camera (3) around setting.
CN201420686325.5U 2014-11-17 2014-11-17 A kind of electronic police high-definition camera with high light inhibit feature Active CN204156960U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109348133A (en) * 2018-11-20 2019-02-15 孙玉芝 A kind of safety monitoring image processing apparatus and method
CN114598836A (en) * 2022-01-11 2022-06-07 凯斯泰尔通信设备(深圳)有限公司 High-definition OSD circuit for high-definition video conference system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109348133A (en) * 2018-11-20 2019-02-15 孙玉芝 A kind of safety monitoring image processing apparatus and method
CN114598836A (en) * 2022-01-11 2022-06-07 凯斯泰尔通信设备(深圳)有限公司 High-definition OSD circuit for high-definition video conference system

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Effective date of registration: 20170929

Address after: 518000 Guangdong city of Shenzhen province Luohu District Liantang Industrial Zone 702 building 4 floor west block No. A-1

Patentee after: Pengcheng, Shenzhen transportation network incorporated company

Address before: 518000 Guangdong city of Shenzhen province Luohu District Liantang Industrial Zone 702 building 4 floor west block A-1 No. 518000

Patentee before: Linrun Industry Co., Ltd.