CN204102259U - A kind of POS terminal operating system hardware platform - Google Patents
A kind of POS terminal operating system hardware platform Download PDFInfo
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- CN204102259U CN204102259U CN201420583902.8U CN201420583902U CN204102259U CN 204102259 U CN204102259 U CN 204102259U CN 201420583902 U CN201420583902 U CN 201420583902U CN 204102259 U CN204102259 U CN 204102259U
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Abstract
The utility model discloses a kind of POS terminal operating system hardware platform, for solving the many and technical matters that travelling speed is slow of POS terminal operating system hardware platform circuit complex data line in prior art, described hardware platform comprises: for storing the storer (10) of POS terminal system program, comprise: communication interface (101,102); For carrying out a CPU (20) of safety check to this system program, comprising: data-interface (201); For running the 2nd CPU (30) of this system program at safety check by rear reading, comprising: data-interface (301); For setting up first communication channel between communication interface (101) and data-interface (201), and/or between communication interface (102) and data-interface (301), set up the on-off controller (40) of second communication channel.
Description
Technical field
The utility model relates to POS terminal technical field, particularly relates to a kind of POS terminal operating system hardware platform.
Background technology
Point-of-sale infosystem (POS, Point Of Sales), i.e. POS system, refer to and directly read merchandise sales information (as trade name, unit price, sales volume, selling time, sales outlet, purchase client etc.) by automatic fetch equipment (as cashier's machine) when merchandising, and be sent to relevant department by communication network and computer system and carry out analyzing processing with the system improving operational efficiency.POS terminal is a kind of multi-functional terminal end, the holder's magnetic strip information on bank card is read by card reader, by POS terminal, operating personnel input dealing money, holder inputs personally identifiable information's (i.e. password), POS terminal is these information by Unionpay center, and Shang Song issuing bank system, completes on-line transaction, provide the information of success or not, and print corresponding bill.
POS terminal system comprises the operating system that can realize various application function and the hardware platform that can carry this operating system, early stage POS terminal function singleness (namely POS terminal operating system is more succinct), POS terminal hardware platform adopts the CPU that performance is lower; Along with the fast development of infotech, arise at the historic moment and can provide the intelligent operating systems such as android, win-mobile of good interactive experience for user, these intelligent operating systems are applied in POS terminal, need the hardware platform that a set of powerful is set in POS terminal to carry intelligent operating system.Again because POS terminal is generally used for financial payment field, the security of POS terminal operating system is most important.POS terminal operating system hardware platform run in the process of the intelligent operating systems such as android, win-mobile, in order to realize high-performance and the high security of POS terminal system, in current POS terminal operating system hardware platform, adopt high-performance CPU (being configured with the non-different mistake flash memories NANDFLASH for storage system working procedure) and safe CPU cooperating; Concrete, according to the safety requirements of financial payment systems, the working procedure in NANDFLASH must accept the verification certification of safe CPU, and namely safe CPU needs to establish a communications link with NANDFLASH.But usual safe CPU is not with NANDFLASH interface.For this problem solution of the prior art be: between safe CPU and NANDFLASH, change-over circuit is set, the serial data that safe CPU exports is converted to parallel data and sends in NANDFLASH, or the parallel data that NANDFLASH exports is converted to serial data and sends in safe CPU, to realize communication therebetween.
But this change-over circuit complex data line is many, adds circuit design cost; Further, the speed that safe CPU reads data in NANDFLASH by change-over circuit is very slow, causes working procedure checking time long, can have a strong impact on the speed of POS terminal start.That is, there is the many and technical matters that travelling speed is slow of POS terminal operating system hardware platform circuit complex data line in prior art.
Utility model content
The embodiment of the present application is by providing a kind of POS terminal operating system hardware platform, solve the many and technical matters that travelling speed is slow of POS terminal operating system hardware platform circuit complex data line in prior art, achieve the technique effect simplifying POS terminal operating system hardware platform circuit, improve travelling speed.
The embodiment of the present application provides a kind of POS terminal operating system hardware platform, comprising:
For storing the storer of the system program making POS terminal work run, described storer comprises: the first communication interface and second communication interface;
For carrying out a CPU of safety check to described system program, a described CPU comprises: the first data-interface;
For running the 2nd CPU of described system program at described safety check by rear reading, described 2nd CPU comprises: the second data-interface;
For setting up first communication channel between described first communication interface and described first data-interface, and/or set up the on-off controller of second communication channel between described second communication interface and described second data-interface; Wherein, a described CPU carries out safety check based on described first communication channel to described system program, and described 2nd CPU reads based on described second communication channel and runs described system program after described safety check passes through.
Optionally, described on-off controller comprises: the first control interface, the second control interface and data output interface;
Wherein, described first data-interface is connected with described first control interface; Described second data-interface is connected with described second control interface; Described data output interface is connected with described first communication interface and/or described second communication interface; Described data output interface can export the input data of described first control interface and/or described second control interface.
Optionally, a described CPU also comprises the 3rd data-interface; Described on-off controller also comprises the 3rd control interface;
Wherein, described 3rd data-interface is connected with described 3rd control interface, sets up third communication channel; When described first communication interface and described second communication interface are same interface, a described CPU communicates with described on-off controller based on described third communication channel, controls the input data that described data output interface exports described first control interface or described second control interface.
Optionally, described 2nd CPU also comprises the 4th data-interface; Wherein, described 4th data-interface is connected with described second communication interface, sets up the 4th communication channel; Described 2nd CPU described safety check by after communicate with described storer with described 4th communication channel based on described second communication channel, read and run described system program.
Optionally, a described CPU also comprises the 5th data-interface; Described 2nd CPU also comprises the 6th data-interface; Wherein, described 5th data-interface is connected with described 6th data-interface, sets up the 5th communication channel; When a described CPU carries out described safety check to described system program, a described CPU controls described 2nd CPU based on described 5th communication channel and is in closed condition; When described safety check passes through, a described CPU controls described 2nd CPU based on described 5th communication channel and is in starting state.
The one or more technical schemes provided in the embodiment of the present application, at least have following technique effect or advantage:
Due in the embodiment of the present application, by adopt in POS terminal operating system hardware platform comprise the first data-interface a CPU (as safe CPU), comprise the 2nd CPU (as high-performance CPU) of the second data-interface and comprise the storer (as NANDFLASH) of the first communication interface and second communication interface, the system program for making POS terminal work run is stored in this storer, and the first communication channel that a described CPU can set up between the first data-interface and the first communication interface based on on-off controller communicates with described storer, safety check is carried out to described system program, reads with the second communication channel enabling the 2nd CPU set up at the second data-interface and second communication interface based on on-off controller after described safety check passes through and run described system program, that is, by selecting safe CPU and NANDFLASH with mating interface, safe CPU and NANDFLASH is communicated based on mating interface, and communication data form therebetween consistent (being all serial or parallel), thus the telecommunication circuit simplified therebetween, the speed making safe CPU read data in NANDFLASH improves, reduction working procedure checking time, reduce the speed of POS terminal start, solve the many and technical matters that travelling speed is slow of POS terminal operating system hardware platform circuit complex data line in prior art, achieve and simplify POS terminal operating system hardware platform circuit, improve the technique effect of travelling speed.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiment of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
A kind of POS terminal operating system hardware platform structured flowchart that Fig. 1 provides for the embodiment of the present application;
The second POS terminal operating system hardware platform structured flowchart that Fig. 2 provides for the embodiment of the present application;
The third POS terminal operating system hardware platform structured flowchart that Fig. 3 provides for the embodiment of the present application;
The 4th kind of POS terminal operating system hardware platform structured flowchart that Fig. 4 provides for the embodiment of the present application.
Embodiment
The embodiment of the present application is by providing a kind of POS terminal operating system hardware platform, solve the many and technical matters that travelling speed is slow of POS terminal operating system hardware platform circuit complex data line in prior art, achieve the technique effect simplifying POS terminal operating system hardware platform circuit, improve travelling speed.
The technical scheme of the embodiment of the present application is for solving the problems of the technologies described above, and general thought is as follows:
The embodiment of the present application provides a kind of POS terminal operating system hardware platform, comprising: for storing the storer of the system program making POS terminal work run, described storer comprises: the first communication interface and second communication interface; For carrying out a CPU of safety check to described system program, a described CPU comprises: the first data-interface; For running the 2nd CPU of described system program at described safety check by rear reading, described 2nd CPU comprises: the second data-interface; For setting up first communication channel between described first communication interface and described first data-interface, and/or set up the on-off controller of second communication channel between described second communication interface and described second data-interface; Wherein, a described CPU carries out safety check based on described first communication channel to described system program, and described 2nd CPU reads based on described second communication channel and runs described system program after described safety check passes through.
Visible, in the embodiment of the present application, by POS terminal operating system hardware platform adopt comprise the first data-interface a CPU (as safe CPU), comprise the 2nd CPU (as high-performance CPU) of the second data-interface and comprise the storer (as NANDFLASH) of the first communication interface and second communication interface, the system program for making POS terminal work run is stored in this storer, and the first communication channel that a described CPU can set up between the first data-interface and the first communication interface based on on-off controller communicates with described storer, safety check is carried out to described system program, reads with the second communication channel enabling the 2nd CPU set up at the second data-interface and second communication interface based on on-off controller after described safety check passes through and run described system program, that is, by selecting safe CPU and NANDFLASH with mating interface, safe CPU and NANDFLASH is communicated based on mating interface, and communication data form therebetween consistent (being all serial or parallel), thus the telecommunication circuit simplified therebetween, the speed making safe CPU read data in NANDFLASH improves, reduction working procedure checking time, reduce the speed of POS terminal start, solve the many and technical matters that travelling speed is slow of POS terminal operating system hardware platform circuit complex data line in prior art, achieve and simplify POS terminal operating system hardware platform circuit, improve the technique effect of travelling speed.
In order to better understand technique scheme, below in conjunction with Figure of description and concrete embodiment, technique scheme is described in detail, the specific features being to be understood that in the embodiment of the present application and embodiment is the detailed description to technical scheme, instead of the restriction to technical scheme, when not conflicting, the technical characteristic in the embodiment of the present application and embodiment can combine mutually.
Embodiment one
Please refer to Fig. 1, the embodiment of the present application provides a kind of POS terminal operating system hardware platform, and for running POS terminal operation system of software, described hardware platform comprises:
For storing the storer 10 of the system program making POS terminal work run, storer 10 comprises: the first communication interface 101 and second communication interface 102;
For carrying out a CPU20 of safety check to described system program, a CPU20 comprises: the first data-interface 201;
For running the 2nd CPU30 of described system program at described safety check by rear reading, the 2nd CPU30 comprises: the second data-interface 301;
For setting up first communication channel between the first communication interface 101 and the first data-interface 201, and/or set up the on-off controller 40 of second communication channel between second communication interface 102 and the second data-interface 301; Wherein, a CPU20 carries out safety check based on described first communication channel to described system program, and the 2nd CPU30 reads based on described second communication channel and runs described system program after described safety check passes through.
Wherein, a CPU20 is the safe CPU in POS terminal hardware platform, has plug-in storer, just can on-line operation run when powering on; 2nd CPU30 is the high-performance CPU in POS terminal hardware platform, arranges external program memory, and need downloading-running program from external program memory when powering on, could work operation; Storer 10 is the external program memory of the 2nd CPU30; One CPU20 and the 2nd CPU30 is and inputs defeated interface with secure digital, i.e. SDIO (Secure Digital Input and Output) interface; Storer 10 is specially the FLASH with SDIO interface, i.e. SDIO FLASH; And SDIO FLASH comprises one group of SDIO interface or two groups of SDIO interfaces; The system program for making POS terminal work run is stored in SDIO FLASH.The function of safe CPU mainly comprises: (1), when POS terminal needs to carry out terminal system program verification, carries out safety verification to system program; As when POS terminal is started shooting or after POS terminal is started shooting 24 hours, safe CPU needs to carry out safety check to the system program in storer 10, causes POS terminal to occur unsafe problems to prevent it from being run by high-performance CPU after being maliciously tampered; (2) when POS terminal inserts Payment Card (as bank card), read the card number information of Payment Card, and described card number information is sent in Payment Card new accounts section (as bank) system, to carry out authentication to Payment Card, when described authentication is passed through, communicate with high-performance CPU, payment authentication (as verified etc. the payment cipher of input) is carried out to Payment Card.The function of high-performance CPU mainly comprises: when safe CPU passes through terminal system program verification, the intelligent operating systems such as android, win-mobile are run in POS terminal, control POS terminal display screen and carry out picture display, and control input operation such as POS terminal response contact action, button operation etc. to realize human-computer interaction function.Safe CPU and high-performance CPU cooperating can complete the payment function of POS terminal.
In specific implementation process, the first data-interface 201 and the second data-interface 301 are SDIO interface.When SDIO FLASH comprises one group of SDIO interface (namely described first communication interface 101 and second communication interface 102 are same group interface), the first data-interface 201 and the second data-interface 301 are all connected with this group SDIO interface of SDIO FLASH; When SDIO FLASH comprises two groups of SDIO interfaces (namely described first communication interface 101 and second communication interface 102 are not same interface), the first data-interface 201 is connected with described two groups of SDIO interfaces respectively with the second data-interface 301 one_to_one corresponding.In addition, the setting of on-off controller 40, decreases the mutual interference in a CPU20 and the 2nd CPU30 and storer 10 communication process.
Below in conjunction with Fig. 2, illustrate the annexation between storer 10, a CPU20, the 2nd CPU30 and on-off controller 40 4:
First, on-off controller 40 comprises: the first control interface 401, second control interface 402 and data output interface 403; Wherein, the first data-interface 201 is connected with the first control interface 401; Second data-interface 301 is connected with the second control interface 402; Data output interface 403 is connected with the first communication interface 101 and/or second communication interface 102; Data output interface 403 can export the input data of the first control interface 401 and/or the second control interface 402.
Due in specific implementation process, according to actual needs, when storer 10 comprises two groups of SDIO interfaces (namely the first communication interface 101 and second communication interface 102 are not same group interface), the data line number of data output interface 403 be two groups of SDIO interface data wire numbers and, when storer 10 only comprises one group of SDIO interface (namely the first communication interface 101 and second communication interface 102 are same group interface), the number of data output interface 403 data line is identical with one group of SDIO interface data wire number, thus ensure that data output interface 403 can be connected with FLASH SDIO Interface Matching.
Please continue to refer to Fig. 2, in order to be communicated with the 2nd CPU30 with a CPU20 by control store 10 effectively, to make described first communication channel and described second communication channel not interfere with each other, a CPU20 also comprises the 3rd data-interface 202; On-off controller 40 also comprises the 3rd control interface 404;
Wherein, the 3rd data-interface 202 is connected with the 3rd control interface 404, sets up third communication channel; When the first communication interface 101 is same interface with second communication interface 102, one CPU20 communicates with on-off controller 40 based on described third communication channel, and control data output interface 403 exports the input data of the first control interface 401 or the second control interface 402.
Due in specific implementation process, no matter whether the first communication interface 101 is same interface with second communication interface 102, need to control to communicate with storer 10 with the 2nd both CPU30 one at synchronization the one CPU20 by a CPU20, realize a CPU20 and can be communicated with storer 10 by same SDIO interface by ensuring escapement from confliction with the 2nd CPU30.Especially, when the first communication interface 101 is same SDIO interface with second communication interface 102, this control operation is essential.
Embodiment two
In specific implementation process, please refer to Fig. 3, in order to make the 2nd CPU30 reading system program running from storer 10 rapidly, the 2nd CPU30 also comprises the 4th data-interface 302; Wherein, the 4th data-interface 302 is connected with second communication interface (102), sets up the 4th communication channel; 2nd CPU30 communicates with storer 10 with described 4th communication channel based on described second communication channel after described safety check passes through, and reads and runs described system program.
In specific implementation process, in order to ensure the security of the system program that the 2nd CPU30 reads from storer 10, a CPU20 also comprises the 5th data-interface 203; 2nd CPU30 also comprises the 6th data-interface 303; Wherein, the 5th data-interface 203 is connected with the 6th data-interface 303, sets up the 5th communication channel; When a CPU20 carries out described safety check to described system program, a CPU20 controls the 2nd CPU30 based on described 5th communication channel and is in closed condition; When described safety check passes through, a CPU20 controls the 2nd CPU30 based on described 5th communication channel and is in starting state.
That is, when a CPU20 carries out safety check to the system program in storer 10, one CPU20 sends closing control instruction to the 2nd CPU30 by described 5th communication channel, is in off position, the 2nd CPU30 cannot be communicated with storer 10 to control the 2nd CPU30; When a CPU20 to the system program in storer 10 carry out safety check pass through time, one CPU20 is sent by described 5th communication channel and starts steering order to the 2nd CPU30, in running order to control the 2nd CPU30,2nd CPU30 is communicated with storer 10, reads and run described system program.
In addition, in specific implementation process, also have between one CPU20 with the 2nd CPU30 based on USB or serial interface UART (Universal Asynchronous Receiver/Transmitter) be directly connected for realizing the 6th communication channel that the two directly communicates, in the process of POS terminal work, when needs carry out password authentification to Payment Card, one CPU20 sends data based on described 6th communication channel to the 2nd CPU30, exports to make a CPU20 prompt window etc. that prompting user carries out Password Input.
Embodiment three
In conjunction with concrete practical application, storer 10 selects model to be the NANDFLASH of the SDIO interface of KE4CN2H5A; On-off controller 40 selects model to be the bus switch of 74CBTLV3257BQ; First data-interface 201 of the one CPU20 (i.e. safe CPU) and second data-interface 301 of the 2nd CPU30 (i.e. high-performance CPU) are high-speed synchronous serial port SPI (Serial Peripheral interface) bus interface, spi bus interface is a kind of interface type in SDIO interface, a kind of high speed, full duplex, synchronous communication bus, and on the pin of chip, only take four lines, save the pin of chip, simultaneously for the layout of PCB saves space, provide convenience.Spi bus is a kind of four line locking bi-directional serial bus of standard, and the signal that four data lines are transmitted is respectively: data input signal SDI, data output signal SDO, clock signal SCLK, chip selection signal CS.
First composition graphs 4 is introduced the annexation between safe CPU20, high-performance CPU30,74CBTLV3257BQ and KE4CN2H5A tetra-devices below:
Safe CPU20 and high-performance CPU30 all has spi bus interface, and all passes through spi bus interface and be connected with two group of four line signal input interface of 74CBTLV3257BQ; Concrete, the spi bus interface 201 of safe CPU20 is connected with the input interface (1B1 ~ 4B1) of 74CBTLV3257BQ, and the spi bus interface 301 of high-performance CPU30 is connected with the input interface (1B2 ~ 4B2) of 74CBTLV3257BQ.Wherein, SPI tetra-line between safe CPU20 and 74CBTLV3257BQ is specially: data input signal line DAT0_1, data output signal line CMD_1, clock cable CLK_1, chip selection signal line RST_1, and this four line forms described first communication channel; SPI tetra-line between high-performance CPU30 and 74CBTLV3257BQ is specially: data input signal line DAT0_2, data output signal line CMD_2, clock cable CLK_2, chip selection signal line RST_2, and this four line forms described second communication channel.
In addition, the data-interface 202 of safe CPU20 connects with the input interface S-phase of 74CBTLV3257BQ, forms the control signal transmission line CTL_1 for control 74CBTLV3257BQ; The data-interface 203 of safe CPU20 is connected with the data-interface 303 of high-performance CPU30, forms the control signal transmission line CTL_2 for controlling high-performance CPU30; The four line output interfaces (1A ~ 4A) of 74CBTLV3257BQ are corresponding to be respectively connected with the four line communication interfaces (A3, M5, M6, K5) of KE4CN2H5A, this four line forms on-off controller and exports channel, comprises data input signal line DAT_0, data output signal line CMD, clock cable CLK, chip selection signal line RST; Communication interface (A4, A5, B2, B3, B4, B5, B6) correspondence of KE4CN2H5A is connected with the data-interface (D1 ~ D7) of high-performance CPU30, form described 4th communication channel, comprise data signal line (DAT_1 ~ DAT_7).
Be introduced below in conjunction with the principle of work of above-mentioned annexation to POS terminal system:
When POS terminal is started shooting or after POS terminal is started shooting 24 hours, safe CPU20 sends the first steering order by control signal transmission line CTL_1 to on-off controller 74CBTLV3257BQ, data-signal on first communication channel described in transmission is exported to make the described on-off controller of 74CBTLV3257BQ, namely at CMD_1, CLK_1, on RST_1 tri-data lines control signal effect under, the system program in 74CBTLV3257BQ is read by data input signal line DAT0_1, and safety check is carried out to described system program, send closing control signal by control signal transmission line CTL_2 to high-performance CPU30 simultaneously, off position is in control the 2nd CPU30, 2nd CPU30 cannot be communicated with 74CBTLV3257BQ.When described safety check passes through, safe CPU20 sends the second steering order by control signal transmission line CTL_1 to on-off controller 74CBTLV3257BQ, data-signal on second communication channel described in transmission is exported to make the described on-off controller of 74CBTLV3257BQ, send startup control signal by control signal transmission line CTL_2 to high-performance CPU30 simultaneously, in running order to control high-performance CPU30, 4th communication channel described in conducting, namely at CMD_2, CLK_2, on RST_2 tri-data lines control signal effect under, (corresponding with data input signal line DAT_0 by data input signal line DAT0_2, the data of transmission on signal wire DAT_0 can be obtained) and this eight data lines of data signal line (DAT_1 ~ DAT_7), the parallel system program read in 74CBTLV3257BQ, and run described system program.
In addition, in specific implementation process, please continue to refer to Fig. 4, safe CPU20 with also have between high-performance CPU30 based on USB or serial interface UART (Universal Asynchronous Receiver/Transmitter) be directly connected for realizing the 6th communication channel that the two directly communicates, in the process of POS terminal work, when needs carry out password authentification to Payment Card, safe CPU20 sends data based on described 6th communication channel to high-performance CPU30, exports to make safe CPU20 the prompt window etc. that prompting user carries out Password Input.
Generally speaking, in the application's scheme, the safe CPU of POS terminal and high-performance CPU can the same SDIO interface of access program storer FLASH, and the FLASH of safe CPU to described SDIO interface has priority access control; Safe CPU has startup control to high-performance CPU simultaneously; In the POS terminal course of work, preferentially safety check is carried out to the system program in SDIO FLAS by safe CPU, and in verification by rear, control to start high-performance CPU and read described system program from SDIO FLASH, to realize the normal operation of POS terminal.Namely the POS terminal based on the application's scheme has high safety, high-performance, low cost, simplicity of design, fireballing advantage.
Although described preferred embodiment of the present utility model, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the utility model scope.
Obviously, those skilled in the art can carry out various change and modification to the utility model and not depart from spirit and scope of the present utility model.Like this, if these amendments of the present utility model and modification belong within the scope of the utility model claim and equivalent technologies thereof, then the utility model is also intended to comprise these change and modification.
Claims (5)
1. a POS terminal operating system hardware platform, is characterized in that, described hardware platform comprises:
For storing the storer (10) of the system program making POS terminal work run, described storer (10) comprising: the first communication interface (101) and second communication interface (102);
For carrying out a CPU (20) of safety check to described system program, a described CPU (20) comprising: the first data-interface (201);
For running the 2nd CPU (30) of described system program at described safety check by rear reading, described 2nd CPU (30) comprising: the second data-interface (301);
For setting up first communication channel between described first communication interface (101) and described first data-interface (201), and/or set up the on-off controller (40) of second communication channel between described second communication interface (102) and described second data-interface (301); Wherein, a described CPU (20) carries out safety check based on described first communication channel to described system program, and described 2nd CPU (30) reads based on described second communication channel and runs described system program after described safety check passes through.
2. operating system hardware platform as claimed in claim 1, it is characterized in that, described on-off controller (40) comprising: the first control interface (401), the second control interface (402) and data output interface (403);
Wherein, described first data-interface (201) is connected with described first control interface (401); Described second data-interface (301) is connected with described second control interface (402); Described data output interface (403) is connected with described first communication interface (101) and/or described second communication interface (102); Described data output interface (403) can export the input data of described first control interface (401) and/or described second control interface (402).
3. operating system hardware platform as claimed in claim 2, it is characterized in that, a described CPU (10) also comprises the 3rd data-interface (202); Described on-off controller (40) also comprises the 3rd control interface (404);
Wherein, described 3rd data-interface (202) is connected with described 3rd control interface (404), sets up third communication channel; When described first communication interface (101) and described second communication interface (102) are for same interface, a described CPU (20) communicates with described on-off controller (40) based on described third communication channel, controls the input data that described data output interface (403) exports described first control interface (401) or described second control interface (402).
4. the operating system hardware platform as described in claim as arbitrary in claims 1 to 3, is characterized in that, described 2nd CPU (30) also comprises the 4th data-interface (302); Wherein, described 4th data-interface (302) is connected with described second communication interface (102), sets up the 4th communication channel; Described 2nd CPU (30) communicates with described storer (10) with described 4th communication channel based on described second communication channel after described safety check passes through, and reads and runs described system program.
5. operating system hardware platform as claimed in claim 4, it is characterized in that, a described CPU (20) also comprises the 5th data-interface (203); Described 2nd CPU (30) also comprises the 6th data-interface (303); Wherein, described 5th data-interface (203) is connected with described 6th data-interface (303), sets up the 5th communication channel; When a described CPU (20) carries out described safety check to described system program, a described CPU (20) controls described 2nd CPU (30) based on described 5th communication channel and is in closed condition; When described safety check passes through, a described CPU (20) controls described 2nd CPU (30) based on described 5th communication channel and is in starting state.
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| CN201420583902.8U CN204102259U (en) | 2014-10-10 | 2014-10-10 | A kind of POS terminal operating system hardware platform |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106991333A (en) * | 2017-04-27 | 2017-07-28 | 上海汇尔通信息技术有限公司 | A kind of safeguard method and device of data |
| CN114078416A (en) * | 2021-11-23 | 2022-02-22 | 京东方科技集团股份有限公司 | Sequential control circuit, display module and display device |
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2014
- 2014-10-10 CN CN201420583902.8U patent/CN204102259U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106991333A (en) * | 2017-04-27 | 2017-07-28 | 上海汇尔通信息技术有限公司 | A kind of safeguard method and device of data |
| CN114078416A (en) * | 2021-11-23 | 2022-02-22 | 京东方科技集团股份有限公司 | Sequential control circuit, display module and display device |
| CN114078416B (en) * | 2021-11-23 | 2023-12-29 | 京东方科技集团股份有限公司 | Time sequence control circuit, display module and display device |
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