CN204089599U - A kind of pulsewidth limiting circuit of inverter - Google Patents
A kind of pulsewidth limiting circuit of inverter Download PDFInfo
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- CN204089599U CN204089599U CN201420455333.9U CN201420455333U CN204089599U CN 204089599 U CN204089599 U CN 204089599U CN 201420455333 U CN201420455333 U CN 201420455333U CN 204089599 U CN204089599 U CN 204089599U
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Abstract
The utility model discloses a kind of pulsewidth limiting circuit of inverter, comprise main inverter circuit, rectifying output circuit, drive circuit, current sampling circuit, power supply IC1, also comprise the first bleeder circuit, voltage follower circuit, integrating circuit, the second bleeder circuit, operational amplifier IC2, operational amplifier IC3.The pulsewidth limiting circuit of this inverter can effective regulation output pulse duration, circuit is made to always work within the scope of safe current, efficiently avoid the generation of bias phenomenon, and circuit structure is simple, without the need to reducing the switching speed of power tube and increasing the absorption energy of power tube absorption circuit, substantially reduce opening and turn-off power loss of power tube, reduce production cost.
Description
Technical field
The utility model relates to inverter, particularly relates to a kind of pulsewidth limiting circuit of inverter.
Background technology
Inverter welding power source is called for short inverter, and have high, the lightweight advantage of efficiency, current domestic annual production has reached ten million platform, starts as increasing family and unit are used.Inverter industry has wide prospect, cause increasing enterprise to start to set foot in this field, under new development form, the function of inverter is more and more stronger and price is more and more lower, cause every cost of enterprise to improve constantly, profit becomes more and more meagre.Therefore, for how reducing product after cost, how improving product reliability, how becoming the most important thing at the situation decline low production production cost not reducing product reliability.
The Master control chip of current inverter operationally, when inverter pulsewidth the widest and occur asymmetry and duty ratio maximum time, because now pulse duration reaches the widest, Master control chip cannot increase pulsewidth again to adjust asymmetry, main inverter circuit is caused easily to occur bias phenomenon, namely two bridge arm current sizes of bridge circuit are asymmetric, wherein a bridge arm current is bigger than normal, another bridge arm current is less than normal, as adjusted not in time, the power tube of the side that electric current is bigger than normal will generate heat seriously, after long-time multicycle magnetic bias, main transformer may enter saturation condition, now just there is the danger burnt out.And the mode of current anti-magnetic bias, mainly by reducing the switching speed of power tube, the absorption energy increasing power tube absorption circuit effectively reduces magnetic bias, but this kind of mode too increases opening of power tube and turn-off power loss, the power of absorption circuit is caused to increase, cause heat in machine to strengthen, therefore need larger radiator and heat radiation wind speed, cause occurring the series of problems such as product cost rising, machine efficiency reduction.
Summary of the invention
The utility model, for defects such as in the machine existed in prior art, heat are large, product cost is high, machine efficiency is low, provides a kind of pulsewidth limiting circuit of new inverter.
In order to solve the problems of the technologies described above, the utility model is achieved through the following technical solutions:
A kind of pulsewidth limiting circuit of inverter, comprise main inverter circuit, rectifying output circuit, drive circuit, current sampling circuit, power supply IC1, described rectifying output circuit, drive circuit is connected with main inverter circuit respectively, described main inverter circuit is connected by the current feedback terminal of current sampling circuit with power supply IC, the output OUTA of described power supply IC1 is connected with drive circuit respectively with output OUTB, also comprise the first bleeder circuit, voltage follower circuit, integrating circuit, second bleeder circuit, operational amplifier IC2, operational amplifier IC3, the first described bleeder circuit leads up to voltage follower circuit, current-limiting resistance R16 is connected with the PWM adjustable side of power supply IC1, another road is connected with the reference voltage terminal of power supply IC1, the output OUTA of described power supply IC1 is connected with integrating circuit by diode D2, the output OUTB of described power supply IC1 is connected with integrating circuit by diode D1, described integrating circuit is connected with the in-phase input end of operational amplifier IC2, output one tunnel of described operational amplifier IC2 is connected with the inverting input of operational amplifier IC2, resistance R12 of separately leading up to is connected with the inverting input of operational amplifier IC3, the in-phase input end of described operational amplifier IC3 is held with the VC of power supply IC1 by the second bleeder circuit and is connected, the output of operational amplifier IC3 is leaded up to resistance R13 and is connected with the inverting input of operational amplifier IC3, separately lead up to resistance R14, diode D5 is connected with the PWM adjustable side of power supply IC1.
The reference voltage terminal of power supply IC1 is by the PWM adjustable side to power supply IC1 after the first bleeder circuit dividing potential drop, to the preset level in the PWM adjustable side of power supply IC1, by regulating the voltage of the PWM adjustable side of power supply IC1, the output OUTA of controllable power IC1 and the impulse magnitude of output OUTB, when main inverter circuit pulse duration is narrower, by the current feedback terminal of current sampling circuit to power supply IC, the output OUTA of power supply IC1 and output OUTB is made to export burst pulse, after operational amplifier IC2, the inverting input of operational amplifier IC3 is arrived through integrating circuit dividing potential drop, if now the in-phase input end voltage of operational amplifier IC3 is lower than inverting input, then the output of operational amplifier IC3 exports high level, if the high level that operational amplifier IC3 exports is higher than the PWM adjustable side voltage of power supply IC1, then now diode D5 ends, resistance R14, diode D5 does not have electric current to flow through, namely the output end voltage of operational amplifier IC3 does not have any impact to power supply IC1, circuit working complete the dividing potential drop depending on the first bleeder circuit, when main inverter circuit pulse is very wide, then the output OUTA of power supply IC1 and the output pulse of output OUTB broaden, the in-phase input end voltage then finally arriving operational amplifier IC3 is higher, now the in-phase input end voltage of operational amplifier IC3 is higher than anti-phase input terminal voltage, the then output output low level of operational amplifier IC3, if now the output end voltage of operational amplifier IC3 is lower than the PWM adjustable side voltage of power supply IC1, then now diode D5 conducting, resistance R14, diode D5 there is electric current to flow through thus the PWM adjustable side voltage of power supply IC1 is dragged down, and then the output OUTA of power supply IC1 and the output pulse width of output OUTB are narrowed, circuit is made to always work within the scope of safe current, efficiently avoid the generation of bias phenomenon, and circuit structure is simple, without the need to reducing the switching speed of power tube and increasing the absorption energy of power tube absorption circuit, substantially reduce opening and turn-off power loss of power tube, reduce production cost.
As preferably, the pulsewidth limiting circuit of a kind of inverter described above, also comprise triode Q1, operational amplifier IC4, the base stage of described triode Q1 is leaded up to divider resistance R6 and is connected with the output OUTA of power supply IC1, divider resistance R7 of separately leading up to is connected to ground, the collector electrode of described triode Q1 is connected with VCC, the emitter of described triode Q1 is connected with the in-phase input end of operational amplifier IC4 by diode D3, described diode D3 two ends are parallel with resistance R9, the inverting input of described operational amplifier IC4 is connected with the second bleeder circuit, the output of described operational amplifier IC4 is by diode D4, resistance R15 is connected with the PWM adjustable side of power supply IC1.
Output OUTA, the output OUTB of power supply IC1 pass through drive circuit, main inverter circuit, rectifying output circuit to late-class circuit, wherein main inverter circuit is also by the current feedback terminal of current sampling circuit to power supply IC1, in use, if when the late-class circuit of rectifying output circuit has short circuit or an overload phenomenon, main inverter circuit may burn out by the big current then produced, and this partial circuit can limiting short-circuit current, make electric current all the time in safe range, avoid the possibility burnt out.
As preferably, the pulsewidth limiting circuit of a kind of inverter described above, also comprises electric capacity C2, electric capacity C5, and described electric capacity C2 is parallel to the two ends of divider resistance R7, described electric capacity C5 one end is connected with the in-phase input end of operational amplifier IC4, other end ground connection.Play filter action, make circuit more stable.
As preferably, the pulsewidth limiting circuit of a kind of inverter described above, the first described bleeder circuit comprises resistance R1, resistance R2, potentiometer VT1, described resistance R2 one end ground connection, the other end is connected with the reference voltage terminal of power supply IC1 by potentiometer VT1, resistance R1, and described voltage follower circuit is connected with potentiometer VT1.
The bleeder circuit of connecting that resistance R1, resistance R2 and potentiometer VT1 form, makes the center tap voltage that just can be changed potentiometer VT1 by regulator potentiometer VT1, and then is transported to rear class thus the preset voltage of change power supply IC.
As preferably, the pulsewidth limiting circuit of a kind of inverter described above, the second described bleeder circuit comprises resistance R8, resistance R10, resistance R11, the in-phase input end of described operational amplifier IC3 is held with the VC of power supply IC1 by resistance R8 and is connected, and a end of described resistance R8 is connected to ground by resistance R10, resistance R11.
After the bleeder circuit dividing potential drop that resistance R8, resistance R10, resistance R11 form, the voltage of the tie point of resistance R10 and resistance R11 as the input voltage of the inverting input of rear class operational amplifier IC4, through the voltage of the tie point of resistance R8 and resistance R10 as the input voltage of the in-phase input end of rear class operational amplifier IC3.
As preferably, the pulsewidth limiting circuit of a kind of inverter described above, also comprise electric capacity C3, electric capacity C4, electric capacity C6, a end, the b end of described resistance R8 are connected to ground respectively by electric capacity C4, electric capacity C3, and the two ends of described resistance R11 are parallel with electric capacity C6.Play filter action, make circuit more stable.
As preferably, the pulsewidth limiting circuit of a kind of inverter described above, described integrating circuit comprises resistance R4, resistance R5, electric capacity C1, the anode of described diode D1 is connected with resistance R4 respectively with the anode of diode D2, described resistance R4 is leaded up to resistance R5 and is connected to ground, another road is connected with the in-phase input end of operational amplifier IC2, and described electric capacity C1 is parallel to the two ends of resistance R5.
In the integrating circuit of resistance R4, resistance R5, electric capacity C composition, resistance R4 and resistance R5 forms bleeder circuit, but owing to there being the effect of electric capacity C1, electric capacity both end voltage i.e. resistance R5 both end voltage can not be suddenlyd change, make electric capacity C1 and resistance R5 both end voltage present a kind of slowly uphill process and slow decline process.
As preferably, the pulsewidth limiting circuit of a kind of inverter described above, described resistance R13 two ends are also parallel with electric capacity C6.Play filter action, make circuit more stable.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of the pulsewidth limiting circuit of a kind of inverter of the utility model.
Embodiment
Below in conjunction with accompanying drawing 1 and embodiment, the utility model is described in further detail, but they are not to restriction of the present utility model:
embodiment 1
As shown in Figure 1, a kind of pulsewidth limiting circuit of inverter, comprise main inverter circuit 2, rectifying output circuit 1, drive circuit 3, current sampling circuit 8, power supply IC1, described rectifying output circuit 1, drive circuit 3 is connected with main inverter circuit 2 respectively, described main inverter circuit 2 is connected with the current feedback terminal of power supply IC by current sampling circuit 8, the output OUTA of described power supply IC1 is connected with drive circuit 3 respectively with output OUTB, it is characterized in that: also comprise the first bleeder circuit 7, voltage follower circuit 6, integrating circuit 4, second bleeder circuit 5, operational amplifier IC2, operational amplifier IC3, the first described bleeder circuit 7 leads up to voltage follower circuit 6, current-limiting resistance R16 is connected with the PWM adjustable side of power supply IC1, another road is connected with the reference voltage terminal of power supply IC1, the output OUTA of described power supply IC1 is connected with integrating circuit 4 by diode D2, the output OUTB of described power supply IC1 is connected with integrating circuit 4 by diode D1, described integrating circuit 4 is connected with the in-phase input end of operational amplifier IC2, output one tunnel of described operational amplifier IC2 is connected with the inverting input of operational amplifier IC2, resistance R12 of separately leading up to is connected with the inverting input of operational amplifier IC3, the in-phase input end of described operational amplifier IC3 is held with the VC of power supply IC1 by the second bleeder circuit 5 and is connected, the output of operational amplifier IC3 is leaded up to resistance R13 and is connected with the inverting input of operational amplifier IC3, separately lead up to resistance R14, diode D5 is connected with the PWM adjustable side of power supply IC1.
During work, the reference voltage terminal of power supply IC1 is by the PWM adjustable side to power supply IC1 after the first bleeder circuit 7 dividing potential drop, to the preset level in the PWM adjustable side of power supply IC1, by regulating the voltage of the PWM adjustable side of power supply IC1, the output OUTA of controllable power IC1 and the impulse magnitude of output OUTB, wherein output OUTA and output OUTB is that symmetrical complement exports, namely width is identical, the pulse that direction is contrary, the pulse that output OUTA exports arrives integrating circuit 4 through diode D2, the pulse that output OUTB exports arrives integrating circuit 4 through diode D1, the in-phase input end of operational amplifier IC2 is arrived after integrating circuit 4 processes, because the output of operational amplifier IC2 is connected with inverting input, the multiplication factor of operational amplifier IC2 is made to equal 1, namely operational amplifier IC2 is voltage follower, therefore the voltage of the in-phase input end input of operational amplifier IC2 is output to the inverting input of operational amplifier IC3, the in-phase input end of operational amplifier IC3 is held with the VC of power supply IC1 by the second bleeder circuit 5 and is connected.Because operational amplifier IC3 is differential amplifier, then when main inverter circuit 2 pulse duration is narrower, by the current feedback terminal of current sampling circuit 8 to power supply IC, output OUTA and output OUTB is made to export burst pulse, the voltage then arriving the inverting input of operational amplifier IC3 is lower, if now the in-phase input end voltage of operational amplifier IC3 is higher than anti-phase input terminal voltage, then the output of operational amplifier IC3 exports high level, by the PWM adjustable side voltage higher than power supply IC1, cause diode D5 cannot conducting, therefore now diode D5 and resistance R14 no current flow through, namely the voltage of operational amplifier IC3 does not have any impact to power supply IC1, circuit working complete the dividing potential drop depending on the first bleeder circuit 7, otherwise, when pulse duration is wider, output OUTA and output OUTB exports pulse and also broadens thereupon, the voltage then finally arriving the inverting input of operational amplifier IC3 is higher, if now the anti-phase input terminal voltage of operational amplifier IC3 is higher than in-phase input end voltage, the then output output low level of operational amplifier IC3, if now the output end voltage of operational amplifier IC3 is lower than the PWM adjustable side voltage of power supply IC1, then diode D5 conducting, now diode D5 and resistance R14 there is electric current to flow through, and the PWM adjustable side voltage of power supply IC1 is dragged down, thus reduce the output OUTA of power supply IC1 and the output pulse width of output OUTB, circuit is made to always work within the scope of safe current, efficiently avoid the generation of bias phenomenon.
As preferably, also comprise triode Q1, operational amplifier IC4, the base stage of described triode Q1 is leaded up to divider resistance R6 and is connected with the output OUTA of power supply IC1, divider resistance R7 of separately leading up to is connected to ground, the collector electrode of described triode Q1 is connected with VCC, the emitter of described triode Q1 is connected with the in-phase input end of operational amplifier IC4 by diode D3, described diode D3 two ends are parallel with resistance R9, the inverting input of described operational amplifier IC4 is connected with the second bleeder circuit 5, the output of described operational amplifier IC4 is by diode D4, resistance R15 is connected with the PWM adjustable side of power supply IC1.
During work, the voltage of the output OUTA output of power supply IC1 is by arriving the base stage of triode Q1 after divider resistance R6 and divider resistance R7 dividing potential drop, because triode Q1 is for penetrating a grade follower, therefore the voltage of the emitter of triode Q1 is equal with the voltage of base stage, the voltage of the emitter of triode Q1 is through resistance R9, to the in-phase input end of operational amplifier IC4 after diode D3, the inverting input of operational amplifier IC4 is held with the VC of power supply IC1 by the second bleeder circuit 5 and is connected, because operational amplifier IC4 is voltage comparator, when circuit normally works, namely when the in-phase input end voltage of operational amplifier IC4 is higher than anti-phase input terminal voltage, the output of operational amplifier IC4 exports high level, higher than the PWM adjustable side voltage of power supply IC1, now diode D4 cannot conducting, on diode D4 and resistance R15, no current flows through, therefore now operational amplifier IC4 does not have any impact to power supply IC1, otherwise, when there is short circuit in the late-class circuit of rectifying output circuit 1, the electric current of main inverter circuit 2 will increase, and by the current feedback terminal of current sampling circuit 8 to power supply IC, make the pulse narrowing that the output OUTA of power supply IC1 exports, the voltage of the inverting input of final arrival operational amplifier IC4 is lower, when making the in-phase input end voltage of now operational amplifier IC4 lower than anti-phase input terminal voltage, the output output low level of operational amplifier IC4, and lower than the PWM adjustable side voltage of power supply IC1, now diode D4 conducting, diode D4 and resistance R15 there is electric current to flow through, and then drag down the PWM adjustable side voltage of power supply IC1, make the pulse duration of the output OUTA of power supply IC1 and output OUTB narrower, thus main inverter circuit 2 and rectifying output circuit 1 operating current are diminished, and make operating current remain in safe range, avoid the danger that main inverter circuit 2 burns out.
As preferably, also comprise electric capacity C2, electric capacity C5, described electric capacity C2 is parallel to the two ends of divider resistance R7, and described electric capacity C5 one end is connected with the in-phase input end of operational amplifier IC4, other end ground connection.
As preferably, the first described bleeder circuit 7 comprises resistance R1, resistance R2, potentiometer VT1, described resistance R2 one end ground connection, the other end is connected with the reference voltage terminal of power supply IC1 by potentiometer VT1, resistance R1, and described voltage follower circuit 6 is connected with potentiometer VT1.
As preferably, the second described bleeder circuit 5 comprises resistance R8, resistance R10, resistance R11, the in-phase input end of described operational amplifier IC3 is held with the VC of power supply IC1 by resistance R8 and is connected, and a end of described resistance R8 is connected to ground by resistance R10, resistance R11.
As preferably, also comprise electric capacity C3, electric capacity C4, electric capacity C6, a end, the b end of described resistance R8 are connected to ground respectively by electric capacity C4, electric capacity C3, and the two ends of described resistance R11 are parallel with electric capacity C6.
As preferably, described integrating circuit 4 comprises resistance R4, resistance R5, electric capacity C1, the anode of described diode D1 is connected with resistance R4 respectively with the anode of diode D2, described resistance R4 is leaded up to resistance R5 and is connected to ground, another road is connected with the in-phase input end of operational amplifier IC2, and described electric capacity C1 is parallel to the two ends of resistance R5.
As preferably, described resistance R13 two ends are also parallel with electric capacity C6.
In a word, the foregoing is only preferred embodiment of the present utility model, the equalization change that all scopes applied for a patent according to the utility model are done and modification, all should belong to covering scope of the present utility model.
Claims (8)
1. the pulsewidth limiting circuit of an inverter, comprise main inverter circuit (2), rectifying output circuit (1), drive circuit (3), current sampling circuit (8), power supply IC1, described rectifying output circuit (1), drive circuit (3) is connected with main inverter circuit (2) respectively, described main inverter circuit (2) is connected with the current feedback terminal of power supply IC by current sampling circuit (8), the output OUTA of described power supply IC1 is connected with drive circuit (3) respectively with output OUTB, it is characterized in that: also comprise the first bleeder circuit (7), voltage follower circuit (6), integrating circuit (4), second bleeder circuit (5), operational amplifier IC2, operational amplifier IC3, described the first bleeder circuit (7) leads up to voltage follower circuit (6), current-limiting resistance R16 is connected with the PWM adjustable side of power supply IC1, another road is connected with the reference voltage terminal of power supply IC1, the output OUTA of described power supply IC1 is connected with integrating circuit (4) by diode D2, the output OUTB of described power supply IC1 is connected with integrating circuit (4) by diode D1, described integrating circuit (4) is connected with the in-phase input end of operational amplifier IC2, output one tunnel of described operational amplifier IC2 is connected with the inverting input of operational amplifier IC2, resistance R12 of separately leading up to is connected with the inverting input of operational amplifier IC3, the in-phase input end of described operational amplifier IC3 is held with the VC of power supply IC1 by the second bleeder circuit (5) and is connected, the output of operational amplifier IC3 is leaded up to resistance R13 and is connected with the inverting input of operational amplifier IC3, separately lead up to resistance R14, diode D5 is connected with the PWM adjustable side of power supply IC1.
2. the pulsewidth limiting circuit of a kind of inverter according to claim 1, it is characterized in that: also comprise triode Q1, operational amplifier IC4, the base stage of described triode Q1 is leaded up to divider resistance R6 and is connected with the output OUTA of power supply IC1, divider resistance R7 of separately leading up to is connected to ground, the collector electrode of described triode Q1 is connected with VCC, the emitter of described triode Q1 is connected with the in-phase input end of operational amplifier IC4 by diode D3, described diode D3 two ends are parallel with resistance R9, the inverting input of described operational amplifier IC4 is connected with the second bleeder circuit (5), the output of described operational amplifier IC4 is by diode D4, resistance R15 is connected with the PWM adjustable side of power supply IC1.
3. the pulsewidth limiting circuit of a kind of inverter according to claim 2, it is characterized in that: also comprise electric capacity C2, electric capacity C5, described electric capacity C2 is parallel to the two ends of divider resistance R7, and described electric capacity C5 one end is connected with the in-phase input end of operational amplifier IC4, other end ground connection.
4. the pulsewidth limiting circuit of a kind of inverter according to claim 1, it is characterized in that: described the first bleeder circuit (7) comprises resistance R1, resistance R2, potentiometer VT1, described resistance R2 one end ground connection, the other end is connected with the reference voltage terminal of power supply IC1 by potentiometer VT1, resistance R1, and described voltage follower circuit (6) is connected with potentiometer VT1.
5. the pulsewidth limiting circuit of a kind of inverter according to claim 1, it is characterized in that: described the second bleeder circuit (5) comprises resistance R8, resistance R10, resistance R11, the in-phase input end of described operational amplifier IC3 is held with the VC of power supply IC1 by resistance R8 and is connected, and a end of described resistance R8 is connected to ground by resistance R10, resistance R11.
6. the pulsewidth limiting circuit of a kind of inverter according to claim 5, it is characterized in that: also comprise electric capacity C3, electric capacity C4, electric capacity C6, a end, the b end of described resistance R8 are connected to ground respectively by electric capacity C4, electric capacity C3, and the two ends of described resistance R11 are parallel with electric capacity C6.
7. the pulsewidth limiting circuit of a kind of inverter according to claim 1, it is characterized in that: described integrating circuit (4) comprises resistance R4, resistance R5, electric capacity C1, the anode of described diode D1 is connected with resistance R4 respectively with the anode of diode D2, described resistance R4 is leaded up to resistance R5 and is connected to ground, another road is connected with the in-phase input end of operational amplifier IC2, and described electric capacity C1 is parallel to the two ends of resistance R5.
8. the pulsewidth limiting circuit of a kind of inverter according to claim 1, is characterized in that: described resistance R13 two ends are also parallel with electric capacity C6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420455333.9U CN204089599U (en) | 2014-08-13 | 2014-08-13 | A kind of pulsewidth limiting circuit of inverter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420455333.9U CN204089599U (en) | 2014-08-13 | 2014-08-13 | A kind of pulsewidth limiting circuit of inverter |
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| Publication Number | Publication Date |
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| CN204089599U true CN204089599U (en) | 2015-01-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420455333.9U Withdrawn - After Issue CN204089599U (en) | 2014-08-13 | 2014-08-13 | A kind of pulsewidth limiting circuit of inverter |
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| CN (1) | CN204089599U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104135155A (en) * | 2014-08-13 | 2014-11-05 | 永康市帝普特科技有限公司 | Pulse width limiting circuit of inverter |
| CN110737301A (en) * | 2019-10-29 | 2020-01-31 | 中国人民解放军海军工程大学 | High-precision positive-negative adjustable type current stabilization system and method based on multi-operational amplifier feedback loop |
-
2014
- 2014-08-13 CN CN201420455333.9U patent/CN204089599U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104135155A (en) * | 2014-08-13 | 2014-11-05 | 永康市帝普特科技有限公司 | Pulse width limiting circuit of inverter |
| CN110737301A (en) * | 2019-10-29 | 2020-01-31 | 中国人民解放军海军工程大学 | High-precision positive-negative adjustable type current stabilization system and method based on multi-operational amplifier feedback loop |
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