CN204067333U - Chip-packaging structure - Google Patents
Chip-packaging structure Download PDFInfo
- Publication number
- CN204067333U CN204067333U CN201420450413.5U CN201420450413U CN204067333U CN 204067333 U CN204067333 U CN 204067333U CN 201420450413 U CN201420450413 U CN 201420450413U CN 204067333 U CN204067333 U CN 204067333U
- Authority
- CN
- China
- Prior art keywords
- chip
- support
- circuit substrate
- packaging structure
- electronic devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
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Abstract
The utility model provides a kind of chip-packaging structure, it comprises circuit substrate, the chip be affixed on circuit substrate, be affixed on circuit substrate and be positioned at the electronic devices and components of chip both sides, circuit substrate is provided with support, under chip and electronic devices and components cover in support, support passes through outer rim frame on circuit substrate, the flange separating chip and electronic devices and components is also provided with below support, chip is placed in the space that the outer rim of support and flange enclose, effectively can prevent the pollution being subject to dust and particle, avoid causing image identification stain problem, improve product yield.
Description
Technical field
The utility model relates to encapsulation field, refers in particular to a kind of encapsulating structure being applied to camera chip.
Background technology
Conventional art be applied to mobile phone camera, the encapsulation of panel computer camera, such as COB encapsulation (chip On board), PLCC encapsulates (Plastic Leaded Chip Carrier), as depicted in figs. 1 and 2, traditional encapsulating structure comprises circuit substrate 110, be affixed on the chip 120 on circuit substrate, to be affixed on circuit substrate and to be positioned at the electronic devices and components 130 of chip both sides, circuit substrate upper cover support 140, chip 120 and electronic devices and components 130 cover in support 140, support 140 posts colour filter 150, as seen from Figure 2, this chip 120 and electronic devices and components 130 are placed in the same space in support 140, each other without isolated, PCB, electronic devices and components are all the parts becoming easily infected by and carry dust, this encapsulating structure of conventional art, after vibration transport, dust is as easy as rolling off a log to be moved on chip photosensitive area, thus cause image identification (take pictures/photograph) to have stain (2), yield is low, impact uses, shorten the camera life-span, cause greatly inconvenience and loss.
Therefore, provide a kind of chip-packaging structure can effectively avoiding chip to be subject to polluting, yield is high real in necessary.
Summary of the invention
The purpose of this utility model is the chip-packaging structure providing a kind of yield high.
For realizing the utility model object, provide following technical scheme:
The utility model provides a kind of chip-packaging structure, it comprises circuit substrate, the chip be affixed on circuit substrate, be affixed on circuit substrate and be positioned at the electronic devices and components of chip both sides, circuit substrate is provided with support, under chip and electronic devices and components cover in support, support passes through outer rim frame on circuit substrate, the flange separating chip and electronic devices and components is also provided with below support, chip is placed in the space that the outer rim of support and flange enclose, effectively can prevent the pollution being subject to dust and particle, avoid causing image identification stain problem, improve product yield.
The flange of this support is consistent with the height of outer rim, and the space making it enclose is more tight, is not invaded by extraneous dust.
Also be provided with the press strip that can compress chip in the inner side of flange below this support.
This rack upper surface is provided with the step surface installing colour filter.
This step surface is provided with at least one groove on one side.
At least one angle of this step surface is provided with the arc angle of abduction, is convenient to place and take out colour filter.
Contrast prior art, the utility model has the following advantages:
The utility model chip-packaging structure improves the structure of support, and the appropriate design of support has isolated the dust and particle that electronic devices and components carry, and makes it can not transfer to chip photosensitive region, greatly improves product yield.
Accompanying drawing explanation
Fig. 1 is the decomposing schematic representation of existing encapsulating structure;
Fig. 2 is the cutaway view of existing encapsulating structure;
Fig. 3 is the decomposing schematic representation of the utility model chip-packaging structure;
Fig. 4 is the cutaway view of the utility model chip-packaging structure.
Embodiment
Refer to Fig. 3 and Fig. 4, the utility model chip-packaging structure comprises circuit substrate 210, be affixed on the chip 220 on circuit substrate, to be affixed on circuit substrate and to be positioned at the electronic devices and components 230 of chip both sides, circuit substrate is provided with support 240, chip 220 and electronic devices and components 230 cover in support 240 times, support 240 passes through outer rim 246 frame on circuit substrate 210, the flange 241 separating chip 220 and electronic devices and components 230 is also provided with below support 240, in the space that the outer rim 246 that chip 220 is placed in support 240 and flange 241 enclose, effectively can prevent the pollution being subject to dust and particle, avoid causing image identification stain problem, improve product yield.
Preferably, the flange 241 of this support 240 is consistent with the height of outer rim 246, and the space making it enclose is more tight, is not invaded by extraneous dust.
Preferably, below this support 240, be also provided with the press strip 242 that can compress chip 220 in the inner side of flange 241, can positioning chip.
Preferably, this support 240 upper surface is provided with the step surface 244 installing colour filter 250, and colour filter 250 is just arranged on step surface 244.
Preferably, this step surface 244 is provided with three grooves 245.
Preferably, this step surface 244 4 jiaos is equipped with the arc angle 243 of abduction, is convenient to place and take out colour filter 250.
The foregoing is only preferred embodiment of the present utility model, protection range of the present utility model is not limited thereto, and anyly all belongs within the utility model protection range based on the equivalent transformation in technical solutions of the utility model.
Claims (6)
1. a chip-packaging structure, it comprises circuit substrate, the chip be affixed on circuit substrate, be affixed on circuit substrate and be positioned at the electronic devices and components of chip both sides, circuit substrate is provided with support, support passes through outer rim frame on circuit substrate, under chip and electronic devices and components cover in support, it is characterized in that, be also provided with the flange separating chip and electronic devices and components below support, chip is placed in the space that the outer rim of support and flange enclose.
2. chip-packaging structure as claimed in claim 1, it is characterized in that, the flange of this support is consistent with the height of outer rim.
3. chip-packaging structure as claimed in claim 2, is characterized in that, be also provided with the press strip that can compress chip below this support in the inner side of flange.
4. the chip-packaging structure as described in any one of claim 1 ~ 3, is characterized in that, this rack upper surface is provided with the step surface installing colour filter.
5. chip-packaging structure as claimed in claim 4, it is characterized in that, this step surface is provided with at least one groove.
6. chip-packaging structure as claimed in claim 4, it is characterized in that, at least one angle of this step surface is provided with the arc angle of abduction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420450413.5U CN204067333U (en) | 2014-08-11 | 2014-08-11 | Chip-packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420450413.5U CN204067333U (en) | 2014-08-11 | 2014-08-11 | Chip-packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204067333U true CN204067333U (en) | 2014-12-31 |
Family
ID=52208789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420450413.5U Ceased CN204067333U (en) | 2014-08-11 | 2014-08-11 | Chip-packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204067333U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024752A (en) * | 2016-06-22 | 2016-10-12 | 深圳市森邦半导体有限公司 | PLCC (plastic leaded chip carrier) module |
-
2014
- 2014-08-11 CN CN201420450413.5U patent/CN204067333U/en not_active Ceased
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024752A (en) * | 2016-06-22 | 2016-10-12 | 深圳市森邦半导体有限公司 | PLCC (plastic leaded chip carrier) module |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141231 Termination date: 20170811 |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| IW01 | Full invalidation of patent right |
Decision date of declaring invalidation: 20170109 Decision number of declaring invalidation: 31093 Granted publication date: 20141231 |
|
| IW01 | Full invalidation of patent right |