CN203983281U - Array base palte and display unit - Google Patents
Array base palte and display unit Download PDFInfo
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- CN203983281U CN203983281U CN201420326927.XU CN201420326927U CN203983281U CN 203983281 U CN203983281 U CN 203983281U CN 201420326927 U CN201420326927 U CN 201420326927U CN 203983281 U CN203983281 U CN 203983281U
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- connecting portion
- switching hole
- public electrode
- array base
- base palte
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- 239000010409 thin film Substances 0.000 claims abstract description 30
- 230000004888 barrier function Effects 0.000 claims description 32
- 238000005530 etching Methods 0.000 claims description 32
- 238000002161 passivation Methods 0.000 claims description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims description 6
- 150000004706 metal oxides Chemical class 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 description 26
- 238000000034 method Methods 0.000 description 26
- 230000015572 biosynthetic process Effects 0.000 description 14
- 238000009413 insulation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000010023 transfer printing Methods 0.000 description 1
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Abstract
The utility model provides a kind of array base palte, this array base palte comprises public electrode wire, thin-film transistor, public electrode, public electrode wire is positioned at the active layer below of thin-film transistor, public electrode wire top is provided with main switching hole, wherein, public electrode is electrically connected with public electrode wire by the main connecting portion being at least partially disposed in main switching hole, main connecting portion comprises main connecting portion and lower main connecting portion, lower main connecting portion comprises main body and is arranged on the flange extending in main body and towards the direction away from center, main switching hole, the lower end of upper main connecting portion is connected with flange, the upper end of upper main connecting portion is connected with public electrode.The utility model also provides the display unit that comprises above-mentioned array base palte.In array base palte provided by the utility model, between public electrode wire and public electrode wire, there is reliable electrical connection.Therefore, comprise the display unit display frame better of array base palte.
Description
Technical field
The utility model relates to Display Technique field, particularly, relates to a kind of array base palte and the display unit that comprises described array base palte.
Background technology
Shown in Fig. 1 is a kind of array base palte, and this array base palte comprises public electrode 10, public electrode wire 20, thin-film transistor 30 and pixel electrode 40, and public electrode 10 is electrically connected with public electrode wire 20.Between the layer at public electrode 10 places and the layer at public electrode wire 20 places, be also provided with etching barrier layer 31 and passivation layer 50, for public electrode 10 is electrically connected with public electrode wire 20, switching hole 60 can be set above public electrode wire 20, when deposition forms public electrode 10, the sidewall in switching hole 60 and diapire are (, the upper surface of public electrode wire 20) on also form one deck public electrode material, the public electrode material of switching in hole 60 is formed as the connecting portion 70 that public electrode wire 20 is electrically connected with public electrode 10.Because passivation layer 50 and etching barrier layer 31 have relatively large thickness, therefore, in the time forming connecting portion 70, easily on the sidewall in switching hole 60, produce breach, cause bad connection between public electrode wire 20 and public electrode 10.
Therefore, how to prevent that between public electrode wire 20 and public electrode 10, bad connection becomes this area technical problem urgently to be resolved hurrily.
Utility model content
The purpose of this utility model is the manufacture method of a kind of array base palte, this array base palte and comprises the display unit of described array base palte.In described array base palte, between public electrode wire and public electrode wire, there is reliable electrical connection.
To achieve these goals, as an aspect of the present utility model, a kind of array base palte is provided, this array base palte comprises public electrode wire, thin-film transistor, public electrode, the active layer interval of described public electrode wire and described thin-film transistor arranges, described public electrode wire top is provided with main switching hole, wherein, described public electrode is electrically connected with described public electrode wire by the main connecting portion being at least partially disposed in described main switching hole, described main connecting portion comprises main connecting portion and lower main connecting portion, described lower main connecting portion comprises main body and is arranged on the flange extending in described main body and towards the direction away from center, described main switching hole, the lower end of described main connecting portion is connected with described flange, the upper end of described main connecting portion is connected with described public electrode.
Preferably, described main switching hole comprises main switching hole and lower main switching hole, and the width in described main switching hole is greater than the width in described lower main switching hole, described main body is arranged in described lower main switching hole, described flange is arranged on the junction in described main switching hole and described lower main switching hole, described main connecting portion is arranged in described main switching hole, and described main connecting portion and described public electrode form as one.
Preferably, described main switching hole comprises main switching hole and lower main switching hole, and the upper end in described flange main switching hole from described extends to the outside in described main switching hole.
Preferably, described lower main connecting portion is synchronizeed and is formed with the pixel electrode of described array base palte, and described main connecting portion and described public electrode form as one
Preferably, described flange top is provided with auxiliary switching hole, and described public electrode is electrically connected with described flange by the auxiliary connecting portion being arranged in described auxiliary switching hole.
Preferably, the active layer of described thin-film transistor is made up of metal oxide, and described array base palte also comprises the etching barrier layer of the active layer top that is arranged on described thin-film transistor, and described flange is arranged on described etching barrier layer top.
Preferably, between described etching barrier layer and described public electrode, be provided with passivation layer.
As another aspect of the present utility model, a kind of manufacture method of array base palte is provided, wherein, described manufacture method comprises:
S10, formation comprise the figure of the grid of public electrode wire and thin-film transistor;
S20, form main switching hole, described main switching hole is positioned at the top of described public electrode wire, and arrives described public electrode wire;
S30, formation comprise the figure of main connecting portion, described main connecting portion is at least partially disposed in described main switching hole, described main connecting portion comprises main connecting portion and lower main connecting portion, the flange that described lower main connecting portion comprises main body and is arranged in described main body and extends towards the direction away from center, described main switching hole, the lower end of described main connecting portion is connected with described flange;
S40, formation comprise the figure of described public electrode, and described public electrode is connected with the upper end of described main connecting portion.
Preferably, the active layer of described thin-film transistor is made up of metal oxide, and described manufacture method is included in carries out between described step S10 and described step S20:
S15, above the active layer of described thin-film transistor, form the step of etching barrier layer;
Described step S20 comprises:
S21, the lower main switching of formation hole, this lower main switching hole is run through described etching barrier layer and is arrived described public electrode wire;
S22, formation are positioned at the passivation layer of described etching barrier layer top;
S23, position corresponding with described lower main switching hole on described etching barrier layer form main switching hole, and remove the passivation material being deposited in described lower main switching hole, and described main switching hole and described lower main switching hole connect, and form described main switching hole.
Preferably, the width in described main switching hole is greater than the width in described lower main switching hole, described step S30 and described step S40 synchronously carry out, and the described main connecting portion forming in described step S30 is in described main switching hole, the main body of described lower main connecting portion is arranged in described lower main switching hole, described flange is positioned at the junction in described main switching hole and described lower main switching hole, and described flange is positioned on described etching barrier layer.
Preferably, the width in described main switching hole equals the width in described lower main switching hole, and described step S30 comprises:
S31, form described lower main connecting portion, described flange is positioned on described etching barrier layer;
S32, form described main connecting portion; Wherein,
Described step S31 carries out between described step S21 and described step S22, and, in described step S31, forming pixel electrode, described step S32 is synchronizeed and is carried out with described step S40.
Preferably, described manufacture method also comprises:
S50, formation are positioned at the auxiliary switching hole of described flange top;
S60, in described auxiliary switching hole, arrange the auxiliary connecting portion of described public electrode and described flange electrical connection.
Preferably, described step S60 is synchronizeed and is carried out with described step S40.
As another aspect of the present utility model, a kind of display unit is provided, this display unit comprises array base palte, wherein, described array base palte is above-mentioned array base palte provided by the utility model.
In array base palte provided by the utility model, after having increased the flange extending towards the direction away from center, main switching hole, the total depth in the main switching of the vertical Length Ratio hole of upper main connecting portion is little, the total depth in the main switching of the vertical Length Ratio hole of the main body of lower main connecting portion is little, therefore, in the time forming described main connecting portion, on the upper connecting portion of this main connecting portion and the lower connecting portion of described main connecting portion, be all difficult for producing breach, and form the metal level continuous uniform of main connecting portion, thereby reduced the probability that in main connecting portion, generation is opened circuit.In other words,, in array base palte provided by the utility model, between public electrode wire and public electrode wire, there is reliable electrical connection.Therefore, comprise the display unit display frame better of described array base palte.
In addition,, while utilizing manufacture method provided by the utility model to manufacture array base palte provided by the utility model, do not increase the complexity of manufacture method.,, in the time utilizing manufacture method provided by the utility model to manufacture described array base palte, can obtain higher production efficiency.
Brief description of the drawings
Accompanying drawing is to be used to provide further understanding of the present utility model, and forms a part for specification, is used from explanation the utility model, but does not form restriction of the present utility model with embodiment one below.In the accompanying drawings:
Fig. 1 is the schematic diagram of existing array base palte;
Fig. 2 is the schematic diagram of the first execution mode of array base palte provided by the utility model;
Fig. 3 is the schematic diagram of the second execution mode of array base palte provided by the utility model;
Fig. 4 utilizes manufacture method provided by the utility model to prepare the flow chart of the array base palte shown in Fig. 2;
Fig. 5 utilizes manufacture method provided by the utility model to prepare the flow chart of the array base palte shown in Fig. 3.
Description of reference numerals
10: public electrode 20: public electrode wire
30: thin-film transistor 31: etching barrier layer
32: active layer 33: source electrode
34: drain electrode 35: grid
36: gate insulation layer 40: pixel electrode
50: passivation layer 60: switching hole
61: main switching hole 62: auxiliary switching hole
70: connecting portion 71: upper main connecting portion
72: lower main connecting portion 80: auxiliary connecting portion
92: the second mask plates of 91: the first mask plates
61a: upper main switching hole 61b: lower main switching hole
72a: main body 72b: flange
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is elaborated.Should be understood that, embodiment described herein only, for description and interpretation the utility model, is not limited to the utility model.
Should be understood that, the noun of locality " upper and lower " using in specification all refers to " upper and lower " direction in accompanying drawing.
As shown in Figures 2 and 3, as an aspect of the present utility model, a kind of array base palte, this array base palte comprises public electrode wire 20, thin-film transistor 30, public electrode 10, public electrode wire 20 is positioned at active layer 32 belows of thin-film transistor 30, and public electrode wire 20 tops are provided with main switching hole 61.Wherein, public electrode 10 is electrically connected with public electrode wire 20 by the main connecting portion being at least partially disposed in main switching hole 61, and described main connecting portion comprises main connecting portion 71 and lower main connecting portion 72.Lower main connecting portion 72 comprises main body 72a and is arranged on main body 72a above and towards the flange 72b extending away from the direction at main switching Kong61 center, the lower end of upper main connecting portion 71 is connected with flange 72b, and the upper end of upper main connecting portion 71 is connected with public electrode 10.
Increase after the flange 72b extending away from the direction at main switching Kong61 center, the total depth in the main switching of the vertical Length Ratio hole 61 of upper main connecting portion 71 is little, the total depth in the main switching of the vertical Length Ratio hole 61 of the main body 72a of lower main connecting portion 72 is little, therefore, in the time forming described main connecting portion, on the upper connecting portion 71 of this main connecting portion and the lower connecting portion 72 of described main connecting portion, be all difficult for producing breach, form the metal level continuous uniform of described main connecting portion, therefore, reduced the probability that in described main connecting portion, generation is opened circuit.In other words,, in array base palte provided by the utility model, between public electrode wire and public electrode wire, there is reliable electrical connection.
Should be understood that, above described " public electrode wire 20 arranges with active layer 32 intervals of thin-film transistor 30 " refers to, (for example between the layer at the layer at public electrode wire 20 places and active layer 32 places of thin-film transistor 30, be also provided with other layers, in the embodiment shown in Fig. 2 and Fig. 3, between the layer at public electrode wire 20 places and the layer at active layer 32 places of thin-film transistor 30, be provided with etching barrier layer 31, gate insulation layer 36 and passivation layer 50).
In the array base palte shown in Fig. 2 and Fig. 3, thin-film transistor 30 has bottom grating structure, that is, the grid 35 of thin-film transistor 30 is arranged on active layer 32 belows.The source electrode 33 of thin-film transistor 30 is identical with set-up mode of the prior art with the set-up mode of drain electrode 34, repeats no more here.
As a kind of embodiment of the present utility model, preferably, as shown in Figure 2, main switching hole 61 comprises main switching hole 61a and lower main switching hole 61b, and the width of upper main switching hole 61a is greater than the width (width described herein refers to main switching hole 61a and the lower main switching hole 61b size along left and right directions in Fig. 2) of lower main switching hole 61b,, main switching hole 61 is formed as shoulder hole.The main body 72a of lower main connecting portion 72 is arranged in lower main switching hole 61b, the junction that flange 72b is arranged on main switching hole 61a and lower main switching hole 61b (, on the step of shoulder hole), upper main connecting portion 71 is arranged in main switching hole 61a, and described main connecting portion and public electrode 10 form as one.
Junction between upper main switching hole 61a and lower main switching hole 61b can be plane, can be also inclined plane.
As another kind of execution mode of the present utility model, as shown in Figure 3, main switching hole 61 comprises main switching hole 61a and lower main switching hole 61b, and flange 72b extends to the outside in described main switching hole from the upper end of lower main switching hole 61b.
In the execution mode shown in Fig. 3, the lower surface of upper main connecting portion 71 can be fitted on the upper surface of flange 72b completely, and therefore, in this embodiment, being electrically connected between public electrode 10 and public electrode wire 20 is more reliable.
For the ease of manufacturing, can in forming pixel electrode 40, form lower main connecting portion 72, and preferably, upper main connecting portion 71 be formed as one with public electrode 10, in the time forming public electrode 10, can synchronously form main connecting portion 71.Should be understood that, flange 72b can not be connected with pixel electrode 40.
In order further to improve the reliability being connected between public electrode 10 and public electrode wire 20, preferably, auxiliary switching hole 62 can be set above flange 72b, public electrode 10 is electrically connected with flange 72b by the auxiliary connecting portion 80 being arranged in auxiliary switching hole 62.
As a kind of embodiment of the present utility model, the active layer of thin-film transistor 30 is made up of metal oxide, in this case, described array base palte also comprises the etching barrier layer 31 of active layer 32 tops that are arranged on described thin-film transistor, and flange 72b is arranged on the top of etching barrier layer 31.In the time that the active layer of thin-film transistor is metal oxide, the advantage that etching barrier layer is set is known in the field, repeats no more here.
As noted before, as a kind of embodiment of the present utility model, between etching barrier layer 31 and public electrode 10, be provided with passivation layer.
As another aspect of the present utility model, the manufacture method of above-mentioned array base palte provided by the utility model is provided, wherein, described manufacture method comprises:
S10, formation comprise the figure of the grid of public electrode wire and thin-film transistor;
S20, form main switching hole, described main switching hole is positioned at the top of described public electrode wire, and described main switching hole arrives described public electrode wire;
S30, formation comprise the figure of main connecting portion, described main connecting portion is at least partially disposed in described main switching hole, described main connecting portion comprises main connecting portion and lower main connecting portion, the flange that described lower main connecting portion comprises main body and is arranged in described main body and extends towards the direction away from center, described main switching hole, the lower end of described main connecting portion is connected with described flange;
S40, formation comprise the figure of described public electrode, and described public electrode is connected with the upper end of described main connecting portion.
Hold intelligiblely, added sequence number for convenience of description before each step, still, the sequence number before each step is not the order that authentic representative is carried out this step.
Particularly, the active layer of described thin-film transistor can be made up of metal oxide, and as shown in Figures 4 and 5, described manufacture method can be included in carries out between described step S10 and described step S20:
S15, above the active layer of described thin-film transistor, form the step of etching barrier layer 31.
Above active layer, be formed with in the situation of etching barrier layer 31, described etching barrier layer is run through in described main switching hole.Can form the step with the hole that connects described etching barrier layer by the composition technique such as printing, transfer printing.For cost-saving, preferably, can utilize traditional photoetching process to form the hole that connects described etching barrier layer.Particularly, described step S20 can comprise:
S21, the lower main switching hole 61b of formation, this lower main switching hole 61b runs through etching barrier layer 31 and arrives public electrode wire 20;
S22, formation are positioned at the passivation layer 50 of etching barrier layer 31 tops;
S23, form main switching hole 61a in etching barrier layer 31 positions corresponding to main switching hole 61b, up and down, and remove the passivation material being deposited in described lower main switching hole, upper main switching hole 61a and lower main switching hole 61b connect, to form described main switching hole.
As shown in Figure 4, after forming the etching barrier layer 31 of covered substrate, can utilize the first mask plate 91 to form lower main switching hole 61b by photoetching process.After forming etching barrier layer 31 and passivation layer 50, can utilize the second mask plate 92 to form upper main switching hole 61a by photoetching process.One skilled in the art will appreciate that therefore, lower main switching hole 61b has also run through gate insulation layer 36 owing to being formed with gate insulation layer 36 between the active layer 32 of thin-film transistor 30 and grid 35.
Shown in Fig. 4 be the array base palte shown in construction drawing 2 time flow chart, as shown in FIG., the width of upper main switching hole 61a is greater than the width of lower main switching hole 61b, should be understood that, " width " described herein refers to main switching hole 61a and the lower main switching hole 61b size along left and right directions in Fig. 4.In this embodiment, described step S30 and described step S40 synchronously carry out (, in same step, forming public electrode 10 and described main connecting portion).As noted before, the upper main connecting portion 71 forming in described step S30 is arranged in described main switching hole 61a, the main body 72a of lower main connecting portion 72 is arranged in lower main switching hole 61b, flange 72b is positioned at the junction of main switching hole 61a and lower main switching hole 61b, and flange 72b is positioned on etching barrier layer 31.
Because step S30 and described step S40 synchronously carry out, therefore, compared with the prior art of describing in background technology, the method for preparing array base palte provided by the utility model does not increase the complexity of preparing array base palte.Hold intelligiblely, in Fig. 4, the direction of arrow is the order of each preparation process in manufacture method provided by the utility model.
In order to prepare the array base palte shown in Fig. 3, as shown in Figure 5, the width of upper main switching hole 61a equals the width of lower main switching hole 61b, and described step S30 comprises:
S31, the lower main connecting portion 72 of formation, flange 72b is positioned on described etching barrier layer;
Main connecting portion 71 in S32, formation; Wherein,
Described step S31 carries out between described step S21 and described step S22, and, in described step S31, forming pixel electrode, described step S32 and described step S40 carry out simultaneously.
As shown in Figure 5, in forming pixel electrode 40, form time main connecting portion 72, in forming public electrode 10, form main connecting portion 71, therefore, compared with the prior art of describing in background technology, the method for preparing array base palte provided by the utility model does not increase the complexity of preparing array base palte.Hold intelligiblely, in Fig. 5, the direction of arrow is the order of each preparation process in manufacture method provided by the utility model.
Comprise that at array base palte, in the execution mode in auxiliary switching hole, described manufacture method also comprises:
S50, formation are positioned at the auxiliary switching hole 62 of flange 72b top;
S60, in auxiliary switching hole 62, arrange the auxiliary connecting portion 80 of public electrode 10 and flange 72b electrical connection.
Prepare in order to reduce array base palte step, enhance productivity, preferably, described step S60 is synchronizeed and is carried out with described step S40., auxiliary connecting portion 80 forms in same step with public electrode 10.
Further preferably, described step S50 and described step S23 carry out simultaneously,, on forming, in main switching hole 61a, form described auxiliary connecting portion 80 that is, further to reduce the step of preparing array base palte, enhance productivity.
In sum, while utilizing manufacture method provided by the utility model to manufacture array base palte provided by the utility model, do not increase the complexity of manufacture method.,, in the time utilizing manufacture method provided by the utility model to manufacture described array base palte, can obtain higher production efficiency.
As another aspect of the present utility model, a kind of display unit is provided, this display unit comprises array base palte, wherein, described array base palte is above-mentioned array base palte provided by the utility model.
Hold intelligiblely, described display unit also comprises color membrane substrates box-like being become with described array base palte.
The display unit that the utility model offers can be the electronic equipments such as liquid crystal panel, TV, mobile phone, panel computer.
In array base palte provided by the utility model, after having increased the flange extending towards the direction away from center, main switching hole, the total depth in the main switching of the vertical Length Ratio hole of upper main connecting portion is little, the total depth in the main switching of the vertical Length Ratio hole of the main body of lower main connecting portion is little, therefore,, in the time forming described main connecting portion, be not easy to produce breach or non-continuous event,, reduced the probability that in main connecting portion, generation is opened circuit.In other words,, in array base palte provided by the utility model, between public electrode wire and public electrode wire, there is reliable electrical connection.Therefore, comprise the display unit display frame better of described array base palte.
Be understandable that, above execution mode is only used to principle of the present utility model is described and the illustrative embodiments that adopts, but the utility model is not limited to this.For those skilled in the art, in the situation that not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection range of the present utility model.
Claims (8)
1. an array base palte, this array base palte comprises public electrode wire, thin-film transistor, public electrode, the active layer interval of described public electrode wire and described thin-film transistor arranges, described public electrode wire top is provided with main switching hole, it is characterized in that, described public electrode is electrically connected with described public electrode wire by the main connecting portion being at least partially disposed in described main switching hole, described main connecting portion comprises main connecting portion and lower main connecting portion, described lower main connecting portion comprises main body and is arranged on the flange extending in described main body and towards the direction away from center, described main switching hole, the lower end of described main connecting portion is connected with described flange, the upper end of described main connecting portion is connected with described public electrode.
2. array base palte according to claim 1, it is characterized in that, described main switching hole comprises main switching and lower main switching hole, and the width in described main switching hole is greater than the width in described lower main switching hole, described main body is arranged in described lower main switching hole, described flange is arranged on the junction in described main switching hole and described lower main switching hole, and described main connecting portion is arranged in described main switching hole, and described main connecting portion and described public electrode form as one.
3. array base palte according to claim 1, is characterized in that, described main switching hole comprises main switching hole and lower main switching hole, and the upper end in described flange main switching hole from described extends to the outside in described main switching hole.
4. array base palte according to claim 3, is characterized in that, described lower main connecting portion is synchronizeed and formed with the pixel electrode of described array base palte, and described main connecting portion and described public electrode form as one
5. according to the array base palte described in any one in claim 1 to 4, it is characterized in that, described flange top is provided with auxiliary switching hole, and described public electrode is electrically connected with described flange by the auxiliary connecting portion being arranged in described auxiliary switching hole.
6. according to the array base palte described in any one in claim 1 to 4, it is characterized in that, the active layer of described thin-film transistor is made up of metal oxide, described array base palte also comprises the etching barrier layer of the active layer top that is arranged on described thin-film transistor, and described flange is arranged on described etching barrier layer top.
7. array base palte according to claim 6, is characterized in that, between described etching barrier layer and described public electrode, is provided with passivation layer.
8. a display unit, described display unit comprises array base palte, it is characterized in that, described array base palte is the array base palte described in any one in claim 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420326927.XU CN203983281U (en) | 2014-06-18 | 2014-06-18 | Array base palte and display unit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420326927.XU CN203983281U (en) | 2014-06-18 | 2014-06-18 | Array base palte and display unit |
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| CN203983281U true CN203983281U (en) | 2014-12-03 |
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| CN201420326927.XU Expired - Lifetime CN203983281U (en) | 2014-06-18 | 2014-06-18 | Array base palte and display unit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104091805A (en) * | 2014-06-18 | 2014-10-08 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method and display device of array substrate |
-
2014
- 2014-06-18 CN CN201420326927.XU patent/CN203983281U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104091805A (en) * | 2014-06-18 | 2014-10-08 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method and display device of array substrate |
| WO2015192526A1 (en) * | 2014-06-18 | 2015-12-23 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor and display device |
| CN104091805B (en) * | 2014-06-18 | 2017-01-25 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method and display device of array substrate |
| US9966389B2 (en) | 2014-06-18 | 2018-05-08 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof and display device |
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