CN203968209U - The opto-electronic image processing system of high accuracy large format scanner - Google Patents

The opto-electronic image processing system of high accuracy large format scanner Download PDF

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Publication number
CN203968209U
CN203968209U CN201420376883.1U CN201420376883U CN203968209U CN 203968209 U CN203968209 U CN 203968209U CN 201420376883 U CN201420376883 U CN 201420376883U CN 203968209 U CN203968209 U CN 203968209U
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CN
China
Prior art keywords
cis
register
control module
large format
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201420376883.1U
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Chinese (zh)
Inventor
吕坤
唐雪松
赵泽东
陈仕隆
杨雷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NINGBO MOSHI OPTOELECTRONICS TECHNOLOGY Co Ltd
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NINGBO MOSHI OPTOELECTRONICS TECHNOLOGY Co Ltd
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Priority to CN201420376883.1U priority Critical patent/CN203968209U/en
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Publication of CN203968209U publication Critical patent/CN203968209U/en
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Abstract

The utility model discloses a kind of opto-electronic image processing system of high accuracy large format scanner, solved available technology adopting CCD and caused cost higher, image easily produces the problem of distortion.The utility model comprises the assembly module forming for the CIS scanning by least 2, the IMAQ control module being connected with assembly module, and the host computer being connected with IMAQ control module, wherein, all CIS are laterally arranged in order along left and right and are two rows, adjacent CIS lays respectively in this two row and is interlaced arrangement, and the end position of adjacent CIS is overlapped on fore-and-aft direction, described assembly module also comprises the AD converter that respective numbers is connected one to one with CIS, and all AD converter are all connected with IMAQ control module.The utility model internal structure is simplified greatly, and cost is lower, and CIS can a plurality of splicings meet the needs that width exposes thoroughly, and is applicable to promoting the use of.

Description

The opto-electronic image processing system of high accuracy large format scanner
Technical field
The utility model relates to a kind of working portion of scanner, specifically refers to the structure of large format scanner inter-process system.
Background technology
Large format scanner is a kind of high-precision comprehensive optics, machinery, the integrated equipment of electric height, and it is delivered to by view data the precision instrument that host computer carries out processes and displays storage by imageing sensor.Meanwhile, large format scanner is also being brought into play irreplaceable effect in some professional domain (as: engineering drawing, the manufacturing, GIS-Geographic Information System, mapping etc.), for the scanning industry of large format provides high-quality image output scheme.
Owing to being subject to the impact of early stage technology, that large format scanner conventionally adopts is CCD(Charge-coupled Device) imageing sensor scans, and by inter-process system, scan image is processed, and the treatment system that ccd image sensor inside is is complicated optical system, cause high expensive, and because light path is longer, there is comparatively significantly picture distortion in the image scanning.
Utility model content
In order to solve the higher problem of cost of available technology adopting ccd image sensor, it is a kind of based on CIS(Contact Image Sensor that the utility model provides) the image processing system framework of the large format scanner that scans of imageing sensor.
To achieve these goals, the technical solution adopted in the utility model is as follows:
The opto-electronic image processing system of high accuracy large format scanner, comprise the assembly module forming for the CIS scanning by least 2, the IMAQ control module being connected with assembly module, and the host computer being connected with IMAQ control module, wherein, all CIS are laterally arranged in order along left and right and are two rows, adjacent CIS lays respectively in this two row and is interlaced arrangement, and the end position of adjacent CIS is overlapped on fore-and-aft direction, described assembly module also comprises the AD converter that respective numbers is connected one to one with CIS, all AD converter are all connected with IMAQ control module.
For realizing the signal integrity output that CIS is collected, described each CIS is connected with IMAQ control module by its three output channels.
Field programming during for ease of use, the signal collecting is sorted, prevent entanglement, described IMAQ control module comprises the FPGA control circuit being directly connected with AD converter, the SDRAM register being connected with FGPA control circuit respectively, FLASH register and stepping motor, wherein stepping motor is used for driving CIS to scan.
Further, described FPGA control circuit comprises FPGA controller, the command register, status register, configuration register and the sequential register that are connected with FPGA controller respectively, wherein CIS is connected with FPGA controller by logical circuit of clock, SDRAM register is connected with sequential register by SDRAM control interface, FLASH register is connected with FPGA controller by FLASH control interface, and FPGA controller is connected with host computer with AD converter.
Wherein, FPGA(Field-Programmable Gate Array), i.e. field programmable gate array; SDRAM register (Synchronous Dynamic Random Access Memory), i.e. synchronous DRAM; FLASH register is Flash EEPROM Memory.
Compared with prior art, the utlity model has following beneficial effect:
(1) the utility model adopts the image capturing system framework based on CIS imageing sensor, carries out large format scanning, has two advantages that prior art is incomparable:
A. because CIS imageing sensor is in the advantage aspect optical system, large format scanner need not embed optical system hardware again and improve scanning effect, can reduce equally large format scanner internal structure complexity, CIS price, far below CCD, reduces this entire system infrastructure cost greatly simultaneously;
The image that B. can fundamentally solve scanning produces the problem of distortion, can make the medium can 1:1 imaging, the process that reduces like this distortion correction can be optimized the internal structure of large format scanner, simplify scanner in follow-up image handling process, also can guarantee to greatest extent the authenticity of data simultaneously.
(2) CIS in the utility model is subject to stepping motor driving, is connected with AD converter simultaneously, and this makes the CIS dismounting in system comparatively easy.
(3) the utility model adopts FPGA control circuit, can connect a plurality of CIS, can realize the parallel transmission of multiple signals, overcome because single CIS is compared with the short defect that is not enough to scan whole medium, also avoided changing or reduce the generation of the fortuitous events such as the logical process that CIS brings is chaotic, sweep length is inadequate.
Accompanying drawing explanation
Fig. 1 is the system block diagram in the utility model-embodiment.
Fig. 2 is the circuit diagram of FPGA control circuit in the utility model-embodiment.
Embodiment
Below in conjunction with drawings and Examples, the utility model is described in further detail, and execution mode of the present utility model includes but not limited to the following example.
Embodiment
As shown in Figure 1, the utility model comprises assembly module, image acquisition and processing control module and host computer three parts.
Wherein assembly module comprises at least 2 CIS, and the AD converter being connected one to one with CIS, and wherein all AD converter are all connected with IMAQ control module.
In the present embodiment, adopt the CIS of 5 A4 breadth sizes to form the splicing of " it " font, the breadth of realizing whole scanner is up to A0 breadth, these 5 CIS are laterally arranged in order and are two row's parallel shapes by its bar shaped direction left and right, adjacent CIS stagger before and after mutually and end position overlapped on fore-and-aft direction, prevent between two CIS to produce the space that there is no transducer, cause the image of gap to gather, can effectively prevent picture distortion.
Owing to all there being three output channels on each CIS, therefore have 15 output channels, each CIS is all connected with an AD converter by output channel, is about to analog signal and converts digital signal to, is convenient to subsequent treatment.
Image acquisition and processing control module as shown in Figure 1, comprise FPGA control circuit, the AD converter being connected with FPGA control circuit respectively, FLASH register, SDRAM register and stepping motor, wherein stepping motor is used for driving CIS to scan, and described FLASH register and SDRAM register are existing storage hardware.
As shown in Figure 2, described FPGA control circuit comprises FPGA controller, the command register, status register, configuration register and the sequential register that are connected with FPGA controller respectively, wherein CIS is connected with logical circuit of clock, SDRAM register is connected with sequential register by SDRAM control interface, FLASH register is connected with FPGA controller by FLASH control interface, and FPGA controller is connected with AD converter, and is connected with host computer by USB port.Wherein, command register, status register, configuration register and sequential register are existing storage hardware, logical circuit of clock is circuit ripe in prior art, simultaneously for ease of clearly expressing the utility model mentality of designing, some general components and parts (as resistance, electric capacity, triode etc.) in this FPGA control circuit, have been omitted, technical staff can lead a surname of this framework lower to the concrete formation of this control circuit of technology common-sense reasoning of this area, and obtain complete electrical connection detail drawing, in the utility model, do not repeat.
According to above-described embodiment, just can realize well the utility model.

Claims (4)

1. the opto-electronic image processing system of high accuracy large format scanner, it is characterized in that, comprise the assembly module forming for the CIS scanning by least 2, the IMAQ control module being connected with assembly module, and the host computer being connected with IMAQ control module, wherein, all CIS are laterally arranged in order along left and right and are two rows, adjacent CIS lays respectively in this two row and is interlaced arrangement, and the end position of adjacent CIS is overlapped on fore-and-aft direction, described assembly module also comprises the AD converter that respective numbers is connected one to one with CIS, all AD converter are all connected with IMAQ control module.
2. the opto-electronic image processing system of high accuracy large format scanner according to claim 1, is characterized in that, described each CIS is connected with IMAQ control module by its three output channels.
3. the opto-electronic image processing system of high accuracy large format scanner according to claim 1 and 2, it is characterized in that, described IMAQ control module comprises the FPGA control circuit being directly connected with AD converter, the SDRAM register being connected with FGPA control circuit respectively, FLASH register and stepping motor, wherein stepping motor is used for driving CIS to scan.
4. the opto-electronic image processing system of high accuracy large format scanner according to claim 3, it is characterized in that, described FPGA control circuit comprises FPGA controller, the command register, status register, configuration register and the sequential register that are connected with FPGA controller respectively, wherein CIS is connected with FPGA controller by logical circuit of clock, SDRAM register is connected with sequential register by SDRAM control interface, FLASH register is connected with FPGA controller by FLASH control interface, and FPGA controller is connected with host computer with AD converter.
CN201420376883.1U 2014-07-09 2014-07-09 The opto-electronic image processing system of high accuracy large format scanner Expired - Fee Related CN203968209U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104104827A (en) * 2014-07-09 2014-10-15 宁波摩视光电科技有限公司 High-precision large-format scanner photoelectric image processing system and implementation method thereof
CN108401085A (en) * 2018-03-14 2018-08-14 河北南昊高新技术开发有限公司 A kind of scan method, scanner and scanning system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104104827A (en) * 2014-07-09 2014-10-15 宁波摩视光电科技有限公司 High-precision large-format scanner photoelectric image processing system and implementation method thereof
CN108401085A (en) * 2018-03-14 2018-08-14 河北南昊高新技术开发有限公司 A kind of scan method, scanner and scanning system

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CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20141126

Termination date: 20170709