CN203968088U

CN203968088U - The regular socket circuit being formed by NAND gate

Info

Publication number: CN203968088U
Application number: CN201420421230.0U
Authority: CN
Inventors: 蒋小芳
Original assignee: Quzhou Disheng Industrial Design Co Ltd
Current assignee: Quzhou Disheng Industrial Design Co Ltd
Priority date: 2014-07-29
Filing date: 2014-07-29
Publication date: 2014-11-26
Anticipated expiration: 2024-07-29

Abstract

The regular socket circuit being formed by NAND gate, relate to a kind of electronic timing circuit, formed by power interface, decompression capacitor, rectifier diode, filtering capacitor, voltage stabilizing didoe, timing resistor a, timing switch, time capacitor a, NAND gate, biasing resistor, triode a, added-time switch, timing resistor b, time capacitor b, isolation resistance, driving resistance, triode b, relay, time delay resistance, delay switch, delay capacitor and isolating diode; Working power is connected to the second input of NAND gate a and the positive pole of time capacitor a by timing resistor a and timing switch; The collector electrode of triode a is connected to the positive pole of time capacitor b by charging resistor, added-time switch and timing resistor b; Time delay resistance is connected to two inputs of NAND gate d and the positive pole of delay capacitor by delay switch.The multi-functional that the utlity model has timing and added-time start, delay switching-off, can meet the requirement using in people's life.

Description

The regular socket circuit being formed by NAND gate

Technical field

The utility model relates to electronic circuit, specially refers to a kind of electronic timing circuit.

Background technology

In people's live and work, often use timer, timer makes to need the work in people's control time to become simply many, also bring great convenience, as utilize timer to switch on power and cook at the time chien shih electric cooker of setting, people just can be had dinner coming home from work, save time.But general timer only has on-delay type timer or off delay type timer, function singleness, can not meet the instructions for use that needs to need again after timing start-up delay switching-off; The structure of programmable timer is by CPU (CPU) as processing and control axis, and circuit structure complexity and cost are high, and its product price is higher, will cause waste many during to the less demanding applications of timing accuracy.

Utility model content

The purpose of this utility model is will provide a kind of circuit structure simply and the low regular socket circuit being made up of NAND gate of cost, has the dual-use function of timing start-up and delay switching-off, makes regular socket can meet the requirement using in people's life.

A kind of regular socket circuit being made up of NAND gate of the present utility model, is characterized in that regular socket main circuit will be by the phase line interface (L) of power supply, the zero line interface (N) of power supply, buffer resistance (R14), decompression capacitor (C2), rectifier diode a(V2), rectifier diode b(V3), filtering capacitor (C3), voltage stabilizing didoe (V4), timing resistor a, timing switch (BK1), time capacitor a(C1), NAND gate a(IC1), biasing resistor (R15), triode a(VT1), charging resistor (R21), added-time switch (BK2), timing resistor b, time capacitor b(C4), isolation resistance (R22), NAND gate b(IC2), NAND gate c(IC3), drive resistance (R34), triode b(VT2), clamp diode (V7), relay, time delay resistance, delay switch (BK3), delay capacitor (C5), NAND gate d(IC4) and isolating diode (V6) composition, wherein, relay pack vinculum circle (K) and contact switch (Ka), timing switch (BK1), added-time switch (BK2) and delay switch (BK3) have respectively lever arm, timing gear, zero-span, the first pin of decompression capacitor (C2) is connected to the phase line interface (L) of power supply by buffer resistance (R14), the crus secunda of decompression capacitor (C2) is connected to rectifier diode a(V2) negative electrode and rectifier diode b(V3) anode, rectifier diode b(V3) negative electrode be connected to the positive pole of filtering capacitor (C3) and the negative electrode of voltage stabilizing didoe (V4) and form working power (V+), rectifier diode a(V2) anode, the anodic bonding of the negative pole of filtering capacitor (C3) and voltage stabilizing didoe (V4) forms ground wire to the zero line interface (N) of power supply, the first pin of timing resistor a is connected to working power (V+), the crus secunda of timing resistor a is connected to the timing gear of timing switch (BK1), the timing gear of timing switch (BK1) is connected to NAND gate a(IC1 by the lever arm of timing switch (BK1)) the second input, NAND gate b(IC2) first input end and time capacitor a(C1) positive pole, NAND gate a(IC1) first input end be connected to working power (V+), time capacitor a(C1) negative pole be connected to ground wire, NAND gate a(IC1) output be connected to triode a(VT1 by biasing resistor (R15)) base stage, triode a(VT1) emitter be connected to ground wire, triode a(VT1) collector electrode be connected to the crus secunda of charging resistor (R21) and the lever arm of added-time switch (BK2), the lever arm of added-time switch (BK2) is connected to the first pin of timing resistor b by the timing gear of added-time switch (BK2), the crus secunda of timing resistor b is connected to time capacitor b(C4) positive pole and the first pin of isolation resistance (R22), time capacitor b(C4) negative pole be connected to ground wire, the crus secunda of isolation resistance (R22) is connected to NAND gate b(IC2) the second input, NAND gate b(IC2) output be connected to NAND gate c(IC3) two inputs, NAND gate c(IC3) output be connected to drive resistance (R34) the first pin and the first pin of time delay resistance, drive resistance (R34) crus secunda be connected to triode b(VT2) base stage, triode b(VT2) emitter be connected to ground wire, triode b(VT2) collector electrode be connected to the anode of clamp diode (V7) and coil (K) output of relay, coil (K) input of the negative electrode of clamp diode (V7) and relay is connected to working power (V+), the crus secunda of time delay resistance is connected to the timing gear of delay switch (BK3), the timing gear of delay switch (BK3) is connected to NAND gate d(IC4 by the lever arm of delay switch (BK3)) two inputs and the positive pole of delay capacitor (C5), the negative pole of delay capacitor (C5) is connected to ground wire, NAND gate d(IC4) output be connected to the negative electrode of isolating diode (V6), the anodic bonding of isolating diode (V6) is to the crus secunda that drives resistance (R34).

In the utility model, in regular socket circuit, there is discharge diode a(V1), discharge diode b(V5), discharge diode c(V9), discharge resistance (R23) and beginning switch (SB), discharge diode a(V1) anodic bonding to time capacitor a(C1) positive pole, discharge diode b(V5) anodic bonding to time capacitor b(C4) positive pole, discharge diode c(V9) anodic bonding to the positive pole of delay capacitor (C5), discharge diode a(V1) negative electrode, discharge diode b(V5) negative electrode and discharge diode c(V9) negative electrode by discharge resistance (R23) be connected to start switch (SB) first utmost point, second utmost point that starts switch (SB) is connected to ground wire, You Bang road resistance a(R13 between the zero-span of timing switch (BK1) and ground wire), You Bang road resistance (R35) between the zero-span of delay switch (BK3) and ground wire, drive resistance (R34) crus secunda and triode b(VT2) base stage between have indicator light diode (V8), when driving crus secunda and the triode b(VT2 of resistance (R34)) base stage between while having indicator light diode (V8), drive the crus secunda of resistance (R34) to be connected to the anode of indicator light diode (V8), the negative electrode of indicator light diode (V8) is connected to triode b(VT2) base stage, in regular socket circuit, there are two hole socket (CZ1), Three-hole socket (CZ2) and protective earthing interface (G), the phase line socket of two hole socket (CZ1) and Three-hole socket (CZ2) is connected to the phase line interface (L) of power supply by the contact switch (Ka) of relay, the neutral receptacle of two hole socket (CZ1) and Three-hole socket (CZ2) is connected to the zero line interface (N) of power supply, and the ground connection socket of Three-hole socket (CZ2) is connected to protection interface (G).

When concrete enforcement, timing resistor a comprises the first timing resistor a(R1), the second timing resistor a(R2), the 3rd timing resistor a(R3), the 4th timing resistor a(R4), the 5th timing resistor a(R5), the 6th timing resistor a(R6), the 7th timing resistor a(R7), the 8th timing resistor a(R8), the 9th timing resistor a(R9), the tenth timing resistor a(R10), the 11 timing resistor a(R11) and the 12 timing resistor a(R12), the first timing resistor a(R1) to the 12 timing resistor a(R12) resistance increase successively, the diverter switch that timing switch (BK1) is timing start-up, timing switch (BK1) has 13 and switches gear, the first gear is zero-span, the second gear to the 13 gears are timing gear, the first timing resistor a(R1) to the 12 timing resistor a(R12) the first pin parallel connection after be connected to working power (V+), the first timing resistor a(R1) to the 12 timing resistor a(R12) crus secunda be connected to successively in order the first timing gear to the 12 timing gears of timing switch (BK1), the timing start-up time of the first timing gear to the 12 timing gears of timing switch (BK1) increases by five minutes successively, timing resistor b comprises the first timing resistor b(R16), the second timing resistor b(R17), the 3rd timing resistor b(R18), the 4th timing resistor b(R19) and the 5th timing resistor b(R20), the first timing resistor b(R16) to the 5th timing resistor b(R20) resistance increase successively, added-time switch (BK2) is the integral point diverter switch of increase available machine time, added-time switch (BK2) has six and switches gear, the first gear is zero-span, the second gear to the six gears are added-time gear, the first timing resistor b(R16) to the 5th timing resistor b(R20) resistance increase successively, the zero-span of added-time switch (BK2) is directly connected to NAND gate b(IC2) the second input, the first timing resistor b(R16) to the 5th timing resistor b(R20) the first pin the first added-time gear when gear to the slender acanthopanax of being connected to successively in order added-time switch (BK2), the first timing resistor b(R16) to the 5th timing resistor b(R20) crus secunda parallel connection after be connected to time capacitor b(C4) positive pole and the first pin of isolation resistance (R22), the zero-span of added-time switch (BK2), the time of the increase integral point start of the second six added-time of added-time gear to the gear increases by one hour successively, time delay resistance comprises the first time delay resistance (R24), the second time delay resistance (R25), the 3rd time delay resistance (R26), the 4th time delay resistance (R27), the 5th time delay resistance (R28), the 6th time delay resistance (R29), the 7th time delay resistance (R30), the 8th time delay resistance (R31), the 9th time delay resistance (R32) and the tenth time delay resistance (R33), the diverter switch that delay switch (BK3) is delay switching-off, delay switch (BK3) has 11 and switches gear, the first gear is zero-span, the second gear to the 11 gears are timing gear, the first time delay resistance (R24) is connected to NAND gate c(IC3 to the first pin parallel connection of the tenth time delay resistance (R33)) output, the first time delay resistance (R24) to the crus secunda of the tenth time delay resistance (R33) is connected to the first timing gear to the ten timing gears of delay switch (BK3) in order successively, timing switch b(BK2) zero-span, the delay switching-off time of the first timing gear to the ten timing gears increases successively five minutes or is slightly long-time.

When the utility model uses, the zero line interface (N) of the phase line interface (L) of power supply and power supply is connected on power circuit, the electric equipment or the utensil that need timing start-up and delay switching-off are connected on two hole socket (CZ1) or Three-hole socket (CZ2), first click the button that starts switch (SB), carry out zero clearing, timing switch a(BK1) be switched to and need on the time of timing start-up gear, timing switch a(BK1) to have ten second gear timings available, as timing switch a(BK1) on timing when inadequate, again added-time switch (BK2) is switched to the gear that needs to increase the integral point time, it is selective that added-time switch (BK2) has five grades of times integral point added-time, then delay switch (BK3) is switched to and is needed on the time of delay switching-off gear, delay switch (BK3) has ten grades of delay switching-off times selective.When circuit is started working, time capacitor a(C1 in circuit) just start to accept charging, until timing switch a(BK1) set time arrive time, time capacitor a(C1) charging reach the voltage of 2/3 working power (V+), make NAND gate a(IC1) the second input and NAND gate b(IC2) first input end be high level, due to NAND gate a(IC1) first input end be connected to working power (V+), therefore, NAND gate a(IC1) output be reversed to low level, make triode a(VT1) cut-off, triode a(VT1) collector electrode be high level, in the time that added-time switch (BK2) switches in zero-span, triode a(VT1) high level of collector electrode is input to NAND gate b(IC2) the second input, at NAND gate b(IC2) two inputs while being all high level, NAND gate b(IC2) output and NAND gate c(IC3) two inputs be low level, NAND gate c(IC3) output be reversed to high level, NAND gate c(IC3) output high level by drive resistance (R34) and indicator light diode (V8) be input to triode b(VT2) base stage, in lighting indicator light, make triode b(VT2) conducting, coil (K) energising of relay, contact switch (Ka) adhesive of relay, the alternating current of 220V is powered to two hole socket (CZ1) and Three-hole socket (CZ2), electric equipment or utensil are started working, realize timing start-up, NAND gate c(IC3) high level of output charges to delay capacitor (C5) by time delay resistance simultaneously, the delay switching-off time to be set then, the charging of delay capacitor (C5) reaches the voltage of 2/3 working power (V+), make NAND gate d(IC4) input be high level, NAND gate d(IC4) output be reversed to low level, drive voltage on resistance (R34) crus secunda by isolating diode (V6) clamper at NAND gate d(IC4) low level of output, triode b(VT2) cut-off and indicator light extinguish, coil (K) dead electricity of relay, the contact switch (Ka) of relay disconnects, two hole socket (CZ1) and Three-hole socket (CZ2) power-off, realize delay switching-off.In above-mentioned process, as timing switch a(BK1) set time arrive time, while switching on added-time gear as added-time switch (BK2), triode a(VT1) high level of collector electrode by timing resistor b to time capacitor b(C4) charge, in the time arriving time added-time of setting, time capacitor b(C4) charging reach the voltage of 2/3 working power (V+), be input to NAND gate b(IC2 by isolation resistance (R22)) the second input, make NAND gate b(IC2) the second input be high level, at this moment NAND gate b(IC2) first input end be high level, therefore, NAND gate c(IC3) output be reversed to high level, triode b(VT2) conducting, contact switch (Ka) adhesive of relay, the alternating current of 220V is powered to two hole socket (CZ1) and Three-hole socket (CZ2), electric equipment or utensil are started working, realize timing start-up.The secondary timing start-up circuit of the utility model design, one side has increased the time width of timing start-up, has improved on the other hand timing accuracy; After timing start-up, carry out again delay switching-off, can meet the requirement using.

In above-mentioned utility model, regular socket main circuit will be made up of NAND gate, timing start-up time and delay switching-off time are processed and are controlled by NAND gate circuit, NAND gate a(IC1), NAND gate b(IC2), NAND gate c(IC3) and NAND gate d(IC4) use cmos digital integrated circuit, specifically select 42 input nand gate integrated circuits of CC4011 model, the power end of 42 input nand gate integrated circuits is connected to working power (V+), and the earth terminal of 42 input nand gate integrated circuits is connected to ground wire.Cmos digital integrated circuit is a kind of desirable micropower circuit, and interface circuit is simple, the strong anti-interference performance of circuit, and input impedance is high, is generally 10 ⁸Ω, therefore, in timing circuit, the resistance of its timing resistor and the capacitance of time capacitor can be selected enough large, to meet the requirement of long delay, and reliable operation, select the resistance of different timing resistors and the capacitance of time capacitor to make timing start-up time or delay switching-off asynchronism(-nization), in the utility model, timing start-up time or delay switching-off time press t=0.693RC and determine.

The regular socket circuit that the utility model uses NAND gate to form, has advantages of simple in structure and reliable operation, makes wall socket or active socket, can meet cooker and so on living utensil completely to the less demanding timing requirement of timing accuracy; The utility model does not need to use large scale integrated circuit, thereby reduces costs, and its product can be undersold.

The beneficial effects of the utility model are: the regular socket circuit being formed by NAND gate providing, there is the multi-functional of timing and added-time start, delay switching-off, and make regular socket can meet the requirement using in people's life.The utlity model has the simple and low advantage of production cost of circuit structure.

Embodiment

embodimentin execution mode shown in accompanying drawing 1, the regular socket main circuit being made up of NAND gate will be by the phase line interface (L) of power supply, the zero line interface (N) of power supply, buffer resistance (R14), decompression capacitor (C2), rectifier diode a(V2), rectifier diode b(V3), filtering capacitor (C3), voltage stabilizing didoe (V4), timing resistor a, timing switch (BK1), time capacitor a(C1), discharge diode a(V1), discharge resistance (R23), start switch (SB), NAND gate a(IC1), biasing resistor (R15), triode a(VT1), charging resistor (R21), added-time switch (BK2), timing resistor b, time capacitor b(C4), discharge diode b(V5), isolation resistance (R22), NAND gate b(IC2), NAND gate c(IC3), drive resistance (R34), indicator light diode (V8), triode b(VT2), clamp diode (V7), relay, time delay resistance, delay switch (BK3), delay capacitor (C5), discharge diode c(V9), NAND gate d(IC4) and isolating diode (V6) composition, wherein, relay pack vinculum circle (K) and contact switch (Ka), timing switch (BK1), added-time switch (BK2) and delay switch (BK3) have respectively lever arm, timing gear, zero-span, the first pin of decompression capacitor (C2) is connected to the phase line interface (L) of power supply by buffer resistance (R14), the crus secunda of decompression capacitor (C2) is connected to rectifier diode a(V2) negative electrode and rectifier diode b(V3) anode, rectifier diode b(V3) negative electrode be connected to the positive pole of filtering capacitor (C3) and the negative electrode of voltage stabilizing didoe (V4) and form working power (V+), rectifier diode a(V2) anode, the anodic bonding of the negative pole of filtering capacitor (C3) and voltage stabilizing didoe (V4) forms ground wire to the zero line interface (N) of power supply, the first pin of timing resistor a is connected to working power (V+), the crus secunda of timing resistor a is connected to the timing gear of timing switch (BK1), You Bang road resistance a(R13 between the zero-span of timing switch (BK1) and ground wire), the timing gear of timing switch (BK1) is connected to NAND gate a(IC1 by the lever arm of timing switch (BK1)) the second input, NAND gate b(IC2) first input end, time capacitor a(C1) positive pole and discharge diode a(V1) anode, discharge diode a(V1) negative electrode be connected to the first pin of discharge resistance (R23), the crus secunda of discharge resistance (R23) is connected to first utmost point that starts switch (SB), second utmost point that starts switch (SB) is connected to ground wire, NAND gate a(IC1) first input end be connected to working power (V+), time capacitor a(C1) negative pole be connected to ground wire, NAND gate a(IC1) output be connected to triode a(VT1 by biasing resistor (R15)) base stage, triode a(VT1) emitter be connected to ground wire, triode a(VT1) collector electrode be connected to the crus secunda of charging resistor (R21) and the lever arm of added-time switch (BK2), the lever arm of added-time switch (BK2) is connected to the first pin of timing resistor b by the timing gear of added-time switch (BK2), the crus secunda of timing resistor b is connected to time capacitor b(C4) positive pole, discharge diode b(V5) anode and the first pin of isolation resistance (R22), time capacitor b(C4) negative pole be connected to ground wire, discharge diode b(V5) negative electrode be connected to start switch (SB) first utmost point, the crus secunda of isolation resistance (R22) is connected to NAND gate b(IC2) the second input, NAND gate b(IC2) output be connected to NAND gate c(IC3) two inputs, NAND gate c(IC3) output be connected to drive resistance (R34) the first pin and the first pin of time delay resistance, drive the crus secunda of resistance (R34) to be connected to the anode of indicator light diode (V8), the negative electrode of indicator light diode (V8) is connected to triode b(VT2) base stage, triode b(VT2) emitter be connected to ground wire, triode b(VT2) collector electrode be connected to the anode of clamp diode (V7) and coil (K) output of relay, coil (K) input of the negative electrode of clamp diode (V7) and relay is connected to working power (V+), the crus secunda of time delay resistance is connected to the timing gear of delay switch (BK3), You Bang road resistance (R35) between the zero-span of delay switch (BK3) and ground wire, the timing gear of delay switch (BK3) is connected to NAND gate d(IC4 by the lever arm of delay switch (BK3)) two inputs, positive pole and the discharge diode c(V9 of delay capacitor (C5)) anode, the negative pole of delay capacitor (C5) is connected to ground wire, discharge diode c(V9) negative electrode be connected to start switch (SB) first utmost point, NAND gate d(IC4) output be connected to the negative electrode of isolating diode (V6), the anodic bonding of isolating diode (V6) is to the crus secunda that drives resistance (R34).In the present embodiment; in regular socket circuit, there are two hole socket (CZ1), Three-hole socket (CZ2) and protective earthing interface (G); the phase line socket of two hole socket (CZ1) and Three-hole socket (CZ2) is connected to the phase line interface (L) of power supply by the contact switch (Ka) of relay; the neutral receptacle of two hole socket (CZ1) and Three-hole socket (CZ2) is connected to the zero line interface (N) of power supply, and the ground connection socket of Three-hole socket (CZ2) is connected to protection interface (G).

In the above embodiments, timing resistor a comprises the first timing resistor a(R1), the second timing resistor a(R2), the 3rd timing resistor a(R3), the 4th timing resistor a(R4), the 5th timing resistor a(R5), the 6th timing resistor a(R6), the 7th timing resistor a(R7), the 8th timing resistor a(R8), the 9th timing resistor a(R9), the tenth timing resistor a(R10), the 11 timing resistor a(R11) and the 12 timing resistor a(R12), the first timing resistor a(R1) to the 12 timing resistor a(R12) resistance increase successively, the diverter switch that timing switch (BK1) is timing start-up, timing switch (BK1) has 13 and switches gear, the first gear is zero-span, the second gear to the 13 gears are timing gear, the first timing resistor a(R1) to the 12 timing resistor a(R12) the first pin parallel connection after be connected to working power (V+), the first timing resistor a(R1) to the 12 timing resistor a(R12) crus secunda be connected to successively in order the first timing gear to the 12 timing gears of timing switch (BK1), the timing start-up time of the first timing gear to the 12 timing gears of timing switch (BK1) increases by five minutes successively, timing resistor b comprises the first timing resistor b(R16), the second timing resistor b(R17), the 3rd timing resistor b(R18), the 4th timing resistor b(R19) and the 5th timing resistor b(R20), the first timing resistor b(R16) to the 5th timing resistor b(R20) resistance increase successively, added-time switch (BK2) is the integral point diverter switch of increase available machine time, added-time switch (BK2) has six and switches gear, the first gear is zero-span, the second gear to the six gears are added-time gear, the first timing resistor b(R16) to the 5th timing resistor b(R20) resistance increase successively, the zero-span of added-time switch (BK2) is directly connected to NAND gate b(IC2) the second input, the first timing resistor b(R16) to the 5th timing resistor b(R20) the first pin the first added-time gear when gear to the slender acanthopanax of being connected to successively in order added-time switch (BK2), the first timing resistor b(R16) to the 5th timing resistor b(R20) crus secunda parallel connection after be connected to time capacitor b(C4) positive pole and the first pin of isolation resistance (R22), the zero-span of added-time switch (BK2), the time of the increase integral point start of the second six added-time of added-time gear to the gear increases by one hour successively, time delay resistance comprises the first time delay resistance (R24), the second time delay resistance (R25), the 3rd time delay resistance (R26), the 4th time delay resistance (R27), the 5th time delay resistance (R28), the 6th time delay resistance (R29), the 7th time delay resistance (R30), the 8th time delay resistance (R31), the 9th time delay resistance (R32) and the tenth time delay resistance (R33), the diverter switch that delay switch (BK3) is delay switching-off, delay switch (BK3) has 11 and switches gear, the first gear is zero-span, the second gear to the 11 gears are timing gear, the first time delay resistance (R24) is connected to NAND gate c(IC3 to the first pin parallel connection of the tenth time delay resistance (R33)) output, the first time delay resistance (R24) to the crus secunda of the tenth time delay resistance (R33) is connected to the first timing gear to the ten timing gears of delay switch (BK3) in order successively, timing switch b(BK2) zero-span, the delay switching-off time of the first timing gear to the ten timing gears increases successively five minutes or is slightly long-time.

In the above embodiments, regular socket main circuit will be made up of NAND gate, timing start-up time and delay switching-off time are processed and are controlled by NAND gate circuit, NAND gate a(IC1), NAND gate b(IC2), NAND gate c(IC3) and NAND gate d(IC4) use cmos digital integrated circuit, specifically select 42 input nand gate integrated circuits of CC4011 model, the power end of 42 input nand gate integrated circuits is connected to working power (V+), and the earth terminal of 42 input nand gate integrated circuits is connected to ground wire.Cmos digital integrated circuit is a kind of desirable micropower circuit, and interface circuit is simple, the strong anti-interference performance of circuit, and input impedance is high, is generally 10 ⁸Ω, therefore, in timing circuit, the resistance of its timing resistor and the capacitance of time capacitor can be selected enough large, to meet the requirement of long delay, and reliable operation, select the resistance of different timing resistors and the capacitance of time capacitor to make timing start-up time or delay switching-off asynchronism(-nization), in the present embodiment, timing start-up time or delay switching-off time press t=0.693RC and determine.

When the above embodiments are used, the zero line interface (N) of the phase line interface (L) of power supply and power supply is connected on power circuit, the electric equipment or the utensil that need timing start-up and delay switching-off are connected on two hole socket (CZ1) or Three-hole socket (CZ2), first click the button that starts switch (SB), carry out zero clearing, timing switch a(BK1) be switched to and need on the time of timing start-up gear, timing switch a(BK1) to have ten second gear timings available, as timing switch a(BK1) on timing when inadequate, again added-time switch (BK2) is switched to the gear that needs to increase the integral point time, it is selective that added-time switch (BK2) has five grades of times integral point added-time, then delay switch (BK3) is switched to and is needed on the time of delay switching-off gear, delay switch (BK3) has ten grades of delay switching-off times selective.When circuit is started working, time capacitor a(C1 in circuit) just start to accept charging, until timing switch a(BK1) set time arrive time, time capacitor a(C1) charging reach the voltage of 2/3 working power (V+), make NAND gate a(IC1) the second input and NAND gate b(IC2) first input end be high level, due to NAND gate a(IC1) first input end be connected to working power (V+), therefore, NAND gate a(IC1) output be reversed to low level, make triode a(VT1) cut-off, triode a(VT1) collector electrode be high level, in the time that added-time switch (BK2) switches in zero-span, triode a(VT1) high level of collector electrode is input to NAND gate b(IC2) the second input, NAND gate b(IC2) two inputs while being all high level, NAND gate b(IC2) output and NAND gate c(IC3) two inputs be low level, NAND gate c(IC3) output be reversed to high level, NAND gate c(IC3) output high level by drive resistance (R34) and indicator light diode (V8) be input to triode b(VT2) base stage, in lighting indicator light, make triode b(VT2) conducting, coil (K) energising of relay, contact switch (Ka) adhesive of relay, the alternating current of 220V is powered to two hole socket (CZ1) and Three-hole socket (CZ2), electric equipment or utensil are started working, realize timing start-up, NAND gate c(IC3) high level of output charges to delay capacitor (C5) by time delay resistance simultaneously, the delay switching-off time to be set then, the charging of delay capacitor (C5) reaches the voltage of 2/3 working power (V+), make NAND gate d(IC4) input be high level, NAND gate d(IC4) output be reversed to low level, make to drive voltage on resistance (R34) crus secunda by isolating diode (V6) clamper at NAND gate d(IC4) low level of output, triode b(VT2) cut-off and indicator light extinguish, coil (K) dead electricity of relay, the contact switch (Ka) of relay disconnects, two hole socket (CZ1) and Three-hole socket (CZ2) power-off, realize delay switching-off.Until timing switch a(BK1) set time arrive time, while switching on added-time gear as added-time switch (BK2), triode a(VT1) high level of collector electrode by timing resistor b to time capacitor b(C4) charge, in the time arriving time added-time of setting, time capacitor b(C4) charging reach the voltage of 2/3 working power (V+), be input to NAND gate b(IC2 by isolation resistance (R22)) the second input, make NAND gate b(IC2) the second input be high level, at this moment NAND gate b(IC2) first input end be high level, therefore, make NAND gate c(IC3) output be reversed to high level, triode b(VT2) conducting, contact switch (Ka) adhesive of relay, the alternating current of 220V is powered to two hole socket (CZ1) and Three-hole socket (CZ2), electric equipment or utensil are started working, realize timing start-up.The secondary timing start-up circuit of the present embodiment design, one side has increased the time width of timing start-up, has improved on the other hand timing accuracy; After timing start-up, carry out again delay switching-off, can meet the requirement using.

Brief description of the drawings

Accompanying drawing 1 is the regular socket circuit diagram being made up of NAND gate of the present utility model.

In figure: R1～R12. the first timing resistor a～ten timing resistor a, R13. be close to road resistance a, R14. buffer resistance, R15. biasing resistor, R16～R20. the first timing resistor b～five timing resistor b, R21. charging resistor, R22. isolation resistance, R23. discharge resistance, R24～R33. the first time delay resistance～ten time delay resistance, R34. drive resistance, R35. be close to road resistance, C1. time capacitor a, C2. decompression capacitor, C3. filtering capacitor, C4. time capacitor b, C5. delay capacitor, V1. discharge diode a, V2. rectifier diode a, V3. rectifier diode b, V4. voltage stabilizing didoe, V5. discharge diode b, V6. isolating diode, V7. clamp diode, V8. indicator light diode, V9. discharge diode c, VT1. triode a, VT2. triode b, V+. working power, IC1. NAND gate a, IC2. NAND gate b, IC3. NAND gate c, IC4. NAND gate d, K. the coil of relay, Ka. the contact switch of relay, BK1. timing switch, BK2. added-time switch, BK3. delay switch, SB. start switch, CZ1. two hole socket, CZ2. Three-hole socket, L. the phase line interface of power supply, N. the zero line interface of power supply, G. protect interface.

Claims

1. the regular socket circuit being made up of NAND gate, is characterized in that regular socket main circuit will be by the phase line interface (L) of power supply, the zero line interface (N) of power supply, buffer resistance (R14), decompression capacitor (C2), rectifier diode a(V2), rectifier diode b(V3), filtering capacitor (C3), voltage stabilizing didoe (V4), timing resistor a, timing switch (BK1), time capacitor a(C1), NAND gate a(IC1), biasing resistor (R15), triode a(VT1), charging resistor (R21), added-time switch (BK2), timing resistor b, time capacitor b(C4), isolation resistance (R22), NAND gate b(IC2), NAND gate c(IC3), drive resistance (R34), triode b(VT2), clamp diode (V7), relay, time delay resistance, delay switch (BK3), delay capacitor (C5), NAND gate d(IC4) and isolating diode (V6) composition, wherein, relay pack vinculum circle (K) and contact switch (Ka), timing switch (BK1), added-time switch (BK2) and delay switch (BK3) have respectively lever arm, timing gear, zero-span,

The first pin of decompression capacitor (C2) is connected to the phase line interface (L) of power supply by buffer resistance (R14), the crus secunda of decompression capacitor (C2) is connected to rectifier diode a(V2) negative electrode and rectifier diode b(V3) anode, rectifier diode b(V3) negative electrode be connected to the positive pole of filtering capacitor (C3) and the negative electrode of voltage stabilizing didoe (V4) and form working power (V+), rectifier diode a(V2) anode, the anodic bonding of the negative pole of filtering capacitor (C3) and voltage stabilizing didoe (V4) forms ground wire to the zero line interface (N) of power supply,

The first pin of timing resistor a is connected to working power (V+), the crus secunda of timing resistor a is connected to the timing gear of timing switch (BK1), the timing gear of timing switch (BK1) is connected to NAND gate a(IC1 by the lever arm of timing switch (BK1)) the second input, NAND gate b(IC2) first input end and time capacitor a(C1) positive pole, NAND gate a(IC1) first input end be connected to working power (V+), time capacitor a(C1) negative pole be connected to ground wire, NAND gate a(IC1) output be connected to triode a(VT1 by biasing resistor (R15)) base stage, triode a(VT1) emitter be connected to ground wire, triode a(VT1) collector electrode be connected to the crus secunda of charging resistor (R21) and the lever arm of added-time switch (BK2), the lever arm of added-time switch (BK2) is connected to the first pin of timing resistor b by the timing gear of added-time switch (BK2), the crus secunda of timing resistor b is connected to time capacitor b(C4) positive pole and the first pin of isolation resistance (R22), time capacitor b(C4) negative pole be connected to ground wire, the crus secunda of isolation resistance (R22) is connected to NAND gate b(IC2) the second input, NAND gate b(IC2) output be connected to NAND gate c(IC3) two inputs, NAND gate c(IC3) output be connected to drive resistance (R34) the first pin and the first pin of time delay resistance, drive resistance (R34) crus secunda be connected to triode b(VT2) base stage, triode b(VT2) emitter be connected to ground wire, triode b(VT2) collector electrode be connected to the anode of clamp diode (V7) and coil (K) output of relay, coil (K) input of the negative electrode of clamp diode (V7) and relay is connected to working power (V+),

The crus secunda of time delay resistance is connected to the timing gear of delay switch (BK3), the timing gear of delay switch (BK3) is connected to NAND gate d(IC4 by the lever arm of delay switch (BK3)) two inputs and the positive pole of delay capacitor (C5), the negative pole of delay capacitor (C5) is connected to ground wire, NAND gate d(IC4) output be connected to the negative electrode of isolating diode (V6), the anodic bonding of isolating diode (V6) is to the crus secunda that drives resistance (R34).

2. a kind of regular socket circuit being formed by NAND gate according to claim 1, it is characterized in that in regular socket circuit, there is discharge diode a(V1), discharge diode b(V5), discharge diode c(V9), discharge resistance (R23) and beginning switch (SB), discharge diode a(V1) anodic bonding to time capacitor a(C1) positive pole, discharge diode b(V5) anodic bonding to time capacitor b(C4) positive pole, discharge diode c(V9) anodic bonding to the positive pole of delay capacitor (C5), discharge diode a(V1) negative electrode, discharge diode b(V5) negative electrode and discharge diode c(V9) negative electrode by discharge resistance (R23) be connected to start switch (SB) first utmost point, second utmost point that starts switch (SB) is connected to ground wire.

3. a kind of regular socket circuit being made up of NAND gate according to claim 1, is characterized in that You Bang road resistance a(R13 between the zero-span of timing switch (BK1) and ground wire); You Bang road resistance (R35) between the zero-span of delay switch (BK3) and ground wire.

4. a kind of regular socket circuit being formed by NAND gate according to claim 1, it is characterized in that drive resistance (R34) crus secunda and triode b(VT2) base stage between have indicator light diode (V8), when driving crus secunda and the triode b(VT2 of resistance (R34)) base stage between while having indicator light diode (V8), drive the crus secunda of resistance (R34) to be connected to the anode of indicator light diode (V8), the negative electrode of indicator light diode (V8) is connected to triode b(VT2) base stage.

5. a kind of regular socket circuit being formed by NAND gate according to claim 1; it is characterized in that in regular socket circuit, having two hole socket (CZ1), Three-hole socket (CZ2) and protective earthing interface (G); the phase line socket of two hole socket (CZ1) and Three-hole socket (CZ2) is connected to the phase line interface (L) of power supply by the contact switch (Ka) of relay; the neutral receptacle of two hole socket (CZ1) and Three-hole socket (CZ2) is connected to the zero line interface (N) of power supply, and the ground connection socket of Three-hole socket (CZ2) is connected to protection interface (G).