CN203968087U

CN203968087U - A kind of plesichronous socket circuit being formed by not gate

Info

Publication number: CN203968087U
Application number: CN201420415038.0U
Authority: CN
Inventors: 蒋小芳
Original assignee: Quzhou Disheng Industrial Design Co Ltd
Current assignee: Quzhou Disheng Industrial Design Co Ltd
Priority date: 2014-07-28
Filing date: 2014-07-28
Publication date: 2014-11-26
Anticipated expiration: 2024-07-28

Abstract

A kind of plesichronous socket circuit being formed by not gate, relate to a kind of electronic timing circuit, by buffer resistance, decompression capacitor, rectifier diode, filtering capacitor, voltage stabilizing didoe, timing resistor a, timing switch a, time capacitor a, not gate a～not gate f, isolating diode, timing resistor b, timing switch b, time capacitor b, driving resistance, triode and relay, formed.The crus secunda of timing resistor a is connected to the positive pole of time capacitor a and the input of not gate a by timing switch a, the output of not gate a is connected to the input of not gate c and the first pin of timing resistor b by not gate b, the output of not gate c is connected to the anode of isolating diode, the negative electrode of isolating diode is by not gate d and drive resistance to be connected to the base stage of triode, and the collector electrode of triode is connected to the coil output of relay.The utlity model has the dual-use function of timing start-up and delay switching-off, make regular socket can meet the requirement of using in people's life.

Description

A kind of plesichronous socket circuit being formed by not gate

Technical field

The utility model relates to electronic circuit, specially refers to a kind of electronic timing circuit.

Background technology

In people's live and work, often use timer, timer makes to need the work in people's control time to become simply many, also to people, bring great convenience, as utilize timer to switch on power and cook at the time chien shih electric cooker of setting, people just can be had a dinner coming home from work, save time.But general timer only has on-delay type timer or off delay type timer, function singleness, can not meet the instructions for use that needs to need again after timing start-up delay switching-off; The structure of programmable timer is by CPU (CPU) as processing and control axis, and circuit structure complexity and cost are high, and its product price is higher, many, will cause waste during to the less demanding applications of timing accuracy.

Utility model content

The purpose of this utility model is will provide a kind of circuit structure simply and the low plesichronous socket circuit consisting of not gate of cost, has the dual-use function of timing start-up and delay switching-off, makes regular socket can meet the requirement of using in people's life.

A kind of plesichronous socket circuit being formed by not gate of the present utility model, it is characterized in that regular socket main circuit will be by the phase line interface (L) of power supply, the zero line interface (N) of power supply, buffer resistance (R12), decompression capacitor (C2), rectifier diode a(V2), rectifier diode b(V3), filtering capacitor (C3), voltage stabilizing didoe (V4), timing resistor a, timing switch a(BK1), time capacitor a(C1), not gate a(IC1), not gate b(IC2), not gate c(IC3), isolating diode a(V6), timing resistor b, timing switch b(BK2), time capacitor b(C4), not gate f(IC6), not gate e(IC5), isolating diode b(V7), not gate d(IC4), drive resistance (R25), triode (VT), clamp diode (V8) and relay form, relay pack vinculum circle (K) and contact switch (Ka), timing switch a(BK1) and timing switch b(BK2) have respectively regularly gear, a zero-span, wherein: the first pin of decompression capacitor (C2) is connected to the phase line interface (L) of power supply by buffer resistance (R12), the crus secunda of decompression capacitor (C2) is connected to rectifier diode a(V2) negative electrode and rectifier diode b(V3) anode, rectifier diode b(V3) negative electrode is connected to the positive pole of filtering capacitor (C3) and the negative electrode of voltage stabilizing didoe (V4) and forms working power (V+), rectifier diode a(V2) anode, the anodic bonding of the negative pole of filtering capacitor (C3) and voltage stabilizing didoe (V4) forms ground wire to the zero line interface (N) of power supply, the first pin of timing resistor a is connected to working power (V+), the crus secunda of timing resistor a is by timing switch a(BK1) timing gear be connected to time capacitor a(C1) positive pole and not gate a(IC1) input, time capacitor a(C1) negative pole is connected to ground wire, not gate a(IC1) output is connected to not gate b(IC2) input, not gate b(IC2) output is connected to not gate c(IC3) input and the first pin of timing resistor b, not gate c(IC3) output be connected to isolating diode a(V6) anode, the crus secunda of timing resistor b is by timing switch b(BK2) timing gear be connected to time capacitor b(C4) positive pole and not gate f(IC6) input, time capacitor b(C4) negative pole is connected to ground wire, not gate f(IC6) output is connected to not gate e(IC5) input, not gate e(IC5) output is connected to isolating diode b(V7) anode, isolating diode b(V7) negative electrode and isolating diode a(V6) negative electrode be connected to not gate d(IC4) input, not gate d(IC4) output is connected to the first pin that drives resistance (R25), the crus secunda of driving resistance (R25) is connected to the base stage of triode (VT), the emitter of triode (VT) is connected to ground wire, the collector electrode of triode (VT) is connected to the anode of clamp diode (V8) and coil (K) output of relay, coil (K) input of the negative electrode of clamp diode (V8) and relay is connected to working power (V+).

In the utility model, not gate a(IC1) in input circuit, have discharge resistance a(R13), discharge diode a(V1) and start switch (SB), discharge resistance a(R13) the first pin is connected to not gate a(IC1) input, discharge resistance a(R13) crus secunda is connected to discharge diode a(V1) anode, discharge diode a(V1) negative electrode is connected to first utmost point that starts switch (SB), and second utmost point that starts switch (SB) is connected to ground wire; At not gate f(IC6) input and start there is discharge resistance b(R27 between first utmost point of switch (SB)) and discharge diode b(V5), discharge resistance b(R27) the first pin is connected to not gate f(IC6) input, discharge resistance b(R27) crus secunda is connected to discharge diode b(V5) anode, discharge diode b(V5) negative electrode be connected to first utmost point that starts switch (SB); At timing switch a(BK1) zero-span and ground wire between You Bang road resistance a(R11); At timing switch b(BK2) zero-span and ground wire between You Bang road resistance c(R26); At not gate d(IC4) input and ground wire between You Bang road resistance b(R24); There is indicator light diode (V9) driving between the crus secunda of resistance (R25) and the base stage of triode (VT), when having indicator light diode (V9) between the crus secunda at driving resistance (R25) and the base stage of triode (VT), the crus secunda of driving resistance (R25) is connected to the anode of indicator light diode (V9), and the negative electrode of indicator light diode (V9) is connected to the base stage of triode (VT); In regular socket circuit, there are two hole socket (CZ1), Three-hole socket (CZ2) and protective earthing interface (G); the phase line socket of two hole socket (CZ1) and Three-hole socket (CZ2) is connected to the phase line interface (L) of power supply by the contact switch (Ka) of relay; the neutral receptacle of two hole socket (CZ1) and Three-hole socket (CZ2) is connected to the zero line interface (N) of power supply, and the ground connection socket of Three-hole socket (CZ2) is connected to protection interface (G).

During concrete enforcement, timing resistor a comprises the first timing resistor a(R1)～the tenth timing resistor a(R10) totally ten, the first timing resistor a(R1)～the tenth resistance timing resistor a(R10) increases successively, timing switch a(BK1) be the diverter switch of timing start-up, timing switch a(BK1) there are 11 and switch gear, the first gear is zero-span, the second gear～11 gear is regularly gear, the first timing resistor a(R1)～the tenth after the first pin parallel connection timing resistor a(R10), be connected to working power (V+), the first timing resistor a(R1)～the tenth crus secunda timing resistor a(R10) is connected to timing switch a(BK1 in order successively) the first gear～ten gear regularly regularly, timing switch a(BK1) regularly the timing start-up time of gear increases the first timing gear～ten successively, timing resistor b comprises the first timing resistor b(R14)～the tenth timing resistor b(R23) totally ten, the first timing resistor b(R14)～the tenth resistance timing resistor b(R23) increases successively, timing switch b(BK2) be the diverter switch of delay switching-off, timing switch b(BK2) there are 11 and switch gear, the first gear is zero-span, the second gear～11 gear is regularly gear, the first timing resistor b(R14)～the tenth after the first pin parallel connection timing resistor b(R23), be connected to not gate b(IC2) output, the first timing resistor b(R14)～the tenth crus secunda timing resistor b(R23) is connected to timing switch b(BK2 in order successively) the first gear～ten gear regularly regularly, timing switch b(BK2) regularly the delay switching-off time of gear increases the first timing gear～ten successively.

When the utility model is used, the zero line interface (N) of the phase line interface (L) of power supply and power supply is connected on power circuit, needing electric equipment or the utensil of timing start-up and delay switching-off to be connected on two hole socket (CZ1) or Three-hole socket (CZ2), first click the button that starts switch (SB), carry out zero clearing, again timing switch a(BK1) be switched to and need on the time of timing start-up gear, timing switch b(BK2) be switched to and need on the time of delay switching-off gear, time capacitor a(C1 in circuit) just start to accept charging, available machine time to be set then, time capacitor a(C1) charging reaches the voltage of 2/3 working power (V+), make not gate a(IC1) input be high level, not gate a(IC1) output and not gate b(IC2) input be low level, not gate b(IC2) output is reversed to high level, high level by timing resistor b to time capacitor b(C4) charge, simultaneously, not gate b(IC2) high level of output is input to not gate c(IC3) input, make not gate d(IC4) output be reversed to high level, high level is by driving resistance (R25) and indicator light diode (V9) to be input to the base stage of triode (VT), when lighting indicator light, make triode (VT) conducting, the coil of relay (K) energising, the contact switch of relay (Ka) adhesive, the alternating current of 220V is powered to two hole socket (CZ1) and Three-hole socket (CZ2), electric equipment or utensil are started working, realized timing start-up, the delay switching-off time to be set then, time capacitor b(C4) charging reaches the voltage of 2/3 working power (V+), make not gate f(IC6) input be high level, not gate e(IC5) output is all high level, not gate e(IC5) high level of output is by isolating diode b(V7) be input to not gate d(IC4) input, make not gate d(IC4) output be reversed to low level, triode (VT) cut-off and indicator light extinguish, the coil of relay (K) dead electricity, the contact switch of relay (Ka) disconnects, two hole socket (CZ1) and Three-hole socket (CZ2) power-off, realized delay switching-off.

In above-mentioned utility model, plesichronous socket circuit mainly consists of not gate, timing start-up time and delay switching-off time are processed and are controlled by not circuit, not gate a(IC1), not gate b(IC2), not gate c(IC3), not gate d(IC4), not gate e(IC5) and not gate f(IC6) use cmos digital integrated circuit, specifically select the hex inverter integrated circuit of CC4069 model, the power end of hex inverter integrated circuit is connected to working power (V+), and the earth terminal of hex inverter integrated circuit is connected to ground wire.Cmos digital integrated circuit is a kind of desirable micropower circuit, and interface circuit is simple, the strong anti-interference performance of circuit, and input impedance is high, is generally 10 ⁸Ω, therefore, in timing circuit, the resistance of its timing resistor and the capacitance of time capacitor can be selected enough large, to meet the requirement of long delay, and reliable operation, select the resistance of different timing resistors and the capacitance of time capacitor to make timing start-up time or delay switching-off asynchronism(-nization), in the utility model, timing start-up time or delay switching-off time press t=0.693RC and determine.

The plesichronous socket circuit that the utility model is used not gate to form, has advantages of simple in structure and reliable operation, makes wall socket or active socket, can meet cooker and so on living utensil completely to the less demanding timing requirement of timing accuracy; The utility model does not need to use large scale integrated circuit, thereby reduces costs, and its product can be undersold.

The beneficial effects of the utility model are: a kind of plesichronous socket circuit being formed by not gate providing, there is the dual-use function of timing start-up and delay switching-off, and make regular socket can meet the requirement of using in people's life.The utlity model has the simple and low advantage of production cost of circuit structure.

Embodiment

embodimentin execution mode shown in accompanying drawing 1, a kind of plesichronous socket circuit consisting of not gate is mainly by the phase line interface (L) of power supply, the zero line interface (N) of power supply, buffer resistance (R12), decompression capacitor (C2), rectifier diode a(V2), rectifier diode b(V3), filtering capacitor (C3), voltage stabilizing didoe (V4), timing resistor a, timing switch a(BK1), time capacitor a(C1), discharge resistance a(R13), discharge diode a(V1), start switch (SB), not gate a(IC1), not gate b(IC2), not gate c(IC3), isolating diode a(V6), timing resistor b, timing switch b(BK2), time capacitor b(C4), discharge resistance b(R27), discharge diode b(V5), not gate f(IC6), not gate e(IC5), isolating diode b(V7), not gate d(IC4), drive resistance (R25), indicator light diode (V9), triode (VT), clamp diode (V8) and relay form, relay pack vinculum circle (K) and contact switch (Ka), timing switch a(BK1) and timing switch b(BK2) have respectively regularly gear, a zero-span, the first pin of decompression capacitor (C2) is connected to the phase line interface (L) of power supply by buffer resistance (R12), the crus secunda of decompression capacitor (C2) is connected to rectifier diode a(V2) negative electrode and rectifier diode b(V3) anode, rectifier diode b(V3) negative electrode is connected to the positive pole of filtering capacitor (C3) and the negative electrode of voltage stabilizing didoe (V4) and forms working power (V+), rectifier diode a(V2) anode, the anodic bonding of the negative pole of filtering capacitor (C3) and voltage stabilizing didoe (V4) forms ground wire to the zero line interface (N) of power supply, the first pin of timing resistor a is connected to working power (V+), the crus secunda of timing resistor a is by timing switch a(BK1) timing gear be connected to time capacitor a(C1) positive pole, discharge resistance a(R13) the first pin and not gate a(IC1) input, at timing switch a(BK1) zero-span and ground wire between You Bang road resistance a(R11), time capacitor a(C1) negative pole is connected to ground wire, discharge resistance a(R13) crus secunda is connected to discharge diode a(V1) anode, discharge diode a(V1) negative electrode is connected to first utmost point that starts switch (SB), second utmost point that starts switch (SB) is connected to ground wire, not gate a(IC1) output is connected to not gate b(IC2) input, not gate b(IC2) output is connected to not gate c(IC3) input and the first pin of timing resistor b, not gate c(IC3) output is connected to isolating diode a(V6) anode, the crus secunda of timing resistor b is by timing switch b(BK2) timing gear be connected to time capacitor b(C4) positive pole, discharge resistance b(R27) the first pin and not gate f(IC6) input, at timing switch b(BK2) zero-span and ground wire between You Bang road resistance c(R26), time capacitor b(C4) negative pole is connected to ground wire, discharge resistance b(R27) crus secunda is connected to discharge diode b(V5) anode, discharge diode b(V5) negative electrode is connected to first utmost point that starts switch (SB), not gate f(IC6) output is connected to not gate e(IC5) input, not gate e(IC5) output is connected to isolating diode b(V7) anode, isolating diode b(V7) negative electrode and isolating diode a(V6) negative electrode be connected to not gate d(IC4) input, at not gate d(IC4) input and ground wire between You Bang road resistance b(R24), not gate d(IC4) output is connected to the first pin that drives resistance (R25), the crus secunda of driving resistance (R25) is connected to the anode of indicator light diode (V9), the negative electrode of indicator light diode (V9) is connected to the base stage of triode (VT), the emitter of triode (VT) is connected to ground wire, the collector electrode of triode (VT) is connected to the anode of clamp diode (V8) and coil (K) output of relay, coil (K) input of the negative electrode of clamp diode (V8) and relay is connected to working power (V+).In the present embodiment, there are two hole socket (CZ1), Three-hole socket (CZ2) and protective earthing interface (G); the phase line socket of two hole socket (CZ1) and Three-hole socket (CZ2) is connected to the phase line interface (L) of power supply by the contact switch (Ka) of relay; the neutral receptacle of two hole socket (CZ1) and Three-hole socket (CZ2) is connected to the zero line interface (N) of power supply, and the ground connection socket of Three-hole socket (CZ2) is connected to protection interface (G).

In the above embodiments, timing resistor a comprises the first timing resistor a(R1)～the tenth timing resistor a(R10) totally ten, the first timing resistor a(R1)～the tenth resistance timing resistor a(R10) increases successively, timing switch a(BK1) be the diverter switch of timing start-up, timing switch a(BK1) there are 11 and switch gear, the first gear is zero-span, the second gear～11 gear is regularly gear, the first timing resistor a(R1)～the tenth after the first pin parallel connection timing resistor a(R10), be connected to working power (V+), the first timing resistor a(R1)～the tenth crus secunda timing resistor a(R10) is connected to timing switch a(BK1 in order successively) the first gear～ten gear regularly regularly, timing switch a(BK1) regularly the timing start-up time of gear increases the first timing gear～ten successively, timing resistor b comprises the first timing resistor b(R14)～the tenth timing resistor b(R23) totally ten, the first timing resistor b(R14)～the tenth resistance timing resistor b(R23) increases successively, timing switch b(BK2) be the diverter switch of delay switching-off, timing switch b(BK2) there are 11 and switch gear, the first gear is zero-span, the second gear～11 gear is regularly gear, the first timing resistor b(R14)～the tenth after the first pin parallel connection timing resistor b(R23), be connected to not gate b(IC2) output, the first timing resistor b(R14)～the tenth crus secunda timing resistor b(R23) is connected to timing switch b(BK2 in order successively) the first gear～ten gear regularly regularly, timing switch b(BK2) regularly the delay switching-off time of gear increases the first timing gear～ten successively, timing start-up time or delay switching-off time press t=0.693RC and determine, not gate a(IC1), not gate b(IC2), not gate c(IC3), not gate d(IC4), not gate e(IC5) and not gate f(IC6) use cmos digital integrated circuit, specifically select the hex inverter integrated circuit of CC4069 model, the power end of hex inverter integrated circuit is connected to working power (V+), and the earth terminal of hex inverter integrated circuit is connected to ground wire.

When the present embodiment is used, the zero line interface (N) of the phase line interface (L) of power supply and power supply is connected on power circuit, needing electric equipment or the utensil of timing start-up and delay switching-off to be connected on two hole socket (CZ1) or Three-hole socket (CZ2), first click the button that starts switch (SB), carry out zero clearing, again timing switch a(BK1) be switched to and need on the time of timing start-up gear, timing switch b(BK2) be switched to and need on the time of delay switching-off gear, time capacitor a(C1 in circuit) just start to accept charging, available machine time to be set then, time capacitor a(C1) charging reaches the voltage of 2/3 working power (V+), make not gate a(IC1) input be high level, not gate a(IC1) output and not gate b(IC2) input be low level, not gate b(IC2) output is reversed to high level, high level by timing resistor b to time capacitor b(C4) charge, simultaneously, not gate b(IC2) high level of output is input to not gate c(IC3) input, make not gate d(IC4) output be reversed to high level, high level is by driving resistance (R25) and indicator light diode (V9) to be input to the base stage of triode (VT), when lighting indicator light, make triode (VT) conducting, the coil of relay (K) energising, the contact switch of relay (Ka) adhesive, the alternating current of 220V is powered to two hole socket (CZ1) and Three-hole socket (CZ2), electric equipment or utensil are started working, realized timing start-up, the delay switching-off time to be set then, time capacitor b(C4) charging reaches the voltage of 2/3 working power (V+), make not gate f(IC6) input be high level, not gate e(IC5) output is all high level, not gate e(IC5) high level of output is by isolating diode b(V7) be input to not gate d(IC4) input, make not gate d(IC4) output be reversed to low level, triode (VT) cut-off and indicator light extinguish, the coil of relay (K) dead electricity, the contact switch of relay (Ka) disconnects, two hole socket (CZ1) and Three-hole socket (CZ2) power-off, realized delay switching-off.

Accompanying drawing explanation

Accompanying drawing 1 is a kind of plesichronous socket circuit figure consisting of not gate of the present utility model.

In figure: R1～R10. the first timing resistor a～ten timing resistor a, R11. be close to road resistance a, R12. buffer resistance, R13. discharge resistance a, R14～R23. the first timing resistor b～ten timing resistor b, R24. be close to road resistance b, R25. drive resistance, R26. be close to road resistance c, R27. discharge resistance b, C1. time capacitor a, C2. decompression capacitor, C3. filtering capacitor, C4. time capacitor b, V1. discharge diode a, V2. rectifier diode a, V3. rectifier diode b, V4. voltage stabilizing didoe, V5. discharge diode b, V6. isolating diode a, V7. isolating diode b, V8. clamp diode, V9. indicator light diode, VT. triode, V+. working power, IC1. not gate a, IC2. not gate b, IC3. not gate c, IC4. not gate d, IC5. not gate e, IC6. not gate f, K. the coil of relay, Ka. the contact switch of relay, BK1. timing switch a, BK2. timing switch b, SB. start switch, CZ1. two hole socket, CZ2. Three-hole socket, L. the phase line interface of power supply, N. the zero line interface of power supply, G. protect interface.

Claims

1. the plesichronous socket circuit being formed by not gate, it is characterized in that regular socket main circuit will be by the phase line interface (L) of power supply, the zero line interface (N) of power supply, buffer resistance (R12), decompression capacitor (C2), rectifier diode a(V2), rectifier diode b(V3), filtering capacitor (C3), voltage stabilizing didoe (V4), timing resistor a, timing switch a(BK1), time capacitor a(C1), not gate a(IC1), not gate b(IC2), not gate c(IC3), isolating diode a(V6), timing resistor b, timing switch b(BK2), time capacitor b(C4), not gate e(IC5), not gate f(IC6), isolating diode b(V7), not gate d(IC4), drive resistance (R25), triode (VT), clamp diode (V8) and relay form, relay pack vinculum circle (K) and contact switch (Ka), timing switch a(BK1) and timing switch b(BK2) have respectively regularly gear, a zero-span, wherein:

The first pin of decompression capacitor (C2) is connected to the phase line interface (L) of power supply by buffer resistance (R12), the crus secunda of decompression capacitor (C2) is connected to rectifier diode a(V2) negative electrode and rectifier diode b(V3) anode, rectifier diode b(V3) negative electrode is connected to the positive pole of filtering capacitor (C3) and the negative electrode of voltage stabilizing didoe (V4) and forms working power (V+), rectifier diode a(V2) anode, the anodic bonding of the negative pole of filtering capacitor (C3) and voltage stabilizing didoe (V4) forms ground wire to the zero line interface (N) of power supply,

The first pin of timing resistor a is connected to working power (V+), the crus secunda of timing resistor a is by timing switch a(BK1) timing gear be connected to time capacitor a(C1) positive pole and not gate a(IC1) input, time capacitor a(C1) negative pole is connected to ground wire, not gate a(IC1) output is connected to not gate b(IC2) input, not gate b(IC2) output is connected to not gate c(IC3) input and the first pin of timing resistor b, not gate c(IC3) output be connected to isolating diode a(V6) anode, the crus secunda of timing resistor b is by timing switch b(BK2) timing gear be connected to time capacitor b(C4) positive pole and not gate f(IC6) input, time capacitor b(C4) negative pole is connected to ground wire, not gate f(IC6) output is connected to not gate e(IC5) input, not gate e(IC5) output is connected to isolating diode b(V7) anode, isolating diode b(V7) negative electrode and isolating diode a(V6) negative electrode be connected to not gate d(IC4) input, not gate d(IC4) output is connected to the first pin that drives resistance (R25), the crus secunda of driving resistance (R25) is connected to the base stage of triode (VT), the emitter of triode (VT) is connected to ground wire, the collector electrode of triode (VT) is connected to the anode of clamp diode (V8) and coil (K) output of relay, coil (K) input of the negative electrode of clamp diode (V8) and relay is connected to working power (V+).

2. a kind of plesichronous socket circuit being formed by not gate according to claim 1, it is characterized in that not gate a(IC1) input circuit in have discharge resistance a(R13), discharge diode a(V1) and start switch (SB), discharge resistance a(R13) the first pin is connected to not gate a(IC1) input, discharge resistance a(R13) crus secunda is connected to discharge diode a(V1) anode, discharge diode a(V1) negative electrode is connected to first utmost point that starts switch (SB), and second utmost point that starts switch (SB) is connected to ground wire; At not gate f(IC6) input and start there is discharge resistance b(R27 between first utmost point of switch (SB)) and discharge diode b(V5), discharge resistance b(R27) the first pin is connected to not gate f(IC6) input, discharge resistance b(R27) crus secunda is connected to discharge diode b(V5) anode, discharge diode b(V5) negative electrode be connected to first utmost point that starts switch (SB).

3. a kind of plesichronous socket circuit consisting of not gate according to claim 1, is characterized in that at timing switch a(BK1) zero-span and ground wire between You Bang road resistance a(R11); At timing switch b(BK2) zero-span and ground wire between You Bang road resistance c(R26); At not gate d(IC4) input and ground wire between You Bang road resistance b(R24).

4. a kind of plesichronous socket circuit being formed by not gate according to claim 1, it is characterized in that there is indicator light diode (V9) driving between the crus secunda of resistance (R25) and the base stage of triode (VT), when having indicator light diode (V9) between the crus secunda at driving resistance (R25) and the base stage of triode (VT), the crus secunda of driving resistance (R25) is connected to the anode of indicator light diode (V9), and the negative electrode of indicator light diode (V9) is connected to the base stage of triode (VT).

5. a kind of plesichronous socket circuit being formed by not gate according to claim 1; it is characterized in that in regular socket circuit, having two hole socket (CZ1), Three-hole socket (CZ2) and protective earthing interface (G); the phase line socket of two hole socket (CZ1) and Three-hole socket (CZ2) is connected to the phase line interface (L) of power supply by the contact switch (Ka) of relay; the neutral receptacle of two hole socket (CZ1) and Three-hole socket (CZ2) is connected to the zero line interface (N) of power supply, and the ground connection socket of Three-hole socket (CZ2) is connected to protection interface (G).