CN203967079U - Wafer-level package common-mode filter and protection device and semiconductor component - Google Patents
Wafer-level package common-mode filter and protection device and semiconductor component Download PDFInfo
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- CN203967079U CN203967079U CN201420415780.1U CN201420415780U CN203967079U CN 203967079 U CN203967079 U CN 203967079U CN 201420415780 U CN201420415780 U CN 201420415780U CN 203967079 U CN203967079 U CN 203967079U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Abstract
The utility model relates to wafer-level package common-mode filter and protection device and semiconductor component.The technical problem being solved by the utility model is to provide the semiconductor component comprising with the single chip integrated common-mode filter of protection device.The semi-conducting material with the resistivity of at least 5 Ω cm is provided.Protection device is formed by a part for this semi-conducting material, and dielectric material is formed on semi-conducting material.Coil is formed on dielectric material.An advantageous effects of the present utility model is: esd protection device can be made up of the substrate of low-resistivity, and common-mode filter can to carry out monolithic integrated with esd protection device.
Description
Technical field
The utility model relate generally to semiconductor component, and relate more particularly to the signal transmission in semiconductor component.
Background technology
Host-host protocol in communication system can comprise the use of the combination of single-ended signal, differential signal or single-ended signal and differential signal.For example, single-ended signal and differential signal are suitable for adopting in the portable communications system of low speed data transmission.But, adopting in the communication system of high speed data transfer, due to the noiseproof feature of differential signal, thereby preferably use differential signal.The system of these types comprises moving electronic components, for example, and smart phone, panel computer, computer and the system that comprises USB (USB) application.Except noise immunity, preferably also comprise large transient voltage to destroying these systems and the protection of current spike.Typically; noise filter (also referred to as common-mode filter (CMF)) and static discharge (ESD) protective circuit and are installed in printed circuit board (PCB) (PCB) together with other circuit of communication system, are respectively used to be reduced in the common-mode noise on differential signal line and suppress large transient state electricity spike.This configuration of element can take the significantly area on PCB, and this is disadvantageous in moving electronic components.Esd protection circuit is made up of the substrate of low-resistivity, the high electric current being run into adapt to during esd event.Owing to there being the eddy current that can reduce filtering performance, thereby the filter element of manufacturing such as inductance coil on the substrate of low-resistivity is worthless.
Therefore will be, advantageously to have for the manufacture of the protection to large electric transition being provided and structure and the method for the semiconductor component of noise filtering can be provided.Will be more advantageously this structure and method to implement be cost-efficient.
Summary of the invention
Treat that the technical problem being solved by the utility model is to provide the protection to large electric transition and noise filtering is provided.
According to an aspect of the present utility model, the invention provides the single chip integrated common-mode filter and the protection device that are configured to wafer-level package, it is characterized in that comprising: the semi-conducting material with the resistivity of at least 5 Ω cm; The protection device being formed by semi-conducting material; The first material layer on semi-conducting material, the first material layer has the opening of filling with the first electric conducting material; And the first coil on the first material layer.
In one embodiment, single chip integrated common-mode filter and protection device comprise: second material layer with the opening of filling with the second electric conducting material on the first material layer; And the second coil on the second material layer.
According to an aspect of the present utility model, the invention provides a kind of semiconductor component, it is characterized in that comprising: the semi-conducting material with the resistivity of at least 5 Ω cm; The protection device being formed by described semi-conducting material; And on described semi-conducting material and common-mode filter single chip integrated with it.
In one embodiment, be also included in the doped region of the first conduction type in described semi-conducting material.
In one embodiment, wherein said protection device is included as the described doped region of described the first conduction type.
In one embodiment, wherein said protection device comprises electrostatic discharge protection device.
In one embodiment, wherein said electrostatic discharge protection device comprises first and second diode being formed by described semi-conducting material.
In one embodiment, wherein said semi-conducting material has the resistivity of at least 500 Ω cm.
In one embodiment, also comprise: the first material layer on dielectric materials layer; And the first conductive coil structure on described the first material layer.
In one embodiment, wherein said the first material layer is photosensitive material.
In one embodiment, wherein said common-mode filter also comprises: the second material layer on described conductive coil structure and on a part for described the first material layer; And the second conductive coil structure on described the second material layer.
In one embodiment, wherein said common-mode filter also comprises: the 3rd material layer on described the second conductive coil structure and on a part for described the second material layer; And be disposed at the conductive structure in described the 3rd material layer.
In one embodiment, wherein said first, second and third material layer is photosensitive material.
In one embodiment, also comprise and be formed as the soldered ball that contacts with the described conductive structure being disposed in described the 3rd material layer.
According to an aspect of the present utility model, the invention provides a kind of comprising and the wafer-level package of the single chip integrated common-mode filter of protection device, it is characterized in that comprising: the semi-conducting material with the resistivity of at least 5 Ω cm; The first doped region of the first conduction type in described semi-conducting material; Wherein said protection device comprises described the first doped region; And described common-mode filter is configured on described semi-conducting material.
In one embodiment, wherein said protection device has the electric capacity that is less than 10pF.
In one embodiment, be also included at least one contact of described semi-conducting material, and wherein said common-mode filter comprises: the first photosensitive material layer on described semi-conducting material and described at least one contact; The second photosensitive material layer on described the first photosensitive material layer, is disposed at the first spirality conductive structure in described the second photosensitive material layer; The 3rd photosensitive material layer on described the second photosensitive material layer and on described the first spirality conductive structure; Be disposed at the second spirality conductive structure in described the 3rd photosensitive material layer; And for making the electric conducting material of described the first spirality electric conducting material and described the second spirality electric conducting material electric coupling.
The utility model can be used in electronic device.An advantageous effects of the present utility model is: for protect large electric transition and be implemented for circuit and method that noise filtering is provided.
Brief description of the drawings
This will be best understood according to the reading about gathering the detailed description that accompanying drawing carries out below for the utility model, and identical Reference numeral is indicated identical element in the accompanying drawings, and in the accompanying drawings:
Fig. 1 comprises according to circuit theory diagrams a kind of embodiment of the present utility model and the semiconductor component single chip integrated common-mode filter of protection device;
Fig. 2 is according to the layout of the wafer-level package (CSP) of the semiconductor component that can comprise Fig. 1 10 of a kind of embodiment of the present utility model;
Fig. 3 is the sectional view along a part of the CSP of Fig. 2 of the hatching 3-3 intercepting of Fig. 2;
Fig. 4 is the sectional view along a part of the CSP of Fig. 2 of the hatching 4-4 intercepting of Fig. 2;
Fig. 5 is according to the layout of the CSP of the semiconductor component that can comprise Fig. 1 10 of another kind of embodiment of the present utility model;
Fig. 6 is the sectional view along a part of the CSP of the hatching 6-6 intercepting of Fig. 5;
Fig. 7 is the sectional view along a part of the CSP of the hatching 7-7 intercepting of Fig. 5;
Fig. 8 is the sectional view in the initial stage of manufacturing according to the semiconductor component of a kind of embodiment of the present utility model;
Fig. 9 is that the semiconductor component of Fig. 8 is at the sectional view of fabrication stage subsequently;
Figure 10 is that the semiconductor component of Fig. 9 is at the sectional view of fabrication stage subsequently;
Figure 11 is that the semiconductor component of Figure 10 is at the sectional view of fabrication stage subsequently;
Figure 12 is that the semiconductor component of Figure 11 is at the sectional view of fabrication stage subsequently;
Figure 13 is that the semiconductor component of Figure 12 is at the sectional view of fabrication stage subsequently;
Figure 14 is that the semiconductor component of Figure 13 is at the sectional view of fabrication stage subsequently;
Figure 15 is that the semiconductor component of Figure 14 is at the sectional view of fabrication stage subsequently;
Figure 16 is that the semiconductor component of Figure 15 is at the sectional view of fabrication stage subsequently;
Figure 17 is that the semiconductor component of Figure 16 is at the sectional view of fabrication stage subsequently;
Figure 18 is that the semiconductor structure of Figure 17 is at the sectional view of fabrication stage subsequently;
Figure 19 is that the semiconductor component of Figure 18 is at the sectional view of fabrication stage subsequently;
Figure 20 is that the semiconductor component of Figure 19 is at the sectional view of fabrication stage subsequently;
Figure 21 is that the semiconductor component of Figure 20 is at the sectional view of fabrication stage subsequently;
Figure 22 is that the semiconductor component of Figure 21 is at the sectional view of fabrication stage subsequently;
Figure 23 is that the semiconductor component of Figure 22 is at the sectional view of fabrication stage subsequently;
Figure 24 is the top view for the manufacture of the coil pattern of the semiconductor component of Figure 23;
Figure 25 is that the semiconductor component of Figure 23 is at the sectional view of fabrication stage subsequently;
Figure 26 is that the semiconductor component of Figure 25 is at the sectional view of fabrication stage subsequently;
Figure 27 is that the semiconductor component of Figure 26 is at the sectional view of fabrication stage subsequently;
Figure 28 is the top view for the manufacture of the coil pattern of the semiconductor component of Figure 27;
Figure 29 is that the semiconductor component of Figure 28 is at the sectional view of fabrication stage subsequently;
Figure 30 is that the semiconductor component of Figure 29 is at the sectional view of fabrication stage subsequently;
Figure 31 is that the semiconductor component of Figure 30 is at the sectional view of fabrication stage subsequently; And
Figure 32 is that the semiconductor component of Figure 31 is at the sectional view of fabrication stage subsequently.
Embodiment
For illustrated simplicity and clarity, the element in figure might not be equal proportion, and same reference numerals in different accompanying drawings is indicated identical element.In addition, about the step known and description and the details of element are omitted for the purpose of the simplicity of describing.As what use herein, current-carrying electrode means in device for electric current is transmitted by the element of this device, for example, the negative electrode of the emitter of the source electrode of MOS transistor or drain electrode, bipolar transistor or collector electrode or diode or anode, and control electrode means in device for controlling the element through the electric current of this device, for example, the grid of MOS transistor or the base stage of bipolar transistor.Although device is interpreted as certain N raceway groove or P-channel device herein, or certain N-type or P type doped region, those skilled in the art should recognize, according to embodiment of the present utility model, complementary type device is possible equally.Those skilled in the art should recognize, the word that uses herein " ... during ", " ... time " and " when ... " not mean action at the accuracy term that starts to occur immediately when action occurs, but can between initial actuating and its caused reaction, exist slightly small but reasonably postpone, for example, propagation delay.Word " is similar to ", the use of " approximately " or " substantially " means: the value of element has expectation will be in close proximity to the value of defined or the parameter of position.But known as the art, always having obstruction value or position is just in time the value of defined or the less variation of position.Very definite in the art: the variation of (for doping content of semiconductor for up to 20 (20%) percent) is the reasonable change with respect to the dreamboat of accurately describing up to ten (10%) at least percent.
Usually, the utility model provides and has comprised with the semiconductor component of the single chip integrated common-mode filter of protection device and for the manufacture of the method for this semiconductor component, and wherein semiconductor component is suitable for wafer-level package (CSP).Protection device can be called protection structure.According to embodiment, method is provided for integrated to common-mode filter and protection device monolithic.The semi-conducting material of the resistivity with at least 5 Ω cm is provided, and protection device is formed by a part for this semi-conducting material and common-mode filter and protection device monolithic integrate.The substrate of high resistivity has reduced the high-frequency loss due to substrate and has contributed to reduce eddy current.Protection device can have the electric capacity that is less than about 5pF.The resistivity of a part for semiconductor substrate is reduced for than little at least one order of magnitude of the resistivity of the body of substrate.(for example there is the protection device of the total capacitance that is less than about 5pF; static discharges (ESD) protection device) can in substrate, have in the part (, thering is the part of the resistivity of at least one order of magnitude less than the body of substrate) of low resistivity and manufacture.Usually, in the time being made in the semi-conducting material with the resistivity that is greater than about 0.01 Ω cm, esd protection device can not provide enough protections, because mobile electric current can flow through substrate in response to esd event.
According to embodiment of the present utility model, the coil of common-mode filter can use one or more thick polyimide layers (for example, to have the different vertical aspect that is greater than about 3 microns (polyimide layers of μ thickness m)) and carrys out monolithic and be integrated in ESD device top.Thick polyimide layer can reduce electric capacity and stop the coil on different conductive layers to be shorted together.Thick polyimides can reduce eddy current equally.
According to another kind of embodiment, comprise for the method that esd protection device and common-mode filter monolithic are integrated: reduce the resistivity of a part for high resistivity substrate, and in substrate, have in the part of low resistivity and manufacture esd protection device.Common-mode filter can be made on esd protection device top.
According to another kind of embodiment, the resistivity of a part for semiconductor substrate is lowered at least one order of magnitude, and protection device is made in the part of the resistivity in semiconductor substrate with reduction.A kind of material is formed on semiconductor substrate, and the coil of common-mode filter is made on this material.
Fig. 1 is the circuit theory diagrams that are integrated in the semiconductor component 10 of the common-mode filter (CMF) 12 on semi-conducting material with protection device 14 monolithics that comprise according to a kind of embodiment of the present utility model.Shown in Fig. 1 is the common-mode filter 12 of the coil 16 and 18 that comprises into differential configuration.Coil 16 has input IN+ and the output OUT+ of a part that forms respectively difference input and difference output.Coil 18 has input IN-and the output OUT-of a part that forms respectively difference input and difference output.Input IN+ and IN-form difference input, and output OUT+ and OUT-form difference output.The magnetic coupling of point 20 and 22 instruction coils 16 and 18.For instance, protection device 14 comprises the protection module 24 being connected with the input terminal IN+ of coil 16 and the protection module 26 being connected with the input terminal IN-of coil 18.Protection module 24 comprises pair of diodes 28 and 30 and Zener diode 32.The negative electrode of diode 28 is connected with the negative electrode of Zener diode 32, and the anodic bonding of the anode of diode 30 and Zener diode 32.The anode of diode 30 and 32 is for example coupled, for receiving operating potential (, operating potential V
sS) source.For instance, operating potential V
sSit is earth potential.Anode and the negative electrode of diode 28 and 30 link together respectively jointly, and are connected to the input terminal IN+ of coil 16.Diode 28 and 30 can be called and turns to diode, and wherein diode 28 also can be called top diode or upper diode, and diode 30 also can be called bottom diode or lower diode.
Protection module 26 comprises pair of diodes 34 and 36 and Zener diode 38.The negative electrode of diode 34 is connected with the negative electrode of Zener diode 38, and the anodic bonding of the anode of diode 36 and Zener diode 38.The anode of diode 36 and 38 is for example coupled, for receiving operating potential (, operating potential V
sS) source.Anode and the negative electrode of diode 34 and 36 link together respectively jointly, and are connected to the input terminal IN-of coil 18.Diode 34 and 36 can be called and turns to diode, and wherein diode 34 can be called diode or top diode, and diode 36 can be called lower diode or bottom diode.It should be noted that, Zener diode 32 and 38 can be realized by the doped region 176,188 and 190 of describing with reference to Figure 15, upper diode 28 and 34 can be realized by the doped region 134,180 and 202 of describing with reference to Figure 19 and a part of p trap 118A, and lower diode 30 and 36 can be realized by the doped region 132,178 and 200 of describing with reference to Figure 19 and a part for p trap 128.
Fig. 2 is the layout of wafer-level package (CSP) 40, and this wafer-level package (CSP) 40 can comprise by having opposite flank 46 and 47 and the semiconductor component 10 that forms of the semiconductor chip 44 of opposite flank 48 and 49.It should be noted that according to embodiment, wafer-level package comprises the semiconductor chip that has (UBM) pad of metal under salient point and be installed on the independent soldered ball of each UBM pad.Wafer-level package 40 comprises: the coil 16 and 18 of the CMF12 periphery of semiconductor chip 44 near, in the core of semiconductor chip 44, turn to diode 28 and 30 and turn to diode 34 and 36, Zener diode 32 under a near part for the coil 16 and 18 side 46 of semiconductor chip 44, and Zener diode 38 under a near part for the coil 16 and 18 side 47 of semiconductor chip 44.It should be noted that coil 16 and 18 is located on different to each other perpendicular slices, and coil 18 can be on coil 16, as shown in Figures 3 and 4.
Briefly, with reference to Fig. 3, there is shown the sectional view of the coil 16 and 18 intercepting along the hatching 3-3 of Fig. 2.Coil 18 is covered on coil 16.Coil 16 has height h
16, width w
16and distance s
16, and coil 18 has height h
18, width w
18and distance s
18.Size h
16, w
16, s
16, h
18, w
18and s
18selected so that the magnetic coupling between coil part maximizes, reduce direct current (DC) resistance of coil 16 and 18, and reduce electric capacity semi-conducting material 12 and to aluminium conductive layer.More particularly, spacing dimension s
16and s
18selected to reduce, and preferably minimize the area being taken by coil 16 and 18, and height and width dimensions h
16, h
18, w
16and w
18selected to reduce DC resistance.In addition, also make width dimensions w
16and w
18diminish to reduce, and preferably minimize, electric capacity.In order to increase, and preferably in order to maximize magnetic coupling, edge or the sidewall vertical alignment of the edge of coil 16 or sidewall and corresponding coil 18.For example, edge 16A aligns with corresponding edge 18A, and edge 16B aligns with corresponding edge 18B.Although coil 18 is illustrated as being covered in completely on coil 16, that is, the edge of coil 16 aligns with the respective edges of coil 18, is not restricted to this.For example, the edge of coil 18 can be in coil 16 on the part between the neighboring edge of coil 16.
Briefly, with reference to Fig. 4, there is shown the sectional view of the coil 16 and 18 intercepting along the hatching 4-4 of Fig. 2.As mentioned above, coil 16 has height h
16, width w
16and distance s
16, and coil 18 has height h
18, width w
18and distance s
18.Although coil 18 is illustrated as being covered in completely on coil 16, that is, the edge of coil 16 aligns with the respective edges of coil 18, is not restricted to this.For example, the edge of coil 18 can be in coil 16 on the part between the neighboring edge of coil 16.
Referring again to Fig. 2, semiconductor component 10 also comprises the UBM pad 50,51,52,53,54 and 55 that soldered ball can couple with it.For instance, UBM pad 50 use act on the UBM layer of input IN+, and UBM pad 51 use act on the UBM layer of output OUT+, and UBM pad 52 use act on the UBM layer of input IN-, and UBM pad 53 use act on the UBM layer of output OUT-; UBM pad 54 use act on and can be used for to providing the UBM layer of the input terminal that the esd protection device of esd protection is connected with the circuit of this terminal electrical connection, and UBM pad 55 is used as and is configured to and current potential V
sSthe UBM layer coupling, this current potential V
sSit can be for example earth potential.It should be noted that and turn to diode (for example, turning to diode 28,30,34 and 36) can be located under corresponding UBM pad.
Referring now to Fig. 5, there is shown the layout of CSP60, this CSP60 can comprise by having opposite flank 66 and 67 and the semiconductor component 10 that forms of the semiconductor chip 64 of opposite flank 68 and 69.CSP60 is included in the coil 70 and 72 of the CMF12 periphery of semiconductor chip 64 near, the UBM pad 71,73,74,75 and 76 being surrounded by coil 70 and 72, and and laterally adjacent and horizontal Zener diode 77 and 78 between them of UBM pad 71 and 73.Diode (for example, turning to diode 28,30,34 and 36) can be located under corresponding UBM pad 74 and 76.It should be noted that coil 70 and 72 is located on different to each other perpendicular slices, and coil 72 can be positioned on coil 70, as shown in Figures 6 and 7.
Briefly, with reference to Fig. 6, there is shown the sectional view of the coil 70 and 72 intercepting along the hatching 6-6 of Fig. 5.Coil 72 is covered on coil 70.Coil 70 has height h
70, width w
70and distance s
70, and coil 72 has height h
72, width w
72and distance s
72.Size h
70, w
70, s
70, h
72, w
72and s
72selected so that the magnetic coupling between coil part maximizes, reduce the DC resistance of coil 70 and 72, and reduce electric capacity semi-conducting material 12 and to aluminium conductive layer.More particularly, spacing dimension s
70and s
72selected to reduce, and preferably minimize the area being taken by coil 70 and 72, and height and width dimensions h
70, h
72, w
70and w
72selected to reduce DC resistance.In addition, also make width dimensions w
70and w
72diminish to reduce, and preferably minimize, electric capacity.In order to increase, and preferably maximize magnetic coupling, edge or the sidewall vertical alignment of the edge of coil 70 or sidewall and corresponding coil 72.For example, edge 70A aligns with corresponding edge 72A, and edge 70B aligns with corresponding edge 72B.Although coil 72 is illustrated as being covered in completely on coil 70, that is, the edge of coil 70 aligns with the respective edges of coil 72, is not restricted to this.For example, the edge of coil 72 can be in coil 70 on the part between the neighboring edge of coil 70.
Briefly, with reference to Fig. 7, there is shown the sectional view of the coil 70 and 72 intercepting along the hatching 7-7 of Fig. 5.As mentioned above, coil 70 has height h
70, width w
70and distance s
70, and coil 72 has height h
72, width w
72and distance s
72.Although coil 72 is illustrated as being covered in completely on coil 70, that is, the edge of coil 72 aligns with the respective edges of coil 70, is not restricted to this.For example, the edge of coil 72 can be in coil 70 on the part between the neighboring edge of coil 70.
Fig. 8 is for example, according to the sectional view of a part for the semiconductor component during manufacture 100 of a kind of embodiment of the present utility model (, being integrated in the common-mode filter on semi-conducting material with protection device monolithic).Shown in Fig. 8 is the semi-conducting material 102 with apparent surface 104 and 106.Surface 104 is also referred to as front surface or upper surface, and surface 106 is also referred to as back of the body surface or lower surface.According to the present embodiment, semi-conducting material 102 comprises the semiconductor substrate with the impurity material doping of P-type conduction, and has the resistivity of at least about 5 Ω cm (Ω-cm).Preferably, the resistivity of substrate 102 is 100 Ω-cm.More preferably, the resistivity of substrate 102 is 500 Ω-cm or larger, that is, and at least 500 Ω-cm, and will be preferably, the resistivity of substrate 102 is 1,000 Ω-cm or larger, that is, and at least 1,000 Ω-cm.The suitable material of substrate 102 comprises semi-conducting material, the semi-conducting material of II-VI family etc. of silicon, compound semiconductor materials (for example, gallium nitride, GaAs, indium phosphide), III-V family.According to other embodiment, semi-conducting material 102 comprises the epitaxial loayer being formed on semiconductor substrate, wherein semiconductor substrate is the silicon material doped with p type impurity and the resistivity with at least 100 Ω-cm, and epitaxial loayer adulterates with the impurity material of P-type conduction and has the resistivity of at least 100 Ω-cm.It should be noted that with the region of N-type alloy or impurity material doping or layer be known as N-type conductivity or N conduction type, and with the region of P type alloy or impurity material doping or layer be known as P-type conduction or P conduction type.
Dielectric materials layer 108 is formed on semiconductor substrate 102 or by it and forms.According to a kind of embodiment of the present utility model, the material of dielectric layer 108 be have about 1,000～approximately
the silicon dioxide of thickness.The technology that is used to form silicon dioxide layer 108 is that those skilled in the art understand.For example, silicon dioxide layer 108 can form by oxidized semiconductor substrate 102, or it can be the TEOS layer forming with plasma enhanced chemical vapor deposition.Still with reference to Fig. 8, photoresist layer, by graphically on dielectric layer 108, has to form the opening 114 of sheltering the shelter 110 of element 112 and dielectric layer 108 parts being exposed.
Referring now to Fig. 9, in dielectric layer 108, be not subject to sheltering part that element 112 protects and use for the wet etchant of the material of etching dielectric layer 108 optionally and remove.For instance, wet etchant is buffered oxide etch agent.This etching meeting retains the part 108A of dielectric layer 108, and surperficial 104 parts are exposed.Part 108A can be called injecting mask, and has sidewall and surface.Shelter element 112 and be removed, and substrate 102 is processed into HF inclination angle to remove the oxide on the exposed part that may be formed at surface 104.Have about 150～approximately
thickness pad oxide layer 116 by semiconductor substrate 102 is positioned over provide about 900 degrees Celsius (DEG C) the stove of ambient temperature within be formed on the exposed part on surface 104.Although the sidewall that pad oxide layer 116 is illustrated as being formed at injecting mask 108A is with surperficial upper, the utility model is not restricted to this.The process that is used to form pad oxide layer 116 can be such, and it is very little making pad oxide layer 116 not be formed at injecting mask 108A thickness upper or that be formed on injecting mask 108A.It should be noted that pad oxide can be called screen oxide.
One or more P traps 118 are by within injecting substrate 102 by the impurity material of P-type conduction and order about impurity material and enter within semi-conducting material 102 and be formed in semiconductor substrate 102.P trap 118 can pass through impurity material according to about 5 × 10
12～about 1 × 10
14atoms/cm
2dosage and about 25～approximately the Implantation Energy of 80keV injects within semiconductor substrate 102 and forms.By semi-conducting material 102 is positioned over and has about 1,000～about 1, in the inert ambient environment of the temperature of 250 DEG C, reach the duration of about 2.5～about 3.5 hours and order about within impurity material enters semi-conducting material 102, and semi-conducting material 102 is annealed.For instance, P trap 118 forms like this: according to about 2 × 10
13atoms/cm
2dosage and approximately the Implantation Energy of 35keV inject p type impurity material, and in nitrogen atmosphere environment at the temperature of about 1,150 DEG C, reach about 3 hours to order about within alloy enters semi-conducting material 102.Suitable P type alloy or impurity material comprise boron, indium etc.
Referring now to Figure 10, pad oxide layer 116 is removed from surface 104, and have about 150～approximately
another pad oxide layer 120 examples of thickness technology of being used to form as described pad oxide layer 116 be formed on surface 104 or formed by it.Photoresist layer, by graphically on injecting mask 108A and pad oxide layer 120, has to form the opening 126 of sheltering the shelter 122 of element 124 and pad oxide layer 120 parts being exposed.The doped region 128 of N-type conductivity is formed in P trap 118, and the doped region 130,132,134 and 136 of N-type conductivity is by injecting the impurity material of N-type conductivity within P trap 118A and be formed in P trap 118A.It should be noted that P trap 118A is one of multiple P traps, and for clarity and Reference numeral " A " is invested to Reference numeral " 118 ",, manufacture and describe with reference to P trap 118A, still should be appreciated that and can have the manufactured multiple doped regions 118 in the inner of semiconductor device.Doped region 128-136 can pass through according to about 3 × 10
12～about 1 × 10
13atoms/cm
2dosage and about 75～approximately the Implantation Energy of 125keV injects impurity material within P trap 118 and forms.Sheltering element 124 is removed, and by semiconductor substrate 102 being positioned over to about 950～about 1, in inert ambient environment at the temperature of 250 DEG C, reach the duration of about 30 minutes to about 2 hours and order about within impurity material enters P trap 118, and semiconductor substrate 102 is annealed.For instance, doped region 128-136 forms like this: according to about 4.3 × 10
12atoms/cm
2dosage and approximately the Implantation Energy of 100keV inject N-type impurity material, and in nitrogen atmosphere environment at the temperature of about 1,200 DEG C, reach about 1 hour to order about within alloy enters P trap 118.Doped region 128-136 can be called N trap.Suitable N-type alloy or impurity material comprise phosphorus, arsenic etc.
Referring now to Figure 11, pad oxide layer 120 and injecting mask 108A use for example wet etching to remove, and have about 150～approximately
the dielectric layer 140 of thickness be formed on semiconductor substrate 102 or by it and form by semiconductor substrate 102 being positioned in the oxidizing atmosphere environment at the temperature of about 900 DEG C.For instance, dielectric layer 140 is to have approximately
the oxide of thickness.In dielectric layer 140 embodiment that the material of dielectric layer 140 is oxide therein, can be called pad oxide.Have about 1,000～approximately
thickness layer a dielectric material 142 be formed in pad oxide layer 140.For instance, dielectric layer 142 is to have approximately
the silicon nitride of thickness, and form with low-pressure chemical vapor deposition.The utility model is not restricted to be used to form the said method of silicon nitride layer 142.
Photoresist layer, by graphically on silicon nitride layer 142, has to form the opening 148 of sheltering the shelter 144 of element 146 and silicon nitride layer 142 parts being exposed.The exposed portions serve of silicon nitride layer 142 is used for example reactive ion etching to remove, so that pad oxide layer 140 parts are exposed.
Referring now to Figure 12, sheltering element 146 is removed, and photoresist layer, is sheltered the shelter 145 of element 147 and is made pad oxide layer 140 and opening 149 that silicon nitride layer 142 exposes to form to have by graphical on the exposed part of silicon nitride layer 142 and pad oxide layer 140.
The doped region 150,152 and 154 of P-type conduction is by injecting the impurity material of P-type conduction in P trap 118A and be formed in the some parts of P trap 118A.Doped region 150-154 can pass through according to about 5 × 10
12～about 3.5 × 10
13atoms/cm
2dosage and about 20～approximately the Implantation Energy of 50keV injects impurity material within P trap 118A and forms.For instance, doped region 150-154 passes through according to about 3 × 10
13atoms/cm
2dosage and approximately the Implantation Energy of 35keV inject p type impurity material and form.Semi-conducting material 102 is annealed.Doped region 150-154 can be called channel stop.Suitable P type alloy or impurity material comprise boron, indium etc.For instance, doped region 150 is laterally adjacent with doped region 132, and doped region 152 is laterally between doped region 132 and 134, and doped region 154 is laterally between doped region 134 and 136.
Referring now to Figure 13, shelter element 147 and be removed, and the duration that reaches about 1～about 5 hours is carried out in an oxidation at the temperature of about 950～about 1,250 DEG C.For instance, an oxidation is carried out about 2 hours at about 1,000 DEG C, has approximately to form
the field oxide structure 156,158,160 and 162 of thickness.According to a kind of embodiment, doped region 132 is adjacent to field oxide structure 156 and 158 and laterally between them, doped region 134 is adjacent to field oxide structure 158 and 162 and laterally between them, and within field oxide regions 160 extends to doped region 134.Silicon nitride layer 142 uses the wet etching process of optionally removing silicon nitride to remove, and pad oxide layer 140 is used the wet etching process of optionally removing oxide to remove.The utility model is not restricted to the said method for removing silicon nitride layer 142 and oxide layer 140.
Referring now to Figure 14, by semiconductor substrate 102 is positioned in the oxidizing atmosphere environment at the temperature of about 900 DEG C, make to have about 150～approximately
the dielectric layer 166 of thickness be formed at semiconductor substrate 102 and field oxide structure 156-162 upper or formed by them.For instance, dielectric layer 166 is to have approximately
the oxide of thickness.The thickness that it should be noted that the dielectric layer 166 on oxide structure 156-162 on the scene can be very thin, thereby it is not shown as and is formed on these structures.In the embodiment that is oxide at the material of dielectric layer 166, dielectric layer 166 can be called pad oxide layer.Photoresist layer is by graphically on pad oxide layer 166, has to form the opening 172 that the part on P trap 118A of sheltering the shelter 168 of element 170 and making pad oxide layer 166 is exposed.
Within injecting P trap 118A by the impurity material of N-type conductivity, the doped region 176 of N-type conductivity is formed in a part and P trap 118A for doped region 130, and the doped region 178 and 180 of N-type conductivity is formed at respectively in doped region 132 and 134.Doped region 176-180 can pass through according to about 5 × 10
14～about 1 × 10
18atoms/cm
2dosage and about 20～approximately the Implantation Energy of 100keV carrys out implanted dopant material and forms.For instance, doped region 176-180 passes through according to about 6 × 10
15atoms/cm
2dosage and approximately the Implantation Energy of 65keV inject arsenic and form.Suitable N-type alloy or impurity material comprise phosphorus, arsenic etc.
Referring now to Figure 15, shelter element 170 and be removed, and photoresist layer is had to form the opening 186 of sheltering the shelter 182 of element 184 and pad oxide layer 166 parts being exposed by graphical on pad oxide layer 166.By by the impurity material dopant implant district 130 of N-type conductivity and P trap 118A and form respectively the doped region 188 and 190 of N-type conductivity in doped region 130 and P trap 118A.Doped region 188 and 190 can be passed through according to about 2.5 × 10
12～about 5 × 10
14atoms/cm
2dosage and about 20～approximately the Implantation Energy of 100keV carrys out implanted dopant material and forms.For instance, doped region 188 and 190 is passed through according to about 3.5 × 10
13atoms/cm
2dosage and approximately the Implantation Energy of 60keV inject phosphorus and form.Within 188 doped region, doped region 130, and be laterally adjacent to the side of doped region 176, and doped region 190 is within P trap 118A, and be laterally adjacent to doped region 176 at the side place of the doped region 176 relative with the side of 188Tong doped region, doped region 176 adjacency.Suitable N-type alloy or impurity material comprise phosphorus, arsenic etc.Doped region 188 and 190 has formed a part for Zener diode.
Referring now to Figure 16, shelter element 184 and be removed, and photoresist layer is by graphically on pad oxide layer 166, has to form the opening 196 of sheltering the shelter 192 of element 194 and pad oxide layer 166 parts being exposed.By by within the impurity material dopant implant district 130 and 134 of P-type conduction and P trap 118A and make respectively within the doped region 198,200 and 202 of P-type conduction is formed at doped region 130, P trap 118A and doped region 134.Doped region 198,200 and 202 can be passed through according to about 5 × 10
14～about 1 × 10
16atoms/cm
2dosage and about 20～approximately the Implantation Energy of 100keV carrys out implanted dopant material and forms.For instance, doped region 198,200 and 202 is passed through according to about 5 × 10
15atoms/cm
2dosage and approximately the Implantation Energy of 50keV carry out B Implanted and form.Within 198 doped region, doped region 130, and be laterally adjacent to the side of doped region 188, doped region 200 is within P trap 118A, and be laterally adjacent to doped region 190 doped region 190 with relative the locating in side 176Tong doped region, doped region 190 adjacency, and within 202 doped region, doped region 134 and laterally between field oxide structure 158 and 160.Suitable P type alloy or impurity material comprise boron, indium etc.
Referring now to Figure 17, shelter that element 194 is removed and pad oxide layer 166 is removed, and dielectric materials layer 206 is formed at semiconductor substrate 102 and field oxide structure 156-162 is upper, and dielectric materials layer 208 is formed on dielectric layer 206, and dielectric materials layer 210 is formed on dielectric layer 208.For instance, dielectric layer 206 forms by being oxidized, and have about 100～approximately
thickness, dielectric layer 208 is the unadulterated silex glasss that form by plasma enhanced chemical vapor deposition, and have about 1,000～approximately
thickness, and dielectric layer 210 is the boron phosphorus silicate glass that form by plasma enhanced chemical vapor deposition, and have about 5,000～approximately
thickness.For instance, dielectric layer 206 has approximately
thickness, dielectric layer 208 has approximately
thickness, and dielectric layer 210 has approximately
thickness.Reflux cycle carries out at the temperature of about 900～about 1,000 DEG C so that dielectric layer 210 planarizations activate the alloy of doped region 176,178,180,188,190,198,200 and 202.For instance, reflux cycle is at the temperature of about 950 DEG C.It should be noted that the utility model is not restricted to above-mentioned thickness and is used to form the said method of dielectric layer 208,208 and 210.
Still with reference to Figure 17, photoresist layer, by graphically on dielectric layer 210, has to form the opening 216 of sheltering the shelter 212 of element 214 and dielectric layer 210 parts being exposed.The part that element 214 protects of being sheltered of passing through part that opening 216 exposes and dielectric layer 208 and 206 of dielectric layer 210 is used for example wet etching process to remove.Those parts of removing dielectric layer 210,208 and 206 can make doped region 176,178,180,198,200 and 202 parts expose.
Referring now to Figure 18, shelter element 214 and be removed, and high melting metal layer (not shown) is deposited on the exposed part of dielectric layer 210 and doped region 176,178,180,198,200 and 202.For instance, refractory metal be have about 100～approximately
the titanium of thickness.Rapid thermal annealing is performed, and wherein refractory metal is heated to the temperature of about 500～about 700 DEG C.This heat treatment meeting impels titanium and pasc reaction, to form titanium silicide in the All Ranges of titanium and silicon or polysilicon contact.As selection, refractory metal can be titanium nitride, tungsten, cobalt etc.The silicide being formed by rapid thermal annealing is as barrier layer.
Aluminum bronze silicon layer 220 is formed on metal barrier (not shown) and dielectric layer 210.For instance, aluminum bronze silicon layer 220 is splashed on metal barrier and dielectric layer 210, and has the thickness of about 1～about 4 μ m.As selection, layer 220 can be aluminium, aluminum bronze, aluminium silicon etc.Photoresist layer, by graphically on aluminum bronze silicon layer 220, has to form the opening 226 of sheltering the shelter 222 of element 224 and aluminum bronze silicon layer 220 parts being exposed.
Referring now to Figure 19, the exposed part of aluminum bronze silicon layer 220 uses metal etching process to remove, and retains contact 220A, 220B, 220C, 220D, 220E and 220F.Layer 220 can carry out etching with plasma etching or wet etching.Contact 220B is as the anode contact of Zener diode, and contact 220C is as the cathode contact of Zener diode.It should be noted that the anode of doped region 198 as Zener diode, and doped region 176,188,190 and 118A cooperation form the negative electrode of Zener diode.Contact 220D forms and turns to diode (for example, lower diode) anode contact, contact 220E forms the cathode contact of lower diode and another and turns to the anode contact of diode (for example, upper diode), and contact 220F forms the negative electrode of diode.A part of doped region 200 and P trap 118A forms the anode of lower diode, and doped region 132 and 178 cooperations form the negative electrode of lower diode, and doped region 202 forms the anode of upper diode, and doped region 134 and 180 forms the negative electrode of upper diode.Contact 220A can be with connecting contact to be formed in being connected between common-mode filter and other circuit elements.It should be noted that the Zener diode being formed in P trap 118A, lower diode and upper diode cooperation form protection structure, for example, esd protection device.
Still with reference to Figure 19, passivation layer 230 is formed on electrode 220A-220F and on the exposed part of dielectric layer 210.For instance, passivation layer 230 comprises the silicon nitride layer being formed on oxide skin(coating), and wherein the thickness of oxide skin(coating) can be about
and the thickness of nitride layer can be about
as selection, passivation layer 230 can comprise individual layer nitride or other suitable dielectric materials.Photoresist layer, by graphically on passivation layer 230, has to form the opening 236 of sheltering the shelter 232 of element 234 and passivation layer 230 parts being exposed.
Referring now to Figure 20, the part that opening 236 exposes of passing through of passivation layer 230 is used for example wet etching to remove.Those parts of removing passivation layer 230 can make electrode 220A and 220E part expose.
Referring now to Figure 21, shelter element 234 and be removed, and light-sensitive polyimide layer 240 is formed on the exposed part of passivation layer 230 and contact 220A and 220E.For instance, polyimide layer 240 is configured to the thickness with about 16 μ m, and then by spin coating to there is the rear cured thickness of even curface substantially and at least about 4 μ m.As selection, the rear cured thickness of polyimide layer 240 can be at least 5 μ m, or at least 8 μ m, or at least 10 μ m.Suitable light-sensitive polyimide material comprises HDM polymer coating, polybenzoxazoles (PBO), dibenzo cyclobutane (BCB) of the light-sensitive polyimide of being sold with trade mark PIMEL by Korean and Japanese company, Korean and Japanese chemical industry and Du Pont's electronics etc.It should be noted that layer 240 is not restricted to as light-sensitive polyimide, but can be to make patterned non-photosensitive material with photoresist.
Referring now to Figure 22, polyimide layer 240 removes by being exposed to electromagnetic radiation (following by development step) in the part of passing through on part that the opening in passivation layer 230 exposes of electrode 220A and 220E.Polyimide layer 240 is cured after the part that is exposed to electromagnetic radiation is removed.The removal of the exposed part of polyimide layer 240 makes electrode 220A and 220E part expose again.
Referring now to Figure 23, have about 1,500～approximately
the adhesive layer 242 of thickness be formed on polyimide layer 240 and on the exposed part of electrode 220A and 220E.Suitable material for adhesive layer 242 comprises titanium tungsten, titanium nitride, titanium, tungsten, platinum etc.Have about 1,500～approximately
the copper seed layer 244 of thickness be formed on adhesive layer 242.For instance, layer 242 and 244 has approximately separately
thickness.Photoresist layer 246 is formed in copper seed layer 244.Preferably, the thickness of photoresist layer 246 is selected as thicker than the thickness of the copper for the treatment of to plate in subsequent step.For instance, the thickness of photoresist layer 246 is about 14 μ m.
Briefly, with reference to Figure 24, there is shown the mask with masking graphics 250 248 for graphical photoresist layer 246.Light passes cross spider region so that photoresist layer 246 parts are exposed.The exposure part of photoresist layer 246 is removed, thereby copper seed layer 244 parts shown in Figure 25 are exposed.
Referring now to Figure 25, after photoresist layer 246 graphical, copper is electroplated onto on the exposed part of copper seed layer 244, thereby forms the structure of contact terminal 256 that can electrically contact with contact 220A and the structure of contact terminal 258 that can electrically contact with contact 220E.Electricity plated with copper can form the coil 260 of inductor (for example,, with reference to the described inductor 16 in Fig. 1-4 or with reference to the described inductor 70 in Fig. 5-7).It should be noted that inductor comprises the coil with wire turn, thereby coil can be called inductor or wire turn.
Referring now to Figure 26, photoresist layer 186 is removed, and this can make copper seed layer 244 parts expose.The exposed part of copper seed layer 244 and the part of adhesive layer 242 under the exposed part of copper seed layer 244 are used for example wet etching process to remove.It should be noted that copper seed layer 244 and adhesive layer 242 can use different etching materials to remove.As selection, can use dry etching to remove the exposed part of layer 244 and 242.
Referring now to Figure 27, polyimide layer 264 is formed on the exposed part and coil 260 of exposed part, structure of contact terminal 256 and 258 of polyimide layer 240.For instance, polyimide layer 264 is configured to the thickness with about 16 μ m, and then by spin coating to there is the rear cured thickness of even curface substantially and about 10 μ m.The thickness that it should be noted that polyimide layer 264 is selected to reduce ghost effect, for example, structure of contact terminal 256 and 258 and coil 260 and the copper layer of electroplated on polyimide layer 264 between parasitic capacitance etc.Suitable light-sensitive polyimide material is discussed with reference to polyimide layer 240.As layer 240, layer 264 is not restricted to light-sensitive polyimide, but can be to make patterned non-photosensitive material with photoresist.The part of polyimide layer 264 on those parts of structure of contact terminal 256 and 258 removes by being exposed to electromagnetic radiation (following by development step).Polyimide layer 264 is cured after the part that is exposed to electromagnetic radiation is removed.The removal of the exposed part of polyimide layer 264 is exposed structure of contact terminal 256 and 258 parts.
Still with reference to Figure 27, have about 1,500～approximately
the adhesive layer 266 of thickness be formed on polyimide layer 264 and on the exposed part of structure of contact terminal 256 and 258.Suitable material for adhesive layer 266 comprises titanium tungsten, titanium nitride, titanium, tungsten, platinum etc.Have about 1,500～approximately
the copper seed layer 268 of thickness be formed on adhesive layer 266.Photoresist layer 270 is formed in copper seed layer 268.Preferably, to be selected as the thickness of the copper layer in copper seed layer 268 than electroplated large for the thickness of photoresist layer 270.The thickness of photoresist layer 270 can be about 5～about 20 μ m, and can be for example about 14 μ m.Those skilled in the art should recognize, the thickness of photoresist layer 270 may be subject to process technology limit due to Line-width precision limitation.
Briefly, with reference to Figure 28, there is shown the mask with masking graphics 274 272 for graphical photoresist layer 270.Light passes cross spider region so that photoresist layer 270 parts are exposed.The exposed portion of photoresist layer 270 is removed, thereby copper seed layer 268 parts are exposed.
Referring now to Figure 29, after graphical photoresist layer 270, copper is electroplated onto on the exposed part of copper seed layer 268, thereby form from the extended structure of contact terminal 276 of structure of contact terminal 256, form from the extended structure of contact terminal 278 of contact 258, and form coil 280 or inductor, for example, the inductor 18 shown in Fig. 1.
Referring now to Figure 30, photoresist layer 270 is removed, and this exposes copper seed layer 268 parts.The exposed part of copper seed layer 268 and the part of adhesive layer 266 under the exposed part of copper seed layer 268 are used for example wet etching process to remove.Polyimide layer 284 is formed on the exposed part and coil 280 of exposed part, structure of contact terminal 276 and 278 of polyimide layer 264.For instance, polyimide layer 284 is configured to the thickness with about 16 μ m, and then by spin coating to form even curface substantially.It should be noted that the thickness of polyimide layer 240 is at least about 5 μ m, and can be at least about 10 μ m after solidifying.The thickness of polyimide layer 284 is selected to reduce ghost effect, for example, structure of contact terminal 276 and 278 and coil 280 and the copper layer of electroplated on polyimide layer 284 between parasitic capacitance.Suitable light-sensitive polyimide material is discussed with reference to polyimide layer 240.As layer 240, layer 284 is not restricted to light-sensitive polyimide, but can be to make patterned non-photosensitive material with photoresist.The part of polyimide layer 284 on those parts of structure of contact terminal 276 and 278 removes by being exposed to electromagnetic radiation (following by development step).Polyimide layer 284 is cured in after the part that is exposed to electromagnetic radiation is removed.The removal of the exposed part of polyimide layer 284 is exposed structure of contact terminal 276 and 278 parts.
Still with reference to Figure 30, have about 1,500～approximately
the adhesive layer 286 of thickness be formed on polyimide layer 284 and on the exposed part of structure of contact terminal 276 and 278.Suitable material for adhesive layer 286 comprises titanium tungsten, titanium nitride, titanium, tungsten, platinum etc.Have about 1,500～approximately
the copper seed layer 288 of thickness be formed on adhesive layer 232.Photoresist layer 290 is formed in copper seed layer 288.Preferably, to be selected as the thickness of the copper layer in copper seed layer 288 than electroplated large for the thickness of photoresist layer 290.The thickness of photoresist layer 290 can be about 5～about 20 μ m, and can be for example about 14 μ m.As mentioned above, the thickness of photoresist layer 290 can limit to select according to Line-width precision.
Referring now to Figure 31, photoresist layer 290 is graphically had to form shelter 292 and the opening 296 of sheltering element 294, and this opening 296 exposes the part of copper seed layer 288 on electrode structure 276 and 278.After sheltering the formation of element 294, copper is electroplated onto on the exposed part of copper seed layer 288, thereby forms from the extended UBM pad 298 of structure of contact terminal 276 and from the extended UBM pad 300 of structure of contact terminal 278.
Referring now to Figure 32, shelter element 294 and be removed, and pedestal 302 and 304 is formed at respectively on UBM pad 298 and 300.For instance, pedestal 302 and 304, by forming with stencil, to apply scaling powder, thereby is placed in soldered ball on UBM pad 298 and 300, and substrate 102 is placed in to reflow ovens to form pedestal 302 and 304.
So far, should recognize, the semiconductor component that profile is little and section is little that comprises single chip integrated CMF and ESD device and the method for the manufacture of this semiconductor component are provided herein.Semiconductor component is formed the wafer-level package with following characteristic: the difference bandwidth of at least 2 gigahertzs; under 500 megahertzes, be less than the common-mode rejection ratio of 15dB, meet the esd protection with the electric capacity that is less than 1.5pF of moving device drop test and temperature cycles standard.CSP encapsulation can be configured to have optional esd protection pin, as shown in Figure 26 and 27.
According to an aspect of the present utility model, the single chip integrated common-mode filter and the protection device that are configured to wafer-level package are provided, comprise: the semi-conducting material with the resistivity of at least 5 Ω cm; The protection device being formed by semi-conducting material; The first material layer on semi-conducting material, this first material layer has the opening of filling with the first electric conducting material; And the first coil on the first material layer.
In one embodiment, single chip integrated common-mode filter and protection device are included in the second material layer on first material layer with the opening of filling with the second electric conducting material; And the second coil on the second material layer.
According on the other hand of the present utility model, semiconductor component is provided, comprise: the semi-conducting material with the resistivity of at least 5 Ω cm; The protection device being formed by semi-conducting material; And on semi-conducting material and common-mode filter single chip integrated with it.
In one embodiment, semiconductor component is included in the doped region of the first conduction type in semi-conducting material.
In one embodiment, protection device is included in the doped region of the first conduction type in semi-conducting material.
In one embodiment, protection device comprises electrostatic discharge protection device.
In one embodiment, electrostatic discharge protection device comprises first and second diode being formed by semi-conducting material.
In one embodiment, semi-conducting material has the resistivity of at least 500 Ω cm.
In one embodiment, semiconductor component is also included in the first material layer on dielectric materials layer; And the first conductive coil structure on the first material layer.
In one embodiment, the first material layer is photosensitive material.
In one embodiment, common-mode filter also comprises: the second material layer on conductive coil structure and on a part for the first material; And the second conductive coil structure on the second material layer.
In one embodiment, common-mode filter also comprises: the 3rd material layer on the second conductive coil structure and on a part for the second material layer; And conductive structure in the 3rd material layer.
In one embodiment, first, second and third material layer is photosensitive material.
In one embodiment, semiconductor component also comprises and is formed as the soldered ball that contacts with the conductive structure being disposed in the 3rd material layer.
According on the other hand of the present utility model, the wafer-level package comprising with the single chip integrated common-mode filter of protection device is provided, comprise: the semi-conducting material with the resistivity of at least 5 Ω cm; The first doped region of the first conduction type in semi-conducting material; Wherein protection device comprises the first doped region; And common-mode filter is configured on semi-conducting material.
In one embodiment, protection device has the electric capacity that is less than 10pF.
In one embodiment, comprise with the wafer-level package of the single chip integrated common-mode filter of protection device and comprise: the first photosensitive material layer on semi-conducting material and this at least one contact; The second photosensitive material layer on the first photosensitive material layer, is disposed at the first spirality conductive structure in the second photosensitive material layer; The 3rd photosensitive material layer on the second photosensitive material layer and on the first spirality conductive structure; Be disposed at the second spirality conductive structure in the 3rd photosensitive material layer; And for by the electric conducting material of the first spirality electric conducting material and the second spirality electric conducting material electric coupling.
According on the other hand of the present utility model, the method for the manufacture of semiconductor component is provided, comprising: the semi-conducting material that the resistivity with at least 5 Ω cm is provided; Form protection device by semi-conducting material; And common-mode filter monolithic is integrated on semi-conducting material.
In one embodiment, the method is also included in the doped region that forms the first conduction type in semi-conducting material.
In one embodiment, the method also comprises by the doped region of the first conduction type and forms protection device.
In one embodiment, form protection device and comprise formation electrostatic discharge protection device.
In one embodiment, forming electrostatic discharge protection device comprises by semi-conducting material and forms first and second diode.
In one embodiment, provide semi-conducting material to comprise the semi-conducting material of the resistivity with at least 500 Ω cm is provided.
In one embodiment, forming common-mode filter is included in and on dielectric materials layer, forms the first material layer; And on the first material layer, form the first conductive coil structure.
In one embodiment, the first material layer is photosensitive material.
In one embodiment, forming common-mode filter is included in and on conductive coil structure and on a part for the first material layer, forms the second material layer; And on the second material layer, form the second conductive coil structure.
In one embodiment, forming common-mode filter also comprises: on the second conductive coil structure and on a part for the second material layer, form the 3rd material layer; In the 3rd material layer, form opening; And form electric conducting material in the opening in the 3rd material layer.
In one embodiment, first, second and third material layer is photosensitive material.
In one embodiment, the method is also included on the electric conducting material in the opening in the 3rd photosensitive material layer and forms soldered ball.
According on the other hand of the present utility model, provide a kind of for the manufacture of comprising and the method for the wafer-level package of the single chip integrated common-mode filter of protection device, comprising: the semi-conducting material that the resistivity with at least 5 Ω cm is provided; In semi-conducting material, form the first doped region of the first conduction type; Form protection device by the first doped region; And on semi-conducting material, form common-mode filter.
In one embodiment, form protection device and comprise that formation has the protection device of the electric capacity that is less than 10pF.
In one embodiment, the method also comprises at least one contact that is formed into semi-conducting material, and wherein forms common-mode filter and comprise: on semi-conducting material and this at least one contact, form the first photosensitive material layer; And form opening in the first photosensitive material layer that this at least one contact is exposed.
In one embodiment, forming common-mode filter also comprises: on photosensitive material, form the first electric conducting material; On the first electric conducting material, form the first shelter, this first shelter is being protected a part for the first electric conducting material and is being had the opening that a part for the first electric conducting material is exposed, and this opening is in the first photosensitive material layer; And in the opening on the exposed part of the first electric conducting material and in the first photosensitive material layer, form the second electric conducting material.
In one embodiment, forming common-mode filter also comprises: remove the first shelter so that the second electric conducting material part is exposed; Remove the part that is subject to the first shelter protection in the first electric conducting material, so that the first photosensitive material layer segment exposes; And on the exposed part of the first photosensitive material and on the second electric conducting material, form the second photosensitive material layer.
In one embodiment, forming common-mode filter also comprises: in the second photosensitive material layer, form opening; On the second photosensitive material layer, form the second shelter, this second shelter has opening; And in this opening, form the 3rd electric conducting material.
In one embodiment, forming common-mode filter also comprises: in the 3rd photosensitive material layer, form opening; On the 3rd photosensitive material layer, form the 3rd shelter, the 3rd shelter has opening; And in this opening, form the 4th electric conducting material.
In one embodiment, form the first shelter comprise form the first shelter, to there is the opening that has spiral section, and wherein form the second shelter comprise form the second shelter, to there is the opening that has spiral section.
In one embodiment, in the opening on the exposed part of the first electric conducting material and in the first photosensitive material layer, form the second electric conducting material.
In one embodiment, the first material layer is photosensitive material.
Although disclose some preferred embodiment and method herein, but those skilled in the art should be clear according to aforementioned disclosure, in the situation that not departing from spirit and scope of the present utility model, can carry out variation and the amendment of this type of embodiment and method.For example, can be positivity or negative photoresist at novel middle the used photoresist of this use.In addition, can also convert conduction type and form semiconductor device, for example, transistor can be P-channel device, instead of N channel device.Should point out, the utility model should only be limited to by the rule of appended claims and applicable law and the desired scope of principle.
Claims (17)
1. the single chip integrated common-mode filter and the protection device that are configured to wafer-level package, is characterized in that comprising:
There is the semi-conducting material of the resistivity of at least 5 Ω cm;
The protection device being formed by described semi-conducting material;
The first material layer on described semi-conducting material, described the first material layer has the opening of filling with the first electric conducting material; And
The first coil on described the first material layer.
2. single chip integrated common-mode filter according to claim 1 and protection device, also comprises:
Second material layer with the opening of filling with the second electric conducting material on described the first material layer; And
The second coil on described the second material layer.
3. a semiconductor component, is characterized in that comprising:
There is the semi-conducting material of the resistivity of at least 5 Ω cm;
The protection device being formed by described semi-conducting material; And
On described semi-conducting material and common-mode filter single chip integrated with it.
4. semiconductor component according to claim 3, is also included in the doped region of the first conduction type in described semi-conducting material.
5. semiconductor component according to claim 4, wherein said protection device is included as the described doped region of described the first conduction type.
6. semiconductor component according to claim 5, wherein said protection device comprises electrostatic discharge protection device.
7. semiconductor component according to claim 6, wherein said electrostatic discharge protection device comprises first and second diode being formed by described semi-conducting material.
8. semiconductor component according to claim 3, wherein said semi-conducting material has the resistivity of at least 500 Ω cm.
9. semiconductor component according to claim 3, characterized by further comprising:
The first material layer on dielectric materials layer; And
The first conductive coil structure on described the first material layer.
10. semiconductor component according to claim 9, wherein said the first material layer is photosensitive material.
11. semiconductor components according to claim 9, wherein said common-mode filter also comprises:
The second material layer on described conductive coil structure and on a part for described the first material layer; And
The second conductive coil structure on described the second material layer.
12. semiconductor components according to claim 11, wherein said common-mode filter also comprises:
The 3rd material layer on described the second conductive coil structure and on a part for described the second material layer; And
Be disposed at the conductive structure in described the 3rd material layer.
13. semiconductor components according to claim 12, wherein said first, second and third material layer is photosensitive material.
14. semiconductor components according to claim 13, also comprise and are formed as the soldered ball that contacts with the described conductive structure being disposed in described the 3rd material layer.
15. 1 kinds comprise and the wafer-level package of the single chip integrated common-mode filter of protection device, it is characterized in that comprising:
There is the semi-conducting material of the resistivity of at least 5 Ω cm;
The first doped region of the first conduction type in described semi-conducting material; Wherein
Described protection device comprises described the first doped region; And
Described common-mode filter is configured on described semi-conducting material.
16. according to claim 15 comprising and the wafer-level package of the single chip integrated common-mode filter of protection device, wherein said protection device has the electric capacity that is less than 10pF.
17. according to claim 16 comprising and the wafer-level package of the single chip integrated common-mode filter of protection device, be also included at least one contact of described semi-conducting material, and wherein said common-mode filter comprises:
The first photosensitive material layer on described semi-conducting material and described at least one contact;
The second photosensitive material layer on described the first photosensitive material layer,
Be disposed at the first spirality conductive structure in described the second photosensitive material layer;
The 3rd photosensitive material layer on described the second photosensitive material layer and on described the first spirality conductive structure;
Be disposed at the second spirality conductive structure in described the 3rd photosensitive material layer; And
For making the electric conducting material of described the first spirality electric conducting material and described the second spirality electric conducting material electric coupling.
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| US201361859129P | 2013-07-26 | 2013-07-26 | |
| US61/859,129 | 2013-07-26 | ||
| US14/283,913 | 2014-05-21 | ||
| US14/283,913 US9209132B2 (en) | 2013-07-26 | 2014-05-21 | Semiconductor component and method of manufacture |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108988536A (en) * | 2017-06-03 | 2018-12-11 | 建准电机工业股份有限公司 | Stator for motor |
| CN109300881A (en) * | 2017-07-25 | 2019-02-01 | 矽品精密工业股份有限公司 | Electronic package and substrate structure and manufacturing method |
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2014
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108988536A (en) * | 2017-06-03 | 2018-12-11 | 建准电机工业股份有限公司 | Stator for motor |
| CN109300881A (en) * | 2017-07-25 | 2019-02-01 | 矽品精密工业股份有限公司 | Electronic package and substrate structure and manufacturing method |
| TWI672840B (en) * | 2017-07-25 | 2019-09-21 | 矽品精密工業股份有限公司 | Electronic package and substrate structure and the manufacture thereof |
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