CN203966520U - A kind of multiple signals multi-screen splicing disposal system - Google Patents
A kind of multiple signals multi-screen splicing disposal system Download PDFInfo
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- CN203966520U CN203966520U CN201420256634.9U CN201420256634U CN203966520U CN 203966520 U CN203966520 U CN 203966520U CN 201420256634 U CN201420256634 U CN 201420256634U CN 203966520 U CN203966520 U CN 203966520U
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Abstract
The utility model relates to a kind of multiple signals multi-screen splicing disposal system.The utility model comprises the FPGA data processing unit that DVI signal gathering unit and DVI signal gathering unit are connected; Described DVI signal gathering unit is comprised of DVI chromacoder and DVI signal pickup assembly, and the output terminal of described DVI chromacoder is connected with the input end of DVI signal pickup assembly; Described FPGA data processing unit is comprised of FPGA data acquisition module, FPGA Data Segmentation transport module, MCU module and storer, and described FPGA data acquisition module is connected with MCU module is two-way.The utility model can be preset multiple demonstration and window scheme, by default various modes, when multi-screen processor designs, solves to a great extent the output mode simplification of devices at full hardware multi-screen splicing device.
Description
Technical field
The utility model relates to a kind of multiple signals multi-screen splicing disposal system.
Background technology
Multi-screen splicing technology is very extensive in field application such as large screen display, video conferencing system, transportation network monitoring, safety monitoring and medical imagings.
Multi-screen processor is the core component of whole splice displaying system.At present, at home and abroad existing multi-screen splicing processor is based on computer card formula splicer and embedded splicer mostly.Embedded splicer principle of work is first a complete mother picture to be transferred to signal processor, signal processor carries out computing according to output display terminal situation, whole picture is cut into a plurality of pictures, then by the view data that computing is good separately, directly give display terminal.Because adopting each only need of hardware structure Digital Image Processor, embedded splicer processes one type, so do not need powerful CPU to carry out computing multi-channel data, simple single-image splicing can be completed, but high-definition picture splicing and the processing of optional position arbitrary size multiwindow can not be solved.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of multiple signals multi-screen splicing disposal system.
The utility model adopts following technical scheme:
The utility model comprises DVI signal gathering unit and the FPGA data processing unit being connected with DVI signal gathering unit; Described DVI signal gathering unit is comprised of DVI chromacoder and DVI signal pickup assembly, and the output terminal of described DVI chromacoder is connected with the input end of DVI signal pickup assembly;
Described FPGA data processing unit is comprised of FPGA data acquisition module, FPGA Data Segmentation transport module, MCU module and storer, described FPGA data acquisition module is connected with MCU module is two-way, described FPGA data acquisition module is connected with storer is two-way, the output terminal of described FPGA data acquisition module is connected with the input end of FPGA Data Segmentation transport module, and the input end of described FPGA data acquisition module is connected with the output terminal of DVI signal pickup assembly.
The utility model also comprises display screen, and the input end of described display screen is connected with the output terminal of described FPGA Data Segmentation transport module.
Described display screen is by 9 sub-display screens that are divided into 3*3.
The two-way connection of described MCU module.
Described DVI chromacoder turns DVI signal converter, RGB by VGA and turns DVI signal converter, VIDEO and turn DVI signal converter and TCP/IP and turn DVI signal converter and form.
The model that described VGA turns DVI signal converter is that wheat grace science and technology DVI3000-VGA turns DVI video converter, the model that RGB turns DVI signal converter is Extron RGB-DVI 300, the model that VIDEO turns DVI signal converter is that the logical VTH-1Video of humorous letter turns DVI converter, and the model that TCP/IP turns DVI signal converter is BT-VDS-L1000.
The model of described DVI signal pickup assembly is T230E.
The EP2C8Q208C8N that described FPGA data acquisition module and FPGA Data Segmentation transport module all adopt ALTERA company to produce.
The LPC2214 that described MCU module adopts En Zhi Pu company to produce.
Described storer adopts DDR2 SDRAM, and described wireless module adopts wherein one or more of infrared module, bluetooth module, radio-frequency module, Wi-Fi module.
Good effect of the present utility model is as follows:
The utility model can be preset multiple demonstration and window scheme, adopts the mode of wireless remote control (infrared, bluetooth, radio frequency, Wi-Fi etc.) that multi-screen splicing system is selected and controlled.By default various modes, when multi-screen processor designs, by the visual format modularization of common display mode or customer requirement, by the mode of wireless remote control, select to show the output mode simplification that solves to a great extent devices at full hardware multi-screen splicing device.The form of wireless remote control can be the form that button adds preview screen, can be also the form of membrane keyboard screen.
Accompanying drawing explanation
Accompanying drawing 1 is the utility model theory diagram.
Accompanying drawing 2 is the utility model image cutting transfer process figure.
Accompanying drawing 3 is the utility model output signal display screen sectional drawing.
Accompanying drawing 4 is the utility model input signal display screen sectional drawing.
Accompanying drawing 5 is the utility model display mode display screen sectional drawing.
Embodiment
As shown in accompanying drawing 1-5, the utility model comprises FPGA data processing unit, display screen and the wireless module that DVI signal gathering unit, DVI signal gathering unit are connected, described DVI signal gathering unit is comprised of DVI chromacoder and DVI signal pickup assembly, and the output terminal of described DVI chromacoder is connected with the input end of DVI signal pickup assembly, described FPGA data processing unit is by FPGA data acquisition module, FPGA Data Segmentation transport module, MCU module and storer form, described FPGA data acquisition module is connected with MCU module is two-way, described FPGA data acquisition module is connected with storer is two-way, the output terminal of described FPGA data acquisition module is connected with the input end of FPGA Data Segmentation transport module, the input end of described FPGA data acquisition module is connected with the output terminal of DVI signal pickup assembly, the input end of described display screen is connected with the output terminal of described FPGA Data Segmentation transport module, described display screen is comprised of 9 sub-display screens that are divided into 3*3, described wireless module and described two-way connection of MCU module, the model of DVI signal pickup assembly is with three-dimensional DVI video signal collecting card T230E, it can gather 480i, 576i, 480p, 576p, 720p, 1080i, the high definition video source signals such as 1080p.
DVI chromacoder described in the utility model turns DVI signal converter by VGA, RGB turns DVI signal converter, VIDEO turns DVI signal converter and TCP/IP turns DVI signal converter composition, the model that described VGA turns DVI signal converter is that wheat grace science and technology DVI3000-VGA turns DVI video converter, the model that RGB turns DVI signal converter is Extron RGB-DVI 300, the model that VIDEO turns DVI signal converter be humorous letter logical/to turn the model that DVI converter and TCP/IP turn DVI signal converter be BT-VDS-L1000 to VTH-1Video, the EP2C8Q208C8N that described FPGA data acquisition module and FPGA Data Segmentation transport module all adopt ALTERA company to produce, the LPC2214 that described MCU module adopts En Zhi Pu company to produce, described storer adopts DDR2 SDRAM, described wireless module adopts infrared module, bluetooth module, radio-frequency module, wherein one or more of Wi-Fi module.
The utility model, with 9 screens, accesses 5 signals, shows that 4 signals are that example processor processing procedure is as follows:
(1) common image input signal DVI signal accesses by DVI video interface, VGA signal accesses by VGA video interface, rgb signal accesses by rgb video interface, and VIDEO vision signal accesses by VIDEO video interface, and network signal accesses by network interface.After the input of multichannel data signal, by signal converter separately, be converted to DVI signal.
(2) FPGA data acquisition module, by receiving all DVI signal datas, is deposited in DDR2 SDRAM, makes the FPGA data acquisition module pattern class image data definite according to MCU module, forms the packet of whole screen image.
(3) FPGA data acquisition module, by the data packet transmission forming to FPGA Data Segmentation transport module, cuts packet, and the data image that each screen display is shown transfers in corresponding screen display.(as shown in Figure 2)
(4) MCU module detection signal access number, communicates with wireless module.MCU module detects the signal number of connecting system at that time, and it is transferred to wireless remote control module by wireless module, determines displayable signal number.
(5) wireless remote control module can adopt the wireless remote control methods such as infrared, bluetooth, radio frequency, Wi-Fi.The form of wireless remote control can be the form that button adds preview screen, can be also the form of membrane keyboard screen.
(6) button of wireless remote control module adds the form of preview screen and the form class of membrane keyboard screen seemingly, can design special remote control screen display device, also can design mobile phone A PP, by mobile phone, controls demonstration.
(7) screen display of wireless remote control module has 3 cascade windows.First cascade window is to select display number, the signal number that this window can select user to want multi-screen to show, for example, access 5 signals, but only want to show 4 signals, just can select to show 4 signals, now can only select the number that is less than or equal to access signal to show, the options of other display numbers is grey, can not select.(shown in Fig. 3) second cascade window is to select to show access signal, and the signal of access is selected to show, for example, accesses 5 signals, shows 4 signals, will select 4 signals in 5 signals.(shown in Fig. 4) the 3rd cascade window is preference pattern, and display mode is selected, and this window has preview mode, and user can see the design sketch after demonstration.After (shown in Fig. 5) determines, by multi-screen processor, large-size screen monitors show just can see the picture of demonstration.
Claims (10)
1. a multiple signals multi-screen splicing disposal system, is characterized in that it comprises DVI signal gathering unit and the FPGA data processing unit being connected with DVI signal gathering unit; Described DVI signal gathering unit is comprised of DVI chromacoder and DVI signal pickup assembly, and the output terminal of described DVI chromacoder is connected with the input end of DVI signal pickup assembly;
Described FPGA data processing unit is comprised of FPGA data acquisition module, FPGA Data Segmentation transport module, MCU module and storer, described FPGA data acquisition module is connected with MCU module is two-way, described FPGA data acquisition module is connected with storer is two-way, the output terminal of described FPGA data acquisition module is connected with the input end of FPGA Data Segmentation transport module, and the input end of described FPGA data acquisition module is connected with the output terminal of DVI signal pickup assembly.
2. a kind of multiple signals multi-screen splicing disposal system according to claim 1, is characterized in that it also comprises display screen, and the input end of described display screen is connected with the output terminal of described FPGA Data Segmentation transport module.
3. a kind of multiple signals multi-screen splicing disposal system according to claim 2, is characterized in that described display screen is comprised of 9 sub-display screens that are divided into 3*3.
4. a kind of multiple signals multi-screen splicing disposal system according to claim 3, is characterized in that it also comprises wireless module, described wireless module and described two-way connection of MCU module.
5. according to a kind of multiple signals multi-screen splicing disposal system described in claim 1,2,3 or 4, it is characterized in that described DVI chromacoder turns DVI signal converter, RGB by VGA and turns DVI signal converter, VIDEO and turn DVI signal converter and TCP/IP and turn DVI signal converter and form.
6. a kind of multiple signals multi-screen splicing disposal system according to claim 5, it is characterized in that the model that described VGA turns DVI signal converter is that wheat grace science and technology DVI3000-VGA turns DVI video converter, the model that RGB turns DVI signal converter is Extron RGB-DVI 300, the model that VIDEO turns DVI signal converter is that the logical VTH-1Video of humorous letter turns DVI converter, and the model that TCP/IP turns DVI signal converter is BT-VDS-L1000.
7. a kind of multiple signals multi-screen splicing disposal system according to claim 6, the model that it is characterized in that described DVI signal pickup assembly is T230E.
8. a kind of multiple signals multi-screen splicing disposal system according to claim 7, is characterized in that the EP2C8Q208C8N that described FPGA data acquisition module and FPGA Data Segmentation transport module all adopt ALTERA company to produce.
9. a kind of multiple signals multi-screen splicing disposal system according to claim 8, is characterized in that the LPC2214 that described MCU module adopts En Zhi Pu company to produce.
10. a kind of multiple signals multi-screen splicing disposal system according to claim 9, it is characterized in that described storer adopts DDR2 SDRAM, described wireless module adopts wherein one or more of infrared module, bluetooth module, radio-frequency module, Wi-Fi module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420256634.9U CN203966520U (en) | 2014-05-20 | 2014-05-20 | A kind of multiple signals multi-screen splicing disposal system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420256634.9U CN203966520U (en) | 2014-05-20 | 2014-05-20 | A kind of multiple signals multi-screen splicing disposal system |
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| Publication Number | Publication Date |
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| CN203966520U true CN203966520U (en) | 2014-11-26 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103971660A (en) * | 2014-05-20 | 2014-08-06 | 河北科技大学 | Multipath signal multi-screen splicing processing system |
| CN110502204A (en) * | 2019-08-26 | 2019-11-26 | 深圳蓝普科技有限公司 | A kind of splice displaying system and its signal control method |
-
2014
- 2014-05-20 CN CN201420256634.9U patent/CN203966520U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103971660A (en) * | 2014-05-20 | 2014-08-06 | 河北科技大学 | Multipath signal multi-screen splicing processing system |
| CN110502204A (en) * | 2019-08-26 | 2019-11-26 | 深圳蓝普科技有限公司 | A kind of splice displaying system and its signal control method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141126 Termination date: 20150520 |
|
| EXPY | Termination of patent right or utility model |