CN203965539U - A kind of TCPST bypass breaker interlock logic simulator - Google Patents
A kind of TCPST bypass breaker interlock logic simulator Download PDFInfo
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- CN203965539U CN203965539U CN201420357622.5U CN201420357622U CN203965539U CN 203965539 U CN203965539 U CN 203965539U CN 201420357622 U CN201420357622 U CN 201420357622U CN 203965539 U CN203965539 U CN 203965539U
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Abstract
A kind of TCPST bypass breaker interlock logic simulator, belong to POWER SYSTEM EMERGENCY holding circuit device, relate in particular to a kind of simulation testing device for controllable phase shifter relay protection circuit, comprise the first to the 7th AND circuit, the first OR circuit and the second OR circuit, the output terminal of the first AND circuit and the second AND circuit is connected to the first OR circuit, and provides bypass breaker combined floodgate interlocking signal by the first OR circuit; The second AND circuit, the 3rd AND circuit and the 4th AND circuit are connected to the 5th AND circuit; The 5th AND circuit, the 6th AND circuit and the 7th AND circuit are connected to the second OR circuit, and provide bypass breaker separating brake interlocking signal by the output terminal of the second OR circuit.This device can be simulated the interlock protection state of TCPST device truly, and for research or the design of TCPST device provides corresponding simulation result, its logical relation is succinct, and reliable in action is easy to realize, and has advantages of cross-platform emulation testing.
Description
Technical field
The utility model belongs to POWER SYSTEM EMERGENCY holding circuit device, relates in particular to a kind of simulation testing device for controllable phase shifter relay protection circuit.
Background technology
Along with socioeconomic sustainable development, life and production are effectively stimulating developing rapidly of electric system to the ever-increasing demand of electric power supply.The space length of energy centre and load center is large capacity, the long objective reason apart from transmission of electric energy.In order to meet transmission of electricity demand, the scale expanding day of electric power networks.Because being in operation, electric system is subject to the steady constraint of the limit of equipment heat, the voltage drop of transmission line of electricity constraint, N-1 Static Security Constraints, the constraint of system small signal stability, voltage stability constraint, Transient Stability Constraints and reliability Reserve Constraint make the ability to transmit electricity of system be difficult to be utilized cmpletely.The potentiality of excavating existed system by novel control element are basic ideas for nearest many decades power science research, electric power network technique upgrading.Once electrical network builds up, the electric parameter of transmission line of electricity reality, system load flow is retrained by Ohm law, Kirchoff law, electric power networks is unique, and what can control fast is to change topological structure by line switching.Certain constraint that the free trend that this shortage is controlled is often moved due to the system that is subject to is had to reduce the utilization factor of system equipment or made system operate in a technical economical index is not good state.In the evolution of power system technology, in order to make electrical network have certain control freedom degree, the reactive-load compensation in parallel realizing with mechanical switching device shifter, the technology such as reactive-load compensation, phase shifter and application of adjustable tap transformer of connecting have successively been born.But mechanical device cannot meet the dynamic demand for control of system in speed, on frequency, cannot fully meet the requirement of systematic steady state regulation and control.Development along with power electronic devices, controllable phase shifter (mainly refers to thyristor control phase shifter, Thyristor Controlled Phase Shifting Transformer, in the following description also referred to as phase shifter or TCPST) obtained studying widely.Due to the fast response characteristic of power electronic devices, TCPST can not only quick adjustment Line Flow, can also realize functions such as improving power system transient stability, damping system vibration.The gordian technique research of carrying out TCPST has great importance to strengthening control device, the pattern of optimizing the system operation of supergrid, and wherein, the research of the control resist technology of TCPST has vital effect to the safety of system, stable operation.Due to the character of supergrid system, the gordian technique research of TCPST mainly realizes by emulation technology.
The control system of controllable phase shifter is the key of system operation, for the operation and management level that improves equipment, has vital role.The control object of control system is isolating switch, disconnecting link and the thyristor becoming in secondary side pressure-control circuit in parallel in system architecture.The controllable phase shifter operation of connecting in the line, the switching of its running status, while breaking down, from system, the operation such as excision all should normally operate to precondition with what do not affect transmission line of electricity fast.Take monophase system as example, and the allocation plan of controllable phase shifter and isolating switch, isolation switch as shown in Figure 1.In figure, controllable phase shifter is comprised of series transformer B, shunt transformer E and thyristor groups T, winding B1, the B2 of series transformer B primary side is connected to the winding E1 of shunt transformer E primary side, and is connected in power network line and moved by isolating switch and isolation switch; Thyristor groups T is connected to the winding B3 of series transformer B secondary side and three winding E2, E3, the E4 of shunt transformer E secondary side.Thyristor groups T in figure is schematic diagram, wherein each independently thyristor in real system, by a plurality of thyristor connection in series-parallel, formed.
Due to the character of supergrid system, the research of the gordian technique of TCPST or the design of application system, must test and emulation said system, and with reference to test and simulation result, the foundation that result is verified or conduct is revised to research or design.
Utility model content
The purpose of this utility model is that a kind of TCPST bypass breaker interlock logic simulator will be provided, it can simulate reflection TCPST bypass breaker interlock logic situation truly, for applied research or the design of controllable phase shifter provides corresponding simulation result, solve the technical matters that applied research or design for controllable phase shifter provide verification platform.
The utility model solves the problems of the technologies described above adopted technical scheme:
A TCPST bypass breaker interlock logic simulator, comprises the first to the 7th AND circuit, the first OR circuit and the second OR circuit, it is characterized in that:
Two input ends of the first AND circuit, be connected respectively to the first bypass isolating switch and the second bypass isolating switch minute position a signal end;
Four input ends of the second AND circuit, are connected respectively to minute position signal end of the first grounding shunt switch and the second grounding shunt switch, and the co-bit signal end of the first bypass isolating switch and the second bypass isolating switch;
The output terminal of the first AND circuit and the second AND circuit, is connected respectively to two input ends of the first OR circuit;
Described TCPST bypass breaker interlock logic simulator, by the output terminal of the first OR circuit, provides bypass breaker combined floodgate interlocking signal;
Four input ends of the 3rd AND circuit, are connected respectively to the co-bit signal end of the first isolating switch and the second isolating switch and the co-bit signal end of the first disconnector and the second disconnector;
Two input ends of the 4th AND circuit, be connected respectively to the first circuit interrupter grounding switch and the second circuit interrupter grounding switch minute position a signal end;
The output terminal of the second AND circuit, the 3rd AND circuit and the 4th AND circuit, is connected respectively to three input ends of the 5th AND circuit;
Four input ends of the 6th AND circuit, are connected respectively to minute position signal end of the first bypass isolating switch and the second bypass isolating switch, and the co-bit signal end of the first grounding shunt switch and the second grounding shunt switch;
Four input ends of the 7th AND circuit, are connected respectively to the co-bit signal end of the first bypass isolating switch and the second bypass isolating switch and the co-bit signal end of the first grounding shunt switch and the second grounding shunt switch;
The output terminal of the 5th AND circuit, the 6th AND circuit and the 7th AND circuit, is connected respectively to three input ends of the second OR circuit;
Described TCPST bypass breaker interlock logic simulator, by the output terminal of the second OR circuit, provides bypass breaker separating brake interlocking signal.
A kind of preferred technical scheme of TCPST bypass breaker interlock logic simulator of the present utility model, is characterized in that described the first AND circuit, the 4th AND circuit and the 5th AND circuit are comprised of 3 input ends three and door integrated circuit; The second described AND circuit, the 3rd AND circuit, the 6th AND circuit and the 7th AND circuit form with door integrated circuit by two 4 input ends are two; The first described OR circuit and the second OR circuit are comprised of 3 input ends three or door integrated circuit.
A kind of preferably technical scheme of TCPST bypass breaker interlock logic simulator of the present utility model, it is characterized in that described TCPST bypass breaker interlock logic simulator is also provided with thyristor pulse block signal output terminal, described thyristor pulse block signal output terminal is connected to thyristor loop, when system enters isolation or inspecting state, described TCPST bypass breaker interlock logic simulator, blocks thyristor triggering impulse signal by described thyristor pulse block signal output terminal.
The beneficial effects of the utility model are:
1. the interlock protection state of TCPST device can be simulated, be reflected to TCPST bypass breaker interlock logic simulator of the present utility model truly, for research or the design of TCPST device provides corresponding simulation result;
2. the logical relation of TCPST bypass breaker interlock logic simulator of the present utility model is succinct, and reliable in action is easy to realize, and has advantages of cross-platform emulation testing.
Accompanying drawing explanation
Fig. 1 is the allocation plan schematic diagram of controllable phase shifter control loop;
Fig. 2 is the main circuit diagram of TCPST bypass breaker interlock logic simulator of the present utility model;
Fig. 3 is the logical relation schematic diagram of TCPST bypass breaker interlock logic simulator of the present utility model;
The label of each parts in above figure: 11-17 is the first AND circuit to the seven AND circuit, 21-22 is the first OR circuit to the second OR circuit, HVB-SE is bypass breaker, BS1 is the first bypass isolating switch, BS2 is the second bypass isolating switch, BES1 is the first grounding shunt switch, BES2 is the second grounding shunt switch, BRK-SE1 is the first isolating switch, BRK-SE2 is the second isolating switch, DS1 is the first disconnector, DS2 is the second disconnector, DES1 is the first circuit interrupter grounding switch, DES2 is the second circuit interrupter grounding switch.
Embodiment
In order to understand better technique scheme of the present utility model, below in conjunction with drawings and Examples, be explained in further detail.
As shown in Figure 1, two bus nodes S are connected by transmission line of electricity with L the allocation plan of controllable phase shifter control loop, and phase shifter TCPST connects and moves in the line, and thyristor voltage regulation loop T is controlling the output response characteristic of TCPST.The protection system of controllable phase shifter is the guarantee of device security, stable operation, to reducing fault coverage, preventing that device damage is significant.The switching of TCPST running status, fast operation such as excision grade from system while breaking down, all should normally operate to precondition with what do not affect transmission line of electricity.The setting of protection should be able to cover all trouble spots, fault type, does not have dead band.During phase shifter place line failure, can be divided into troubles inside the sample space and external area error by fault scene, fault subregion is referring to Fig. 1.Troubles inside the sample space refers to and comprises the fault occurring within the scope of TCPST body and phase shifter both sides isolating switch.External area error refers to the fault that the region outside the isolating switch of phase shifter both sides occurs, and comprises the situation that circuit, two side bus, adjacent lines break down.It is abnormal etc. that the common fault in thyristor control loop is refused triggering, false triggering, Trigger Angle, can cause circuit cutout, short circuit in winding, system to produce the faults such as harmonic wave and occur, and to system, normal operation has a huge impact.Isolating switch in phase shifter system structure plays a part to switch phase shifter state in normal course of operation, and deciliter combinations of states of these equipment can form different running statuses, is respectively: operation, bypass, isolation, maintenance and bypass breaker maintenance.Can be rapidly when breaking down by phase shifter bypass or excise from system, reduce fault coverage, protection system equipment.For example, when thyristor loop T breaks down, the first isolating switch BRK-SE1 of the bypass breaker HVB-SE that need close, tripping phase shifter both sides and the second isolating switch BRK-SE2 excise TCPST and locking trigger pulse from circuit.In order to prevent maloperation, while controlling deciliter state of isolating switch, disconnecting link, must there is certain logical interlock relation.Because isolating switch in phase shifter structure, isolation switch are numerous, and relate to the control of thyristor, its interlock logic is also more complicated.TCPST bypass breaker interlock logic simulator of the present utility model can provide the divide/combined floodgate interlocking signal of relative breaker or chopper switch: when described divide/combined floodgate interlocking signal is logical one, allow the divide/closing operation of corresponding isolating switch or chopper switch; When described divide/combined floodgate interlocking signal is logical zero, forbid the divide/closing operation of corresponding isolating switch or chopper switch.
Fig. 2 is the main circuit diagram of TCPST bypass breaker interlock logic simulator of the present utility model, comprises the first to the 7th AND circuit 11-17, the first OR circuit 21 and the second OR circuit 22, wherein:
Two input ends of the first AND circuit 11, be connected respectively to the first bypass isolating switch BS1 and the second bypass isolating switch BS2 minute position a signal end;
Four input ends of the second AND circuit 12, are connected respectively to a minute position signal end of the first grounding shunt switch BES1 and the second grounding shunt switch BES2, and the co-bit signal end of the first bypass isolating switch BS1 and the second bypass isolating switch BS2;
The output terminal of the first AND circuit 11 and the second AND circuit 12, is connected respectively to two input ends of the first OR circuit 21;
Described TCPST bypass breaker interlock logic simulator, by the output terminal of the first OR circuit 21, provides bypass breaker HVB-SE combined floodgate interlocking signal;
Four input ends of the 3rd AND circuit 13, are connected respectively to the co-bit signal end of the first isolating switch BRK-SE1 and the second isolating switch BRK-SE2 and the co-bit signal end of the first disconnector DS1 and the second disconnector DS2;
Two input ends of the 4th AND circuit 14, be connected respectively to the first circuit interrupter grounding switch DES1 and the second circuit interrupter grounding switch DES2 minute position a signal end;
The output terminal of the second AND circuit 12, the 3rd AND circuit 13 and the 4th AND circuit 14, is connected respectively to three input ends of the 5th AND circuit 15;
Four input ends of the 6th AND circuit 16, are connected respectively to a minute position signal end of the first bypass isolating switch BS1 and the second bypass isolating switch BS2, and the co-bit signal end of the first grounding shunt switch BES1 and the second grounding shunt switch BES2;
Four input ends of the 7th AND circuit 17, are connected respectively to the co-bit signal end of the first bypass isolating switch BS1 and the second bypass isolating switch BS2 and the co-bit signal end of the first grounding shunt switch BES1 and the second grounding shunt switch BES2;
The output terminal of the 5th AND circuit 15, the 6th AND circuit 16 and the 7th AND circuit 17, is connected respectively to three input ends of the second OR circuit 22;
Described TCPST bypass breaker interlock logic simulator, by the output terminal of the second OR circuit 22, provides bypass breaker HVB-SE separating brake interlocking signal.
An embodiment of TCPST bypass breaker interlock logic simulator of the present utility model adopts 74 serial integrated logic circuit elements to realize, wherein, the first AND circuit 11, the 4th AND circuit 14 and the 5th AND circuit 15 are comprised of 3 input ends three and door integrated circuit 7411; The second AND circuit 12, the 3rd AND circuit 13, the 6th AND circuit 16 and the 7th AND circuit 17 form with door integrated circuit 7422 by two 4 input ends are two; The first OR circuit 21 and the second OR circuit 22 are comprised of 3 input ends three or door integrated circuit 7427.
In an embodiment of TCPST bypass breaker interlock logic simulator of the present utility model, also be provided with thyristor pulse block signal output terminal, described thyristor pulse block signal output terminal is connected to thyristor loop T, when system enters isolation or inspecting state, described TCPST bypass breaker interlock logic simulator, blocks thyristor triggering impulse signal by described thyristor pulse block signal output terminal.
Fig. 3 has provided the logical relation schematic diagram of TCPST bypass breaker interlock logic simulator of the present utility model, adopt actual electrical sub-element (true environment) or with computer software (virtual environment), all can realize logical relation or the logic function of this device, that is to say, TCPST bypass breaker interlock logic simulator of the present utility model, both can adopt above-mentioned integrated logic circuit element to realize, can use chip microprocessor programming simulation to realize, or, according to the logical organization shown in Fig. 3, in virtual environment, with computer software, simulate to realize, can be widely used in the research of TCPST device interlocking protective system, design, manufacture field.
Those of ordinary skill in the art will be appreciated that; above embodiment is only for the technical solution of the utility model is described; and be not used as restriction of the present utility model; any variation of the above embodiment being done based on connotation of the present utility model, modification, all will drop in the protection domain of claim of the present utility model.
Claims (3)
1. a TCPST bypass breaker interlock logic simulator, comprises the first to the 7th AND circuit, the first OR circuit and the second OR circuit, it is characterized in that:
Two input ends of the first AND circuit, be connected respectively to the first bypass isolating switch and the second bypass isolating switch minute position a signal end;
Four input ends of the second AND circuit, are connected respectively to minute position signal end of the first grounding shunt switch and the second grounding shunt switch, and the co-bit signal end of the first bypass isolating switch and the second bypass isolating switch;
The output terminal of the first AND circuit and the second AND circuit, is connected respectively to two input ends of the first OR circuit;
Described TCPST bypass breaker interlock logic simulator, by the output terminal of the first OR circuit, provides bypass breaker combined floodgate interlocking signal;
Four input ends of the 3rd AND circuit, are connected respectively to the co-bit signal end of the first isolating switch and the second isolating switch and the co-bit signal end of the first disconnector and the second disconnector;
Two input ends of the 4th AND circuit, be connected respectively to the first circuit interrupter grounding switch and the second circuit interrupter grounding switch minute position a signal end;
The output terminal of the second AND circuit, the 3rd AND circuit and the 4th AND circuit, is connected respectively to three input ends of the 5th AND circuit;
Four input ends of the 6th AND circuit, are connected respectively to minute position signal end of the first bypass isolating switch and the second bypass isolating switch, and the co-bit signal end of the first grounding shunt switch and the second grounding shunt switch;
Four input ends of the 7th AND circuit, are connected respectively to the co-bit signal end of the first bypass isolating switch and the second bypass isolating switch and the co-bit signal end of the first grounding shunt switch and the second grounding shunt switch;
The output terminal of the 5th AND circuit, the 6th AND circuit and the 7th AND circuit, is connected respectively to three input ends of the second OR circuit;
Described TCPST bypass breaker interlock logic simulator, by the output terminal of the second OR circuit, provides bypass breaker separating brake interlocking signal.
2. TCPST bypass breaker interlock logic simulator according to claim 1, is characterized in that described the first AND circuit, the 4th AND circuit and the 5th AND circuit are comprised of 3 input ends three and door integrated circuit; The second described AND circuit, the 3rd AND circuit, the 6th AND circuit and the 7th AND circuit form with door integrated circuit by two 4 input ends are two; The first described OR circuit and the second OR circuit are comprised of 3 input ends three or door integrated circuit.
3. TCPST bypass breaker interlock logic simulator according to claim 1 and 2, it is characterized in that described TCPST bypass breaker interlock logic simulator is also provided with thyristor pulse block signal output terminal, described thyristor pulse block signal output terminal is connected to thyristor loop, when system enters isolation or inspecting state, described TCPST bypass breaker interlock logic simulator, blocks thyristor triggering impulse signal by described thyristor pulse block signal output terminal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420357622.5U CN203965539U (en) | 2014-06-30 | 2014-06-30 | A kind of TCPST bypass breaker interlock logic simulator |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420357622.5U CN203965539U (en) | 2014-06-30 | 2014-06-30 | A kind of TCPST bypass breaker interlock logic simulator |
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| CN203965539U true CN203965539U (en) | 2014-11-26 |
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| CN201420357622.5U Expired - Lifetime CN203965539U (en) | 2014-06-30 | 2014-06-30 | A kind of TCPST bypass breaker interlock logic simulator |
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Granted publication date: 20141126 |