CN203896333U - CDR phase discriminator system - Google Patents
CDR phase discriminator system Download PDFInfo
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- CN203896333U CN203896333U CN201420275490.1U CN201420275490U CN203896333U CN 203896333 U CN203896333 U CN 203896333U CN 201420275490 U CN201420275490 U CN 201420275490U CN 203896333 U CN203896333 U CN 203896333U
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Abstract
The utility model discloses a CDR phase discriminator system. The CDR phase discriminator system comprises at least four groups of phase discrimination equipment and two OR gates; each group of the phase discrimination equipment comprises a phase discriminator, a first trigger and a second trigger, sampling information obtained through sampling at three continuous phase time points of a sampling clock is input to the phase discriminators, the phase discriminators perform contrastive analyses on the input sampling information, and first output ends and second output ends of the phase discriminators are respectively connected with input ends of the first triggers and input ends of the second triggers; a clock, the phase of which is different from the phase of the current sampling clock, of system clocks is input to clock control ends of the first triggers and the second triggers, and the other clock, the phase of which is different from the phase of the current sampling clock, of the system clocks is input to enablement ends of the first triggers and the second triggers; and the first trigger of each group of the phase discrimination equipment is connected with an input end of one or the OR gates, and the second trigger of each group of the phase discrimination equipment is connected with an input end of the other of the OR gates. According to the CDR phase discriminator system, system delays and jitters of the CDR phase discriminator system are reduced, and judgment accuracy is improved.
Description
Technical field
The utility model relates to semiconductor integrated circuit field, relates more specifically to a kind of CDR phase discriminator system.
Background technology
Please refer to Fig. 1 and Fig. 2, traditional CDR phase discriminator system as shown in Figure 2, comprise data simultaneous module and phase discriminator module, data simultaneous module is synchronously exported the data (as the S1 in Fig. 1, S2, S3, S4) of input in the information (D1, D2, D3, D4) of out of phase time point (clk0-clk7) the sampling acquisition of system clock clk; Wherein, the phase place of clk1-clk7 has postponed successively one with respect to system clock clk and has postponed unit, and the relative clk of phase place of clk0 does not postpone; The length of the concrete time of this delay unit by data determines, referring to Fig. 1, when this delay unit is set, clk0, clk2, clk4, clk6 sample in the centre position of corresponding data, and clk1, clk3, clk5, clk7 sample in Data flipping position; Phase discriminator module judgement sampling clock (clk0-clk7) is with respect to data (S1, S2, S3, S4) lead-lag, send judgement information to CDR with feedback regulation clock data relative position.
Please combination is with reference to figure 3 again, and Fig. 3 is the structured flowchart of phase discriminator module in prior art.As shown in the figure, information D 1, D2, D3, D4 that sampling obtains, input respectively four phase discriminators, and each phase discriminator is used along sampled value and adjacent data sampled value and compared to adjudicate sampling along lead-lag.Above-mentioned have 4 phase over-samplings, thus have 4 available along information, use 4 parts of same circuits to judge respectively, as shown in Figure 3.Information after phase discriminator judgement is input summer 1, adder 2 respectively, and 1 pair of phase discriminator of adder 1 is added with the phase demodulation information of phase discriminator 2, and 2 pairs of phase discriminators of adder 3 are added with the phase demodulation information of phase discriminator 4; 1 pair of adder 1 addition result of trigger is carried out intermediate storage to guarantee timing closure, and 2 pairs of adder 2 addition result of trigger store to guarantee timing closure; 3 pairs of triggers of adder 1 are added again with the phase demodulation information sum of trigger 2 outputs; 3 pairs of adder 3 addition result of trigger are carried out intermediate storage to guarantee timing closure; Majority vote/ballot device is done most ballot judgements to phase discriminator 1, phase discriminator 2, phase discriminator 3, phase discriminator 4 sums, judgement current data clock phase relativeness; Finally by trigger 4 output two court verdict out1, out2.
In CDR phase discriminator system, phase information is adjudicated and is effectively fed back to control circuit and control the new phase change time and be called system delay.The size of system delay value has directly determined CDR phase discriminator system effect bandwidth, this value is larger, from phase information, adjudicate and effectively feed back to control circuit to control time of new phase change longer, the phase information cumulative amount of mistake is also larger, and it is also more and more far away that sampling phase point departs from ideal point.In the CDR of prior art phase discriminator system, data simultaneous module need to be used 1.5 cycle T (T=4*UI, UI was 4 phase over-sampling cycles) data are synchronous, in the phase discriminator module of cascade, used 3 grades of triggers (trigger 1,2, trigger 3, trigger 4), every one-level trigger need to use 1T to incite somebody to action result before this and do majority vote; Thereby the system delay that whole system is introduced is altogether 1.5T+3T=4.5T.So large system delay will be introduced larger CDR thrashing, and the court verdict error of CDR phase discriminator system is increased.
Therefore, be necessary to provide a kind of improved CDR phase discriminator system to overcome above-mentioned defect.
Utility model content
The purpose of this utility model is to provide a kind of CDR phase discriminator system, and CDR phase discriminator system of the present utility model has reduced system delay, has reduced the shake of CDR phase discriminator system, has improved judgement precision.
For achieving the above object, the utility model provides a kind of CDR phase discriminator system, comprise sampler, system clock postpones to form sampling clock to its phase place, described sampler is sampled to the data message of input at the different phase time point of sampling clock, wherein, described CDR phase discriminator system also comprise at least four group phase demodulation equipment and two or, described in every group, phase demodulation equipment comprises phase discriminator, the first trigger and the second trigger, sampler is inputted phase discriminator described in each by the sample information obtaining in the sampling of three continuous phase time points of sampling clock, described phase discriminator is analyzed the sample information of input, and described in each, phase discriminator has two outputs, the first output of described phase discriminator is connected with the input of described the first trigger, the second output of described phase discriminator is connected with the input of described the second trigger, the different clock of system clock one and the phase place of current sampling clock is inputted respectively the clock control end of described the first trigger and the second trigger, and the different clock of phase place of system clock another and current sampling clock is inputted respectively the Enable Pin of described the first trigger and the second trigger, the output of described first trigger of every group of phase demodulation equipment all with described in one or door input is connected, the output of described second trigger of every group of phase demodulation equipment all with described in another or input be connected.
Preferably, described sampling clock is that system clock postpones 0-N the clock postponing after unit, and the length of each delay unit is input data information length half, and N is positive integer.
Preferably, input three sample information of phase discriminator described in each, the sample information that first sample information obtains for sampling previous data message centre position, second sample information that sample information is the previous data message of sampling and rear data message upturned position acquisition, the 3rd sample information that sample information obtains for the rear data message centre position of sampling, and this two data message is two adjacent data messages.
Preferably, input the sampling clock that the clock of the first trigger and the second trigger described in each is sampled data information centre position.
Preferably, described phase demodulation equipment is four groups, the sampling clock of the first trigger of described first group of phase demodulation equipment and the input of the clock control end of the second trigger is to have postponed 6 system clocks that postpone unit, and the sampling clock of the first trigger of described first group of phase demodulation equipment and the input of the Enable Pin of the second trigger is to have postponed 4 system clocks that postpone unit; The sampling clock of the first trigger of described second group of phase demodulation equipment and the input of the clock control end of the second trigger is to have postponed 0 system clock that postpones unit, and the clock of the first trigger of described second group of phase demodulation equipment and the input of the Enable Pin of the second trigger is to have postponed 6 system clocks that postpone unit; The sampling clock of the first trigger of described the 3rd group of phase demodulation equipment and the input of the clock control end of the second trigger is to have postponed 2 system clocks that postpone unit, and the sampling clock of the first trigger of described the 3rd group of phase demodulation equipment and the input of the Enable Pin of the second trigger is to have postponed 0 system clock that postpones unit; The sampling clock of the first trigger of described the 4th group of phase demodulation equipment and the input of the clock control end of the second trigger is to have postponed 4 system clocks that postpone unit, and the sampling clock of the first trigger of described the 4th group of phase demodulation equipment and the input of the clock control end of the second trigger is to have postponed 2 system clocks that postpone unit.
Compared with prior art, CDR phase discriminator system of the present utility model is only used one-level phase discriminator equipment to complete phase discrimination function, and only includes one-level trigger in described phase discriminator equipment, and the system delay of generation is 0.5T, reduce the shake of CDR phase discriminator system, improved judgement precision
By following description also by reference to the accompanying drawings, it is more clear that the utility model will become, and these accompanying drawings are used for explaining the utility model.
Accompanying drawing explanation
Fig. 1 is the sequential chart of the CDR phase demodulation systematic sampling of prior art.
Fig. 2 is the structured flowchart of the CDR phase demodulation system of prior art.
Fig. 3 is the structured flowchart of phase discriminator module of the CDR phase demodulation system of prior art.
Fig. 4 is the sequential chart of CDR phase demodulation systematic sampling of the present utility model.
Fig. 5 is the structured flowchart of CDR phase demodulation system of the present utility model.
Embodiment
With reference now to accompanying drawing, describe embodiment of the present utility model, in accompanying drawing, similarly element numbers represents similar element.As mentioned above, the utility model provides a kind of CDR phase discriminator system, and CDR phase discriminator system of the present utility model has reduced system delay, has reduced the shake of CDR phase discriminator system, has improved judgement precision.
Incorporated by reference to reference to figure 4 and Fig. 5, CDR phase discriminator system of the present utility model comprises: sampler (not shown), at least four group phase demodulation equipment and two or (OR1, OR2).System clock clk postpones to form sampling clock to its phase place, and described sampler is at sampling clock different phase time point (clk0, clk1, clk2, clk3, clk4, clk5, clk6, clk7 ...) the data message data of input is sampled.Described in every group, phase demodulation equipment comprises phase discriminator PHDJDG, the first trigger DFF1 and the second trigger DFF2, sampler is by the sample information (M0, M1, M2, M3, M4, M5, the M6 that obtain in three continuous phase time point samplings of sampling clock ...) inputting phase discriminator PHDJDG described in each, described phase discriminator PHDJDG is analyzed the sample information of input; And described in each, phase discriminator PHDJDG has two outputs, the first output up of described phase discriminator PHDJDG is connected with the input of described the first trigger DFF1, and the second output dn of described phase discriminator PHDJDG is connected with the input of described the second trigger DFF2; Thereby described phase discriminator PHDJDG inputs to described the first trigger DFF1 and the second trigger DFF2 by its court verdict by its two output.The different clock of system clock one and the phase place of current sampling clock is inputted respectively the clock control end of described the first trigger DFF1 and the second trigger DFF2, and the different clock of phase place of system clock another and current sampling clock is inputted respectively the Enable Pin of described the first trigger DFF1 and the second trigger DFF2; Thereby when two sampling clocks of described the first trigger DFF1 of input and the second trigger DFF2 are rising edge, described the first trigger DFF1 and the second trigger DFF2 export the court verdict of described phase discriminator PHDJDG.The output of the described first trigger DFF1 of every group of phase demodulation equipment all with described in one or the input of door OR1 is connected, the output of the described second trigger DFF2 of every group of phase demodulation equipment all with described in another or the input of OR2 be connected; Thereby arbitrary sample information all can be exported court verdict by described or door OR1, OR2 by described phase discriminator PHDJDG judgement for lead-lag, to facilitate, carry out subsequent adjustment.Wherein, described sampling clock is that system clock clk postpones 0-N the clock postponing after unit, and the length of each delay unit is input data information length half, and N is positive integer, and the value of N can according to how many concrete settings of sampled data information data; The phase place of sampling clock clk1-clk7 has postponed successively one with respect to system clock clk and has postponed unit, the relative clk of phase place of clk0 does not postpone, specifically as shown in Figure 4, when described delay unit is set, sampling clock clk0, clk2, clk4, clk6 are at corresponding data information (S1, S2, S3, S4 ...) centre position sample, and clk1, clk3, clk5, clk7 are at data message (S1, S2, S3, S4 ...) upturned position samples, thereby can be specifically set the time of delay that postpones unit according to the length of input data information data.As shown in Figures 4 and 5, described sampler is at the different phase time point (clk0 of sampling clock, clk1, clk2, clk3, clk4, clk5, clk6, clk7 ...) data message (M0 that obtains of sampling, M1, M2, M3, M4, M5, M6 ...) in preferred implementation of the present utility model, input three sample information of phase discriminator PHDJDG described in each, sample information (the M0 that first sample information obtains for sampling previous data message centre position, M2, M4, M6 ... in one), second sample information (M1 that sample information is the previous data message of sampling and rear data message upturned position acquisition, M3, M5, M7 ... in one), the 3rd the sample information (M0 that sample information obtains for the rear data message centre position of sampling, M2, M4, M6 ... in one), and this two data message is two adjacent data messages.In addition, inputting the sampling clock that the clock of the first trigger DFF1 and the second trigger DFF2 described in each is sampled data information centre position, for example, is sampling clock (clk0, clk2, clk4, clk6 ...) in two.
Particularly, with reference to figure 5, a specific embodiment of the present utility model is described.Clock clk0 compares system clock clk and has postponed 0 delay unit, and the centre position of clock clk0 sampled data information S1, the information M0 after being sampled; Sampling clock clk1 compares system clock clk and has postponed 1 delay unit, and clock clk1 sampled data information S1 turn to the upturned position of data message S2, the information M1 after being sampled; The rest may be inferred, and sampling clock clkN compares system clock clk and postponed N delay unit, obtains sample information MN; And as shown in Figure 4, when N is even numbers, the centre position of sampling clock clkN sampled data information, when N is odd number, the upturned position of sampling clock clkN sampled data information.Sampler is inputted described phase discriminator PHDJDG by the sample information M0-MN obtaining three continuous phase time point samplings, be specially in Fig. 5, input first group of phase discriminator equipment phase discriminator PHDJDG be sample information M0, M1, M2, and sample information M0 is the sample information that sampled data information S1 centre position obtains, sample information M1 is the sample information that sampled data information S1 and data message S2 upturned position obtain, and sample information M2 is the sample information that sampled data information S2 centre position obtains; Described phase discriminator PHDJDG adjudicates sample information M0, M1, the M2 of input, and by two output up, dn output court verdict, wherein, the court verdict of described phase discriminator PHDJDG is as shown in table 1:
Table 1
The input of two output up of described phase discriminator PHDJDG, dn respectively with the first trigger DFF1 and the second trigger DFF2 is connected, thereby described phase discriminator PHDJDG inputs respectively two triggers by its court verdict; Input the Enable Pin of the first trigger DFF1 and the second trigger DFF2 with the sampling clock clk4 of sampling described data message S1 and S2 out of phase, input the clock control end of the first trigger DFF1 and the second trigger DFF2 with the sampling clock clk6 of sampling described data message S1 and S2 out of phase, thereby when the rising edge of sampling clock clk4 and clk6 arrives, the output up1 of described the first trigger DFF1 and the second trigger DFF2 and dn1 are by the two court verdict outputs of described phase discriminator PHDJDG.Four groups of phase discriminator equipment of described second group of phase discriminator equipment to the all arrange with above-mentioned first group of phase discriminator the processing procedure of the sample information of input, difference is only, the sampling clock of the first trigger DFF1 of described first group of phase demodulation equipment and the input of the clock control end of the second trigger DFF2 is to have postponed 6 system clocks that postpone unit, and the sampling clock of the first trigger DFF1 of described first group of phase demodulation equipment and the input of the Enable Pin of the second trigger DFF2 is to have postponed 4 system clocks that postpone unit; The sampling clock of the first trigger DFF1 of described second group of phase demodulation equipment and the input of the clock control end of the second trigger DFF2 is to have postponed 0 system clock that postpones unit, and the clock of the first trigger DFF1 of described second group of phase demodulation equipment and the input of the Enable Pin of the second trigger DFF2 is to have postponed 6 system clocks that postpone unit; The sampling clock of the first trigger DFF1 of described the 3rd group of phase demodulation equipment and the input of the clock control end of the second trigger DFF2 is to have postponed 2 system clocks that postpone unit, and the sampling clock of the first trigger DFF1 of described the 3rd group of phase demodulation equipment and the input of the Enable Pin of the second trigger DFF2 is to have postponed 0 system clock that postpones unit; The sampling clock of the first trigger DFF1 of described the 4th group of phase demodulation equipment and the input of the clock control end of the second trigger DFF2 is to have postponed 4 system clocks that postpone unit, and the sampling clock of the first trigger DFF1 of described the 4th group of phase demodulation equipment and the input of the clock control end of the second trigger DFF2 is to have postponed 2 system clocks that postpone unit; As shown in Figure 5, do not repeat them here.Described in every group, the output of the first trigger DFF1 of phase discriminator equipment is connected with input described or door OR1, and up1-up4 inputs described or door OR1; Described in every group, the output of the second trigger DFF2 of phase discriminator equipment is connected with input described or door OR2, and dn1-dn4 inputs described or door OR2; Thereby arbitrary sample information all can be exported court verdict by described or door OR1, OR2 by described phase discriminator judgement for lead-lag, to facilitate, carry out subsequent adjustment.
Above combination most preferred embodiment is described the utility model, but the utility model is not limited to the embodiment of above announcement, and should contain the various modifications of carrying out according to essence of the present utility model, equivalent combinations.
Claims (5)
1. a CDR phase discriminator system, comprise sampler, system clock postpones to form sampling clock to its phase place, described sampler is sampled to the data message of input at the different phase time point of sampling clock, it is characterized in that, also comprise at least four group phase demodulation equipment and two or, described in every group, phase demodulation equipment comprises phase discriminator, the first trigger and the second trigger, sampler is inputted phase discriminator described in each by the sample information obtaining in the sampling of three continuous phase time points of sampling clock, described phase discriminator is analyzed the sample information of input, and described in each, phase discriminator has two outputs, the first output of described phase discriminator is connected with the input of described the first trigger, the second output of described phase discriminator is connected with the input of described the second trigger, the different clock of system clock one and the phase place of current sampling clock is inputted respectively the clock control end of described the first trigger and the second trigger, and the different clock of phase place of system clock another and current sampling clock is inputted respectively the Enable Pin of described the first trigger and the second trigger, the output of described first trigger of every group of phase demodulation equipment all with described in one or door input is connected, the output of described second trigger of every group of phase demodulation equipment all with described in another or input be connected.
2. CDR phase discriminator system as claimed in claim 1, is characterized in that, described sampling clock is that system clock postpones 0-N the clock postponing after unit, and the length of each delay unit is input data information length half, and N is positive integer.
3. CDR phase discriminator system as claimed in claim 2, it is characterized in that, input three sample information of phase discriminator described in each, the sample information that first sample information obtains for sampling previous data message centre position, second sample information that sample information is the previous data message of sampling and rear data message upturned position acquisition, the 3rd sample information that sample information obtains for the rear data message centre position of sampling, and this two data message is two adjacent data messages.
4. CDR phase discriminator system as claimed in claim 1, is characterized in that, inputs the sampling clock that the clock of the first trigger and the second trigger described in each is sampled data information centre position.
5. CDR phase discriminator system as claimed in claim 1, it is characterized in that, described phase demodulation equipment is four groups, the sampling clock of the first trigger of described first group of phase demodulation equipment and the input of the clock control end of the second trigger is to have postponed 6 system clocks that postpone unit, and the sampling clock of the first trigger of described first group of phase demodulation equipment and the input of the Enable Pin of the second trigger is to have postponed 4 system clocks that postpone unit; The sampling clock of the first trigger of described second group of phase demodulation equipment and the input of the clock control end of the second trigger is to have postponed 0 system clock that postpones unit, and the clock of the first trigger of described second group of phase demodulation equipment and the input of the Enable Pin of the second trigger is to have postponed 6 system clocks that postpone unit; The sampling clock of the first trigger of described the 3rd group of phase demodulation equipment and the input of the clock control end of the second trigger is to have postponed 2 system clocks that postpone unit, and the sampling clock of the first trigger of described the 3rd group of phase demodulation equipment and the input of the Enable Pin of the second trigger is to have postponed 0 system clock that postpones unit; The sampling clock of the first trigger of described the 4th group of phase demodulation equipment and the input of the clock control end of the second trigger is to have postponed 4 system clocks that postpone unit, and the sampling clock of the first trigger of described the 4th group of phase demodulation equipment and the input of the clock control end of the second trigger is to have postponed 2 system clocks that postpone unit.
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