CN203895510U - Low temperature poly-silicon thin film transistor (TFT), array substrate and display device - Google Patents
Low temperature poly-silicon thin film transistor (TFT), array substrate and display device Download PDFInfo
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- CN203895510U CN203895510U CN201420335254.4U CN201420335254U CN203895510U CN 203895510 U CN203895510 U CN 203895510U CN 201420335254 U CN201420335254 U CN 201420335254U CN 203895510 U CN203895510 U CN 203895510U
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Abstract
The utility model discloses a poly-silicon thin film transistor (TFT), an array substrate and a display device. The low-temperature poly-silicon TFT comprises a substrate, a buffer layer formed on the substrate and an active layer formed on the buffer layer through a composition process. In addition, a thermal insulation heat preservation layer is further formed on the active layer. According to the utility model, the thermal insulation heat preservation layer is designed in a poly-silicon thin film structure, the thermal insulation heat preservation layer and the buffer layer suppress temperature spreading of molten silicon at the upper surface and the lower surface of the active layer respectively, and a role of double-layer heat preservation is played, thereby obviously prolonging the crystallization time of polycrystalline silicon. Meanwhile, the pattern design of the thermal insulation heat preservation layer can enable the active layer to be crystallized at an edge portion of the pattern so as to form poly-silicon seed crystal, thereby guiding growth of the molten silicon, being conducive to growth of large-size crystal grains, and effectively improving the mobility of the TFT.
Description
Technical field
The utility model relates to Display Technique field, relates in particular to a kind of low-temperature polysilicon film transistor and array base palte thereof and display unit.
Background technology
Flourish along with flat-panel screens technology, active matrix type organic luminous display device (Active Matrix Organic Light Emitting Diode, be called for short AMOLED) due to it, there is the good characteristics such as more frivolous, self-luminous and high reaction rate, become the trend of following display development.It can comprise active switch, insulating barrier, transparency electrode, luminescent layer and the metal electrode being formed on successively on substrate, and wherein, active switch is connected with transparency electrode by contact hole, to control writing of view data.At present, the development of maximizing for adapting to AMOLED size, active switch adopts low-temperature polysilicon film transistor (Low Temperature Poly-silicon TFT is called for short LTPS-TFT) as pixel switch control element conventionally; And whether for the electrical performance of LTPS-TFT, have direct impact for the preparation of the quality quality of the low-temperature polysilicon film of LTPS-TFT, therefore, the manufacturing technology of low-temperature polysilicon film also more and more comes into one's own.
In the preparation technology of LTPS-TFT and semiconductor device, the formation of active layer is all generally first to deposit certain thickness amorphous silicon layer, then adopts special process to make amorphous silicon crystallization form polysilicon, to improve the mobility of charge carrier in active layer.The main technique that amorphous silicon crystallization technology adopts is at present Excimer-Laser Crystallization (ELA).
In ELA technique, its crystallization method is to adopt the high-octane Ear Mucosa Treated by He Ne Laser Irradiation of certain wavelength in amorphous silicon membrane surface, after irradiating, the temperature of silicon film surface rises to rapidly 1400 ℃ of left and right, now amorphous silicon is molten condition, after laser energy is withdrawn, substrate is cooling rapidly, and in cooling procedure, amorphous silicon crystallization forms polysilicon.In this process, the cooling rate of substrate is too fast, and crystal grain does not have time enough growth, causes crystallite dimension less, and carrier mobility is lower, and the reaction speed of TFT and semiconductor device is slow and power consumption is high, the product competitiveness problem such as cannot get a promotion.
Utility model content
(1) technical problem that will solve
The technical problems to be solved in the utility model is how to overcome in the process of amorphous silicon crystallization formation polysilicon, the cooling rate of substrate is too fast, crystal grain does not have time enough growth, cause crystallite dimension less, carrier mobility is lower, the reaction speed of TFT and semiconductor device is slow and power consumption is high, the product competitiveness problem such as cannot get a promotion.
(2) technical scheme
For solving the problems of the technologies described above, the utility model provides a kind of low-temperature polysilicon film transistor, described low-temperature polysilicon film transistor comprises substrate, the resilient coating forming on substrate, and the active layer forming on resilient coating by composition technique, in addition, on described active layer, be also formed with thermal insulating warm-keeping layer.
Wherein, the not insulated heat-insulation layer in the edge of described active layer covers.The border width of the described active layer that preferably, not insulated heat-insulation layer covers is to be not more than 1/4 of active layer width.
Wherein, described thermal insulating warm-keeping layer forms by spraying coating process, and its thickness range is
wherein, described thermal insulating warm-keeping layer is prepared from by high temperature resistant resistance to compression, conductive coefficient material low, that adhesiveness is good, at high temperature to active layer, can not produce harmful effect.
Particularly, the material of described thermal insulating warm-keeping layer comprises silicon nitride and silica (preferably but be not limited to silicon nitride, silica).
Further, low-temperature polysilicon film transistor described in the utility model is also included in gate insulation layer, gate electrode, interlayer insulating film and source electrode and the drain electrode that the top of described thermal insulating warm-keeping layer forms successively, and described source electrode and drain electrode are respectively by running through the via hole of interlayer insulating film, gate insulation layer and thermal insulating warm-keeping layer and the two ends of described active layer are connected.
The utility model further provides a kind of array base palte, comprises above-mentioned low-temperature polysilicon film transistor.
The utility model also provides the display unit that contains above-mentioned array base palte.
(3) beneficial effect
The utility model for the structural design of LTPS-TFT or semiconductor device thermal insulating warm-keeping layer, to slow down the cooldown rate of substrate in ELA process, increase the crystallite dimension of polysilicon, improve the electric property of TFT.
Particularly, the utility model is at the upper surface of active layer, to be formed with the thermal insulating warm-keeping layer of pattern (Pattern), the diffusion of temperature in the upper surface of active layer and lower surface suppress molten silicon respectively of this thermal insulating warm-keeping layer and resilient coating, play the effect of double-layer heat insulation, thereby obviously extend the time of polysilicon crystallization.Meanwhile, the design of thermal insulating warm-keeping layer can make active layer form polysilicon seed crystal in the first crystallization of pattern edge part, and the growth of guiding molten silicon, contributes to the growth of large scale crystal grain, effectively raises the mobility of TFT.
Accompanying drawing explanation
Fig. 1 is the process chart that the utility model polycrystalline SiTFT forms;
Fig. 2 is the utility model TFT structural representation;
Reference numeral: 1 is substrate; 2 is resilient coating; 3 is active layer; 4 is thermal insulating warm-keeping layer; 5 is gate insulation layer; 6 is insulating barrier; 7 is gate electrode; 8 is source electrode; 9 is drain electrode, and 10 is photoresist.
Embodiment
For clearer description this programme, below in conjunction with specific embodiment, technical solutions of the utility model are elaborated.Obviously, described embodiment is a part of embodiment of the present utility model, rather than whole embodiment.Based on described embodiment of the present utility model, the every other embodiment that those of ordinary skills obtain under the prerequisite without creative work, belongs to the scope that the utility model is protected.
Embodiment 1
The present embodiment discloses a kind of low-temperature polysilicon film transistor, as shown in Figure 2, this low-temperature polysilicon film transistor, be included in substrate 1, and on substrate 1 resilient coating 2, active layer 3 and the thermal insulating warm-keeping layer 4 forming successively, wherein, by forming active layer 3 by composition technique on the amorphous silicon layer of low-temperature polysilicon film transistor in embodiment 1, active layer 3 is no more than insulated heat-insulation layer 4 coverings in edge of its width 1/4 simultaneously.
Simultaneously, described in the present embodiment, low-temperature polysilicon film transistor is also included in gate insulation layer 5, gate electrode 7, interlayer insulating film 6 and source electrode 8 and the drain electrode 9 that the top of thermal insulating warm-keeping layer 4 forms successively, wherein, source electrode 8 is connected with the two ends of active layer 3 by running through the insulation via hole of interlayer insulating film 6, gate insulation layer 5 and thermal insulating warm-keeping layer 4 respectively with drain electrode 9.
In the present embodiment, on active layer 3, deposit the thermal insulating warm-keeping layer 4 that one deck is very thin, after forming specific pattern, carry out ELA technique, the effect of ELA is by recrystallization after active layer melting, form polysilicon, in technique, the temperature propagation degree of depth of ELA can reach 100nm at present, and the thickness of active layer 3 is generally no more than 50nm, so increase very thin thermal insulating warm-keeping layer 4 on active layer 3, can not have impact to the melting recrystallization of ELA technique and active layer 3.
Wherein, the material of thermal insulating warm-keeping layer 4 must at least meet following basic condition: conductive coefficient should be the smaller the better, compression strength is high, good heat resistance, and adhesiveness is good, normal temperature stability inferior high, at high temperature to active layer, can not produce harmful effect, and must in TFT technique, easily prepare, as the oxide of silicon (SiOx), silicon nitrides (SiNx) etc., the disclosed multiple material that meets above-mentioned condition of prior art can be as desirable heat-insulating material.
The present embodiment preferred nitrogen SiClx or silica material, more preferably silica.The thickness range of thermal insulating warm-keeping layer is
the formed thermal insulating warm-keeping layer of this type of material can meet design and material requirements, under corresponding technique, forms macromeritic polysilicon.
Wherein, substrate 1 can be selected the multiple substrate that polysilicon membrane forms that can be used for, and as glass substrate, quartz base plate etc., its thickness adopts stock size.
The present embodiment is the Double insulating effect with resilient coating 2 by thermal insulating warm-keeping layer 4, in the environment of substrate 1 downwards of the temperature that can suppress molten silicon in active layer 3 and top, spreads, and has extended the crystallization time of polysilicon; Simultaneously, in the present embodiment, the pattern width of thermal insulating warm-keeping layer 4 is slightly less than the pattern width of active layer 3, in crystallization process, the cooldown rate of insulated heat-insulation layer 4 cover parts can be not very fast for active layer 3 pattern edges, and first crystallization forms polysilicon, and as seed crystal, the growth of the insulated heat-insulation layer 4 cover part crystal grain of guiding, which more contributes to the growth of large scale crystal grain, has improved the mobility of TFT.
Embodiment 2
The present embodiment provides a kind of method for the preparation of low-temperature polysilicon film transistor, specifically comprises:
The 1st step a: substrate 1 is provided, forms resilient coating 2 on substrate 1; On resilient coating 2, form active layer 3; At active layer 3, form thermal insulating warm-keeping layer 4.
Wherein, the process chart of the concrete formation of active layer 3 is shown in Fig. 1:
(1) on substrate 1, deposit successively resilient coating 2, active layer 3 and thermal insulating warm-keeping layer 4, obtain initial configuration;
(2) on thermal insulating warm-keeping layer 4, form photoresist 10;
(3) through overexposure, etching technics, form the preliminary pattern of active layer 3 patterns and thermal insulating warm-keeping layer 4;
(4) through cineration technics, remove the photoresist of thermal insulating warm-keeping layer 4 marginal portions;
(5) through over etching and stripping technology, form thermal insulating warm-keeping layer 4 patterns;
(6) through crystallization process, the amorphous silicon crystallization of active layer 3 is formed to polysilicon (active layer 3 after crystallization see in Fig. 1 final structure shown in shade layer structure).Wherein, crystallization process refers to and adopts ELA technique to make amorphous silicon layer surface temperature moment reach 1400 ℃, and amorphous silicon is melting at high temperature, after Ear Mucosa Treated by He Ne Laser Irradiation finishes, and along with temperature reduces, the amorphous silicon layer generation recrystallization of melting, thus form polysilicon.
Particularly, this step is selected if glass substrate is as substrate 1, and substrate 1 is carried out to prerinse, utilizes plasma enhanced chemical vapor deposition method deposition resilient coating 2, rear deposition active layer 3, and at active layer 3 surface deposition thermal insulating warm-keeping layers 4.Wherein, resilient coating 2 can be continued to use existing structure, as the double-decker by silicon nitride layer and silicon dioxide layer, lower floor is that thickness is the silicon nitride layer of 50-150nm, upper strata is that thickness is the silicon dioxide layer of 100-350nm, the active layer 3 that is 300-600nm for thickness above of silicon dioxide layer, thermal insulating warm-keeping layer 4 thickness are
employing silicon nitride material is prepared from.
The 2nd step: deposit successively gate insulation layer 5, gate electrode 7, interlayer dielectric layer 6 and source electrode 8 and drain electrode 9 on thermal insulating warm-keeping layer 4, form the basic structure of TFT and semiconductor device.
Be specially: above thermal insulating warm-keeping layer 4, deposit gate insulation layer 5; Above gate insulation layer 5, form grid metallic film, by composition technique, form the pattern of gate electrode 7, and doping treatment is carried out to form ion doped region in the region at described active layer 3 two ends; Above gate electrode 7, form interlayer insulating film 6, and form and run through the insulating barrier via hole of described thermal insulating warm-keeping layer 4, gate insulation layer 5 and interlayer insulating film 6 by composition technique, thereby expose the ion doped region at described active layer 3 two ends; Above interlayer insulating film 6, metallic film is leaked in formation source, and forms source electrode 8 and drain electrode 9 by composition technique, and source electrode 8 is connected with the ion doped region at active layer 3 two ends by described insulating barrier via hole respectively with drain electrode 9.
The present embodiment is by having increased thermal insulating warm-keeping layer 4 at active layer upper surface, can be in crystallization process after high-octane laser be withdrawn, jointly active layer is incubated with resilient coating 2, greatly reduce the cooling rate of amorphous silicon layer, make crystal grain after formation, have time enough growth, increase crystallite dimension (about crystal grain average grain diameter 2um), can prepare the thin-film transistor (structure is shown in Fig. 2) described in embodiment 1.
Embodiment 3
The present embodiment provides a kind of array base palte, this array base palte comprises the low-temperature polysilicon film transistor described in embodiment 1, when the array base palte forming is thus used for display backplane, can improve reaction speed, reduce power consumption etc., be applicable to the fields such as active matrix organic light emitting diode display (AMOLED), low-temperature polysilicon film transistor liquid crystal display (LTPS TFT-LCD).
Embodiment 4
The present embodiment provides a kind of display unit, and this display unit comprises the array base palte described in embodiment 3.The display unit of the present embodiment, can be active matrix organic light emitting diode display (AMOLED) or liquid crystal display etc., owing to having adopted low-temperature polysilicon film transistor in this display unit, aspect electric property, compared with amorphous silicon, be greatly improved, can improve the competitiveness of this display unit.
By above embodiment, can find out, the utility model is by increasing thermal insulating warm-keeping layer on active layer surface, in employing ELA mode, carry out in the crystallization process of active layer, after high-octane laser is withdrawn, thermal insulating warm-keeping layer and resilient coating can be incubated silicon thin film jointly, greatly reduce its cooldown rate, make crystal grain after formation, have time enough growth, increased crystallite dimension, improved carrier mobility, the reaction rate that has improved TFT and semiconductor device, has reduced power consumption, has promoted the competitiveness of product.The method that the utility model adopts, easily operation in process of production, technical process succinctly and not expends raw material; By increasing the size of polysilicon grain, finally can access the good low-temperature polysilicon film transistor of mobility; The low-temperature polysilicon film that this technique obtains can be used as the active layer of low-temperature polysilicon film transistor, is applicable to the fields such as active matrix organic light emitting diode display (AMOLED) and low-temperature polysilicon film transistor liquid crystal display (LTPS TFT-LCD).
In addition; embodiment in above-described embodiment can further combine or replace; and embodiment is described preferred embodiment of the present utility model; not design of the present utility model and scope are limited; do not departing under the prerequisite of the utility model design philosophy; the various changes and modifications that in this area, professional and technical personnel makes the technical solution of the utility model, all belong to protection range of the present utility model.
Claims (8)
1. a low-temperature polysilicon film transistor, comprises the resilient coating and the active layer that on substrate, form successively, it is characterized in that: be also included in the thermal insulating warm-keeping layer forming on described active layer.
2. low-temperature polysilicon film transistor according to claim 1, is characterized in that: the not insulated heat-insulation layer in the edge of described active layer covers.
3. low-temperature polysilicon film transistor according to claim 2, is characterized in that: the border width of the described active layer that not insulated heat-insulation layer covers is to be not more than 1/4 of active layer width.
4. low-temperature polysilicon film transistor according to claim 1, is characterized in that: the thickness of described thermal insulating warm-keeping layer is
5. low-temperature polysilicon film transistor according to claim 1, is characterized in that: the material of described thermal insulating warm-keeping layer comprises silicon nitride or silica.
6. according to the low-temperature polysilicon film transistor described in claim 1-5 any one, it is characterized in that: be also included in gate insulation layer, gate electrode, interlayer insulating film that the top of described thermal insulating warm-keeping layer forms successively, and source electrode and drain electrode, described source electrode and drain electrode are respectively by running through the via hole of interlayer insulating film, gate insulation layer and thermal insulating warm-keeping layer and the two ends of described active layer are connected.
7. an array base palte, is characterized in that, comprises the low-temperature polysilicon film transistor described in claim 1-6 any one.
8. a display unit, is characterized in that: comprise array base palte claimed in claim 7.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104078621A (en) * | 2014-06-20 | 2014-10-01 | 京东方科技集团股份有限公司 | Low-temperature polycrystalline silicon thin film transistor, manufacturing method thereof, array substrate and display device |
| WO2017107274A1 (en) * | 2015-12-21 | 2017-06-29 | 武汉华星光电技术有限公司 | Low-temperature polysilicon thin film transistor and preparation method therefor |
| WO2020186448A1 (en) * | 2019-03-19 | 2020-09-24 | 深圳市柔宇科技有限公司 | Transparent display panel and display device |
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2014
- 2014-06-20 CN CN201420335254.4U patent/CN203895510U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104078621A (en) * | 2014-06-20 | 2014-10-01 | 京东方科技集团股份有限公司 | Low-temperature polycrystalline silicon thin film transistor, manufacturing method thereof, array substrate and display device |
| WO2015192558A1 (en) * | 2014-06-20 | 2015-12-23 | 京东方科技集团股份有限公司 | Low-temperature polysilicon thin film transistor and manufacturing method thereof, array substrate and display device |
| WO2017107274A1 (en) * | 2015-12-21 | 2017-06-29 | 武汉华星光电技术有限公司 | Low-temperature polysilicon thin film transistor and preparation method therefor |
| US10192975B2 (en) | 2015-12-21 | 2019-01-29 | Wuhan China Star Optoelectronics Technology Co., Ltd | Low temperature polycrystalline silicon thin film transistor |
| WO2020186448A1 (en) * | 2019-03-19 | 2020-09-24 | 深圳市柔宇科技有限公司 | Transparent display panel and display device |
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