CN203838706U - Computer mainframe and peripheral switching sequence control device - Google Patents

Computer mainframe and peripheral switching sequence control device Download PDF

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Publication number
CN203838706U
CN203838706U CN201420244858.8U CN201420244858U CN203838706U CN 203838706 U CN203838706 U CN 203838706U CN 201420244858 U CN201420244858 U CN 201420244858U CN 203838706 U CN203838706 U CN 203838706U
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CN
China
Prior art keywords
gate
connects
resistance
full bridge
delay time
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201420244858.8U
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Chinese (zh)
Inventor
于延
张明宇
王金江
肖鑫
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Harbin Normal University
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Harbin Normal University
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Priority to CN201420244858.8U priority Critical patent/CN203838706U/en
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Publication of CN203838706U publication Critical patent/CN203838706U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Abstract

The utility model belongs to the field of computers and discloses a computer mainframe and peripheral switching sequence control device. The computer mainframe and peripheral switching sequence control device aims to solve the problem that the switching sequence of a computer mainframe and a peripheral is not reliable under manual control. The computer mainframe and peripheral switching sequence control device comprises a switch S, a full bridge rectifying circuit UR, a diode VD, a capacitor C1, a resistor R1, a resistor R2, a resistor R3, a NOT gate D1, a NOT gate D2, an electricity delay time relay K1 and a bidirectional thyristor VTH, wherein the diode VD and the capacitor C1 form a time-delay circuit; the resistor R1, the resistor R2, the resistor R3, the NOT gate D1 and the NOT gate D2 form a Schmitt trigger; a 220V alternating current power source outputs a direct current power source to be a working power source via the full bridge rectifying circuit UR; the switch S is switched on, the Schmitt trigger triggers the bidirectional thyristor VTH, and the peripheral is electrified firstly; the electricity delay time relay K1 is electrified, and the mainframe is electrified after being delayed; the switch S is switched off, the electricity delay time relay K1 loses power, the mainframe is turned off instantaneously, the capacitor C1 discharges electricity, the Schmitt trigger delays and turns over to be of a low level, the bidirectional thyristor VTH delays to lose trigger voltage, and the then the peripheral is turned off.

Description

Main frame and peripheral hardware switching sequence control device
Technical field
The utility model relates to main frame and peripheral hardware switching sequence control device, belongs to computer realm.
Background technology
The main frame of computing machine and the start of peripheral hardware, shutdown order has strict demand, in the time of start, establish over first, after drive main frame; In the time of shutdown, first close main frame, rear pass peripheral hardware.Peripheral hardware comprises the equipment such as display, printer.If order is got wrong, the dash current the lighter who produces when open and close machine causes loss of data, and severe one can cause damaging main frame.And people may not necessarily strictly observe these rules at ordinary times, cause computing machine to suffer damage.
Summary of the invention
The utility model object is sequentially unreliable by manual control in order to solve main frame and peripheral hardware switching on and shutting down, and the problem that can cause computing machine to suffer damage, provides a kind of main frame and peripheral hardware switching sequence control device.
Main frame described in the utility model and peripheral hardware switching sequence control device, it comprises switch S, full bridge rectifier UR, diode VD, resistance R 1, resistance R 2, resistance R 3, capacitor C 1, not gate D1, not gate D2, on-delay time relay K1 and bidirectional thyristor VTH;
One end of 220V AC power connects power supply terminal of a power supply terminal, peripheral hardware and one end of switch S of main frame simultaneously, and the other end of switch S connects an ac input end of full bridge rectifier UR;
Another power supply terminal of main frame connects one end of on-delay time relay K1 time delay normally opened contact; Another power supply terminal of peripheral hardware connects a central electrode of bidirectional thyristor VTH;
The other end of 220V AC power connects the other end, another central electrode of bidirectional thyristor VTH and another ac input end of full bridge rectifier UR of on-delay time relay K1 time delay normally opened contact simultaneously;
The cathode power supply output terminal of full bridge rectifier UR connects one end of anode and the on-delay time relay K1 coil of diode VD simultaneously; The other end of on-delay time relay K1 coil connects one end of capacitor C 1 and the negative power supply output terminal of full bridge rectifier UR simultaneously;
The negative electrode of diode VD connects the other end of capacitor C 1 and one end of resistance R 1 simultaneously, one end of the other end while contact resistance R2 of resistance R 1 and the input end of not gate D1, the output terminal of not gate D1 connects the input end of not gate D2, the other end of the output terminal while contact resistance R2 of not gate D2 and one end of resistance R 3; The other end of resistance R 3 connects the control utmost point of bidirectional thyristor VTH.
Advantage of the present utility model: main frame described in the utility model and peripheral hardware switching sequence control device are simple in structure, while easily realizing start, establishes over first, after drive main frame; When shutdown, first close main frame, the order of rear pass peripheral hardware, the effectively safety of protected host.
Brief description of the drawings
Fig. 1 is the structural representation of main frame described in the utility model and peripheral hardware switching sequence control device.
Embodiment
Embodiment one: present embodiment is described below in conjunction with Fig. 1, main frame and peripheral hardware switching sequence control device described in present embodiment, it comprises switch S, full bridge rectifier UR, diode VD, resistance R 1, resistance R 2, resistance R 3, capacitor C 1, not gate D1, not gate D2, on-delay time relay K1 and bidirectional thyristor VTH;
One end of 220V AC power connects power supply terminal of a power supply terminal, peripheral hardware and one end of switch S of main frame simultaneously, and the other end of switch S connects an ac input end of full bridge rectifier UR;
Another power supply terminal of main frame connects one end of on-delay time relay K1 time delay normally opened contact; Another power supply terminal of peripheral hardware connects a central electrode of bidirectional thyristor VTH;
The other end of 220V AC power connects the other end, another central electrode of bidirectional thyristor VTH and another ac input end of full bridge rectifier UR of on-delay time relay K1 time delay normally opened contact simultaneously;
The cathode power supply output terminal of full bridge rectifier UR connects one end of anode and the on-delay time relay K1 coil of diode VD simultaneously; The other end of on-delay time relay K1 coil connects one end of capacitor C 1 and the negative power supply output terminal of full bridge rectifier UR simultaneously;
The negative electrode of diode VD connects the other end of capacitor C 1 and one end of resistance R 1 simultaneously, one end of the other end while contact resistance R2 of resistance R 1 and the input end of not gate D1, the output terminal of not gate D1 connects the input end of not gate D2, the other end of the output terminal while contact resistance R2 of not gate D2 and one end of resistance R 3; The other end of resistance R 3 connects the control utmost point of bidirectional thyristor VTH.
Full bridge rectifier UR is the full bridge rectifier being made up of four diodes.Full bridge rectifier UR exports direct current, and direct supply VDD provides working power for subsequent conditioning circuit.
Resistance R 1, resistance R 2, resistance R 3, not gate D1 and not gate D2 form Schmidt trigger, are that A point voltage carries out Shape correction to the upper voltage of C1, become the trigger voltage that edge is precipitous, for triggering bidirectional thyristor VTH.
The principle of work of the on-delay time relay: the on-delay time relay has time delay normally opened contact, time delay normally closed contact; Coil obtains electric, its time delay normally opened contact time closing, and its time delay normally closed contact time delay disconnects; When coil losing electricity, the instantaneous closure of time delay normally opened contact of its closure state, the instantaneous closure of time delay normally closed contact of its off-state.
Principle of work:
When start, Closing Switch S, direct supply VDD is full of electricity for capacitor C 1 rapidly by diode VD, in capacitor C 1, A point voltage, after Schmidt trigger Shape correction, triggers bidirectional thyristor VTH conducting through resistance R 3, peripheral hardware immediately electric.In this process, it is worth emphasizing that, capacitor C 1 charging rate is very fast, because it is undertaken by diode VD, instead of pass through resistance, resistance when diode VD forward conduction is similar to zero, and electric current is almost unimpeded to charge for capacitor C 1, therefore, charging rate is very fast, and the duration of charging is negligible.
While pressing switch S closure, on-delay time relay K1 coil obtains electric, and its time delay normally opened contact time closing obtains electric after main frame.While having realized start, establish over first, after drive main frame sequential control.
When shutdown, cut-off switch S, on-delay time relay K1 coil losing electricity, the instantaneous disconnection of time delay normally opened contact of its closure state, the first power-off of main frame.
When cut-off switch S, because the electric capacity at capacitor C 1 two ends can not suddenly change, the upper A point voltage of C1 is still high level 1, and start slowly to discharge through resistance R 1 and not gate D1 input end, before on C1, A point voltage is down to the negative sense threshold value of Schmidt trigger, Schmidt trigger output voltage is still 1, and bidirectional thyristor VTH continues to keep conducting state because trigger voltage exists, and peripheral hardware still has electricity; The carrying out of discharging along with capacitor C 1, the upper A point voltage of C1 constantly reduces, until the upper A point voltage of C1 is down to the negative sense threshold value of Schmidt trigger, the upset of Schmidt trigger output voltage is 0, bidirectional thyristor VTH ends because losing trigger voltage, and peripheral hardware power-off, while having realized shutdown, first close main frame, the sequential control of rear pass peripheral hardware.Peripheral hardware is delayed the time of main frame power-off by deciding the discharge time of capacitor C 1, and the size that changes capacitor C 1 just can change delay time.

Claims (2)

1. main frame and peripheral hardware switching sequence control device, it is characterized in that, it comprises switch S, full bridge rectifier UR, diode VD, resistance R 1, resistance R 2, resistance R 3, capacitor C 1, not gate D1, not gate D2, on-delay time relay K1 and bidirectional thyristor VTH;
One end of 220V AC power connects power supply terminal of a power supply terminal, peripheral hardware and one end of switch S of main frame simultaneously, and the other end of switch S connects an ac input end of full bridge rectifier UR;
Another power supply terminal of main frame connects one end of on-delay time relay K1 time delay normally opened contact; Another power supply terminal of peripheral hardware connects a central electrode of bidirectional thyristor VTH;
The other end of 220V AC power connects the other end, another central electrode of bidirectional thyristor VTH and another ac input end of full bridge rectifier UR of on-delay time relay K1 time delay normally opened contact simultaneously;
The cathode power supply output terminal of full bridge rectifier UR connects one end of anode and the on-delay time relay K1 coil of diode VD simultaneously; The other end of on-delay time relay K1 coil connects one end of capacitor C 1 and the negative power supply output terminal of full bridge rectifier UR simultaneously;
The negative electrode of diode VD connects the other end of capacitor C 1 and one end of resistance R 1 simultaneously, one end of the other end while contact resistance R2 of resistance R 1 and the input end of not gate D1, the output terminal of not gate D1 connects the input end of not gate D2, the other end of the output terminal while contact resistance R2 of not gate D2 and one end of resistance R 3; The other end of resistance R 3 connects the control utmost point of bidirectional thyristor VTH.
2. main frame and peripheral hardware switching sequence control device according to claim 1, is characterized in that, full bridge rectifier UR is the full bridge rectifier being made up of four diodes.
CN201420244858.8U 2014-05-14 2014-05-14 Computer mainframe and peripheral switching sequence control device Expired - Fee Related CN203838706U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201420244858.8U CN203838706U (en) 2014-05-14 2014-05-14 Computer mainframe and peripheral switching sequence control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201420244858.8U CN203838706U (en) 2014-05-14 2014-05-14 Computer mainframe and peripheral switching sequence control device

Publications (1)

Publication Number Publication Date
CN203838706U true CN203838706U (en) 2014-09-17

Family

ID=51516521

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201420244858.8U Expired - Fee Related CN203838706U (en) 2014-05-14 2014-05-14 Computer mainframe and peripheral switching sequence control device

Country Status (1)

Country Link
CN (1) CN203838706U (en)

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C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140917

Termination date: 20150514

EXPY Termination of patent right or utility model