CN203786492U - HART communication hardware circuit device - Google Patents
HART communication hardware circuit device Download PDFInfo
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- CN203786492U CN203786492U CN201320794946.0U CN201320794946U CN203786492U CN 203786492 U CN203786492 U CN 203786492U CN 201320794946 U CN201320794946 U CN 201320794946U CN 203786492 U CN203786492 U CN 203786492U
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- hart
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- buffer circuit
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Abstract
The utility model discloses a HART communication hardware circuit device and a method for using the device to perform HART. The circuit device comprises a microprocessor, a HART modulation-demodulation circuit, a HART communication switchover isolating circuit, and a multi-path of switchover isolating circuit. The microprocessor receives channel selection instructions sent from hardware configuration and device management software, and chooses one path of the HART devices through controlling the multi-path of switchover isolating circuit, so as to realize point-to-point device parameter setting among the HART devices and other HART communication. Thus, the plurality of HART devices share the common HART modulation-demodulation circuit. Compared with the conventional point-to-point communication method, cost of using the HART modulation-demodulation circuit is reduced, so cost of the device is reduced. Compared with a conventional one-to-many all-digital communication method, the device enables analog communication and digital communication at the same time, and the plurality of channels do not influence each other, so interference is low and failure rate is low.
Description
Technical field
The present invention relates to HART communication technique field, especially relate to a kind of HART Communication hardware circuit device.
Background technology
HART is the abbreviation of highway addressable remote sensor bus.HART agreement is the frequency shift keying digital signal that superposeed in 4～20mA simulating signal.Therefore, analog communication and digital communication can be carried out simultaneously, and digital communication can interference simulation communication, is a kind of for the communication protocol between field intelligent instrument and pulpit equipment.
HART agreement is the transitional technology occurring from analogue instrument to field bus system transition process, has over a period to come certain vitality.At present, HART product under the contract is widely used in automation control area.Because HART communication protocol is retaining on the basis of traditional 4～20mA current signal, expanded the ability of bi-directional digital communication, this agreement makes existing analogue instrument under improved situation, can progressively realizing digitizing, thereby greatly reduces costs, and enhances competitiveness.But at present HART equipment, must point-to-point communication when analog communication and digital communication are carried out, and is furnished with a HART communication device for each HART equipment simultaneously, cost is high like this, and profit is low, very uneconomical; And existing other can be realized the digital communication modes of one-to-many, so communication modes is complicated, and between its multiplexer channel, interference is large, and failure rate is high.
Summary of the invention
In order to address the above problem, realize multichannel HART point-to-point communication, and can reduce costs, guarantee that reliability is high, the advantage of failure rate is low simultaneously, the technical solution adopted in the utility model is as follows:
A HART Communication hardware circuit device, comprises that buffer circuit is switched in microprocessor, HART modulation-demodulation circuit, HART communication and multichannel is switched buffer circuit, wherein:
Described microprocessor is for sending channel selecting instruction and the HART command information of receiving from external management terminal, and a HART device responds information receiving returns to external management terminal; Described HART modulation-demodulation circuit is for modulating the data that send from described microprocessor or the data of switching buffer circuit transmission from described HART communication being carried out to demodulation; Described HART communication switch buffer circuit for data transmission that described HART modulation-demodulation circuit is sent to corresponding HART equipment and the data of HART device responds are returned to described HART modulation-demodulation circuit; Described multichannel switching buffer circuit is used to HART modulation-demodulation circuit and n road HART equipment to carry out data transmission provides line channel;
Described microprocessor switches buffer circuit by HART modulation-demodulation circuit and HART communication and is connected, described HART communication is switched buffer circuit and is connected with multichannel switching buffer circuit, described multichannel is switched buffer circuit and is connected with n road HART device signal output terminal respectively, and the control signal input end that buffer circuit and multichannel switching buffer circuit are switched in described HART modulation-demodulation circuit, HART communication is connected with the I/O end of microprocessor respectively.
Further, described n is 16, described multichannel is switched buffer circuit and is comprised that multichannel is switched buffer circuit one and multichannel is switched buffer circuit two, described multichannel is switched the HART device signal output terminal that buffer circuit one connects respectively 1 ~ 8 tunnel, multichannel is switched the HART device signal output terminal that buffer circuit two connects respectively 9 ~ 16 tunnels, the control signal input end that the control signal input end of described multichannel switching buffer circuit one and multichannel are switched buffer circuit two is connected respectively the I/O end of microprocessor, described multichannel is switched buffer circuit one and is connected with HART communication switching buffer circuit with multichannel switching buffer circuit two.
Further, described HART Communication hardware circuit device also comprises data acquisition circuit and channel switch, described multichannel is switched buffer circuit and by channel switch, is connected with n road HART device signal output terminal respectively, described data acquisition circuit is connected with microprocessor, the data input pin of described data acquisition circuit is connected with n road HART device signal output terminal by channel switch respectively, and the I/O end of described data acquisition circuit is connected with the Enable Pin of channel switch respectively.
Further, described n is 16, described multichannel is switched buffer circuit and is comprised that multichannel is switched buffer circuit one and multichannel is switched buffer circuit two, described multichannel is switched buffer circuit one and by channel switch, is connected respectively the HART device signal output terminal on 1 ~ 8 tunnel, multichannel is switched buffer circuit two and by channel switch, is connected respectively the HART device signal output terminal on 9 ~ 16 tunnels, the control signal input end that the control signal input end of described multichannel switching buffer circuit one and multichannel are switched buffer circuit two is connected respectively the I/O end of microprocessor, described multichannel is switched buffer circuit one and is connected with HART communication switching buffer circuit with multichannel switching buffer circuit two.
Further, described data acquisition circuit comprises 16 circuit-switched data Acquisition Circuit, 8 circuit-switched data Acquisition Circuit one and 8 circuit-switched data Acquisition Circuit two, described 8 circuit-switched data Acquisition Circuit one connect respectively the HART device signal output terminal on 1 ~ 8 tunnel by channel switch, described 8 circuit-switched data Acquisition Circuit two connect respectively the HART device signal output terminal on 9 ~ 16 tunnels by channel switch, described 8 circuit-switched data Acquisition Circuit one are connected with microprocessor by 16 circuit-switched data Acquisition Circuit respectively with 8 circuit-switched data Acquisition Circuit two, the I/O end of described 8 circuit-switched data Acquisition Circuit one is connected with the channel switch Enable Pin on 1 ~ 8 tunnel respectively, the I/O end of described 8 circuit-switched data Acquisition Circuit two is connected with the channel switch Enable Pin on 9 ~ 16 tunnels respectively.
The present invention's beneficial effect compared with prior art:
1, by microprocessor, control multichannel switching buffer circuit and select a wherein road HART equipment, realizing main frame the HART such as arranges and communicates by letter with point-to-point device parameter between HART equipment, make the HART modulation-demodulation circuit of multichannel HART equipment sharing of common, compare with traditional point-to-point communication mode, reduced the cost that uses HART modulation-demodulation circuit, made the cost of this device.
2, failure rate is low.Between the multiplexer channel of this device, be independent of each other, interference is little, compares with the digital communication modes of traditional one-to-many, and failure rate is low, can realize analog communication and digital communication simultaneously.
3, in this device, use HART communication to switch buffer circuit and multichannel switching buffer circuit, realize the feature of isolation completely, reliability is high, is independent of each other between multiplexer channel simultaneously, and interference is little.
4, in this device, by microprocessor control channel switch and multichannel, switch buffer circuit and realize the switching between traditional sampling process and HART communication process, improved the versatility of system.
Accompanying drawing explanation
Fig. 1 is the principle schematic of a kind of HART Communication hardware circuit of the present invention device embodiment mono-.
Fig. 2 is the principle schematic of a kind of HART Communication hardware circuit of the present invention device embodiment bis-.
Fig. 3 is the principle schematic of a kind of HART Communication hardware circuit of the present invention device embodiment tri-.
Fig. 4 is the principle schematic of a kind of HART Communication hardware circuit of the present invention device embodiment tetra-.
Embodiment
A kind of HART Communication hardware circuit device, as shown in Figure 1, comprise microprocessor 1, HART modulation-demodulation circuit 2, buffer circuit 3 is switched in HART communication and multichannel is switched buffer circuit 4, described microprocessor 1 switches buffer circuit 3 by HART modulation-demodulation circuit 2 and HART communication and is connected, I/O end and the HART modulation-demodulation circuit 2 of microprocessor 1, HART communication is switched buffer circuit 3 and is connected with the control signal input end of multichannel switching buffer circuit 4, for sendaisle selection instruction and HART command information, and the HART device responds information receiving is returned to external management terminal.Described HART modulation-demodulation circuit 2, for according to the direction control signal of the microprocessor 1 of receiving, is modulated the data that send from described microprocessor 1 or the data of switching buffer circuit 3 transmissions from described HART communication is carried out to demodulation.Described HART communication is switched buffer circuit 3 and is connected with multichannel switching buffer circuit 4, simultaneously, described multichannel is switched buffer circuit 4 and is connected with n road HART device signal output terminal respectively, and wherein port number n can be according to the needs of actual HART device talk and actual set.HART communication switch buffer circuit 3 for data transmission that described HART modulation-demodulation circuit 2 is sent to corresponding HART equipment and the data of HART device responds are returned to described HART modulation-demodulation circuit 2.Described multichannel switching buffer circuit 4 is used to HART modulation-demodulation circuit 3 and n road HART equipment to carry out data transmission provides line channel.
Fig. 2 is another embodiment of a kind of HART Communication hardware circuit of the present invention device, in itself and Fig. 1, the difference of embodiment is, port number n is 16, multichannel is switched buffer circuit 4 and is divided into multichannel switching buffer circuit 1 and multichannel switching buffer circuit 2 42, described multichannel is switched the HART device signal output terminal that buffer circuit one connects respectively 1 ~ 8 tunnel, multichannel is switched the HART device signal output terminal that buffer circuit two connects respectively 9 ~ 16 tunnels, the control signal input end that the control signal input end of described multichannel switching buffer circuit one and multichannel are switched buffer circuit two is connected respectively the I/O end of microprocessor, described multichannel is switched buffer circuit one and is connected with HART communication switching buffer circuit with multichannel switching buffer circuit two.
Fig. 3 is the 3rd embodiment of a kind of HART Communication hardware circuit of the present invention device, data acquisition circuit 5 and the channel switch H1 ~ Hn that is arranged at each HART device signal output terminal on the basis of Fig. 1 embodiment, have been increased, described multichannel is switched buffer circuit 4 and by channel switch H1 ~ Hn, is connected with n road HART device signal output terminal respectively, described data acquisition circuit 5 is connected with microprocessor 1, the data input pin of described data acquisition circuit 5 is connected with n road HART device signal output terminal by channel switch H1 ~ Hn respectively, the I/O end of described data acquisition circuit 5 is connected with the Enable Pin of channel switch H1 ~ Hn respectively.
Fig. 4 is the 4th embodiment of a kind of HART Communication hardware circuit of the present invention device, it has increased by 16 circuit-switched data Acquisition Circuit 51 on the basis of Fig. 2 embodiment, 8 circuit-switched data Acquisition Circuit 1 and 8 circuit-switched data Acquisition Circuit 2 53, described 8 circuit-switched data Acquisition Circuit 1 connect respectively the HART device signal output terminal on 1 ~ 8 tunnel by channel switch H1 ~ H8, described 8 circuit-switched data Acquisition Circuit 2 53 connect respectively the HART device signal output terminal on 9 ~ 16 tunnels by channel switch H9 ~ H16, described 8 circuit-switched data Acquisition Circuit 1 are connected with microprocessor 1 by 16 circuit-switched data Acquisition Circuit 51 respectively with 8 circuit-switched data Acquisition Circuit 2 53, the I/O end of described 8 circuit-switched data Acquisition Circuit 1 is connected with the Enable Pin of the channel switch H1 ~ H8 on 1 ~ 8 tunnel respectively, the I/O end of described 8 circuit-switched data Acquisition Circuit two is connected with the Enable Pin of the channel switch H9 ~ H16 on 9 ~ 16 tunnels respectively.
The above; it is only preferred embodiment of the present utility model; not the utility model is imposed any restrictions; every any simple modification of above embodiment being done according to the utility model technical spirit, change and equivalent structure change, and all still belong to the protection domain of technical solutions of the utility model.
Claims (5)
1. a HART Communication hardware circuit device, is characterized in that, comprises that buffer circuit is switched in microprocessor, HART modulation-demodulation circuit, HART communication and multichannel is switched buffer circuit, wherein:
Described microprocessor is for sending channel selecting instruction and the HART command information of receiving from external management terminal, and a HART device responds information receiving returns to external management terminal; Described HART modulation-demodulation circuit is for modulating the data that send from described microprocessor or the data of switching buffer circuit transmission from described HART communication being carried out to demodulation; Described HART communication switch buffer circuit for data transmission that described HART modulation-demodulation circuit is sent to corresponding HART equipment and the data of HART device responds are returned to described HART modulation-demodulation circuit; Described multichannel switching buffer circuit is used to HART modulation-demodulation circuit and n road HART equipment to carry out data transmission provides line channel;
Described microprocessor switches buffer circuit by HART modulation-demodulation circuit and HART communication and is connected, described HART communication is switched buffer circuit and is connected with multichannel switching buffer circuit, described multichannel is switched buffer circuit and is connected with n road HART device signal output terminal respectively, and the control signal input end that buffer circuit and multichannel switching buffer circuit are switched in described HART modulation-demodulation circuit, HART communication is connected with the I/O end of microprocessor respectively.
2. HART Communication hardware circuit device according to claim 1, it is characterized in that, n is 16, described multichannel is switched buffer circuit and is comprised that multichannel is switched buffer circuit one and multichannel is switched buffer circuit two, described multichannel is switched the HART device signal output terminal that buffer circuit one connects respectively 1 ~ 8 tunnel, multichannel is switched the HART device signal output terminal that buffer circuit two connects respectively 9 ~ 16 tunnels, the control signal input end that the control signal input end of described multichannel switching buffer circuit one and multichannel are switched buffer circuit two is connected respectively the I/O end of microprocessor, described multichannel is switched buffer circuit one and is connected with HART communication switching buffer circuit with multichannel switching buffer circuit two.
3. HART Communication hardware circuit device according to claim 1, it is characterized in that, also comprise data acquisition circuit and channel switch, described multichannel is switched buffer circuit and by channel switch, is connected with n road HART device signal output terminal respectively, described data acquisition circuit is connected with microprocessor, the data input pin of described data acquisition circuit is connected with n road HART device signal output terminal by channel switch respectively, and the I/O end of described data acquisition circuit is connected with the Enable Pin of channel switch respectively.
4. HART Communication hardware circuit device according to claim 3, it is characterized in that, n is 16, described multichannel is switched buffer circuit and is comprised that multichannel is switched buffer circuit one and multichannel is switched buffer circuit two, described multichannel is switched buffer circuit one and by channel switch, is connected respectively the HART device signal output terminal on 1 ~ 8 tunnel, multichannel is switched buffer circuit two and by channel switch, is connected respectively the HART device signal output terminal on 9 ~ 16 tunnels, the control signal input end that the control signal input end of described multichannel switching buffer circuit one and multichannel are switched buffer circuit two is connected respectively the I/O end of microprocessor, described multichannel is switched buffer circuit one and is connected with HART communication switching buffer circuit with multichannel switching buffer circuit two.
5. HART Communication hardware circuit device according to claim 4, it is characterized in that, described data acquisition circuit comprises 16 circuit-switched data Acquisition Circuit, 8 circuit-switched data Acquisition Circuit one and 8 circuit-switched data Acquisition Circuit two, described 8 circuit-switched data Acquisition Circuit one connect respectively the HART device signal output terminal on 1 ~ 8 tunnel by channel switch, described 8 circuit-switched data Acquisition Circuit two connect respectively the HART device signal output terminal on 9 ~ 16 tunnels by channel switch, described 8 circuit-switched data Acquisition Circuit one are connected with microprocessor by 16 circuit-switched data Acquisition Circuit respectively with 8 circuit-switched data Acquisition Circuit two, the I/O end of described 8 circuit-switched data Acquisition Circuit one is connected with the channel switch Enable Pin on 1 ~ 8 tunnel respectively, the I/O end of described 8 circuit-switched data Acquisition Circuit two is connected with the channel switch Enable Pin on 9 ~ 16 tunnels respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320794946.0U CN203786492U (en) | 2013-12-06 | 2013-12-06 | HART communication hardware circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320794946.0U CN203786492U (en) | 2013-12-06 | 2013-12-06 | HART communication hardware circuit device |
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| Publication Number | Publication Date |
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| CN203786492U true CN203786492U (en) | 2014-08-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201320794946.0U Expired - Fee Related CN203786492U (en) | 2013-12-06 | 2013-12-06 | HART communication hardware circuit device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103631182A (en) * | 2013-12-06 | 2014-03-12 | 杭州优稳自动化系统有限公司 | HART (highway addressable remote transducer) communication hardware circuit device and HART communication method by same |
| CN106094605A (en) * | 2016-02-04 | 2016-11-09 | 北京安控科技股份有限公司 | A kind of HART multichannel switching circuit and method |
| CN106100857A (en) * | 2016-06-20 | 2016-11-09 | 北京安控科技股份有限公司 | A kind of RTU with HART communication function designs device |
-
2013
- 2013-12-06 CN CN201320794946.0U patent/CN203786492U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103631182A (en) * | 2013-12-06 | 2014-03-12 | 杭州优稳自动化系统有限公司 | HART (highway addressable remote transducer) communication hardware circuit device and HART communication method by same |
| CN106094605A (en) * | 2016-02-04 | 2016-11-09 | 北京安控科技股份有限公司 | A kind of HART multichannel switching circuit and method |
| CN106100857A (en) * | 2016-06-20 | 2016-11-09 | 北京安控科技股份有限公司 | A kind of RTU with HART communication function designs device |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140820 Termination date: 20191206 |