CN203774573U - SWD debugging interface device - Google Patents
SWD debugging interface device Download PDFInfo
- Publication number
- CN203774573U CN203774573U CN201320771281.1U CN201320771281U CN203774573U CN 203774573 U CN203774573 U CN 203774573U CN 201320771281 U CN201320771281 U CN 201320771281U CN 203774573 U CN203774573 U CN 203774573U
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- China
- Prior art keywords
- interface
- swd
- decreased
- debugging interface
- type structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 230000003247 decreasing effect Effects 0.000 abstract 4
- 238000010586 diagram Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- Coupling Device And Connection With Printed Circuit (AREA)
Abstract
The utility model discloses an SWD debug interface connecting device. The SWD debug interface connecting device comprises five interface wires which respectively are a power source Vcc, ground Gnd, a data line SWDIO, a clock line SWDCLK and a reset control line Reset. With the SWD debug interface connecting device of the utility model adopted, the number of connecting wires between a debugger and a motherboard can be decreased with debugging normally performed; and when a CPU printed board is drawn, an area occupied by an SWD debugging interface can be decreased, and connecting lines between the SWD debugging interface and a CPU can be decreased, and therefore, cost can be reduced, and complexity in the drawing of the printed board can be decreased.
Description
technical field:
The utility model relates to the jockey of a kind of CPU debugger and cpu motherboard, particularly relates to a kind of SWD debugging interface jockey.
background technology:
Specially power transformation energy information acquisition terminal is the various Data acquisition and storage functions that realize around CPU, need to CPU be programmed and be debugged.Common debud mode has the double contact pin of the 2.54mm spacing of 20 or 14 pins, and these jockey pin numbers are many, and line is many, and the PCB area taking is large, connects relative complex.
utility model content:
Technical problem to be solved in the utility model is: overcome the deficiencies in the prior art, provide a kind of simple, easy to connect and reduce the SWD debugging interface jockey of connecting line quantity between debugger and mainboard.
The technical solution of the utility model is: a kind of SWD debugging interface jockey, contain five interface lines, described five interface lines be respectively power Vcc, Gnd, data wire SWDIO, clock line SWDCLK and reset control line Reset.
The two-port of described five interface lines is respectively jack type structure or plug-type structure.One port of described five interface lines is jack type structure, and another port is plug-type structure.
The beneficial effects of the utility model are:
1, the utility model can be realized when drawing CPU printed board, reduces the area that SWD debugging interface takies, the wiring quantity between minimizing and CPU, thus reduce costs, reduce the complexity while drawing printed board.
2, the utility model, in the situation that guaranteeing that debugging is normally carried out, reduces the connecting line quantity between debugger and mainboard, easy and simple to handle, efficiency is high.
3, the utility model is simple, easy to connect and reduce connecting line quantity between debugger and mainboard, is easy to promotion and implementation, has good economic benefit.
accompanying drawing explanation:
Fig. 1 is the leg signal key diagram of SWD debugging interface jockey;
Fig. 2 is the PCB encapsulation schematic diagram of the jockey of SWD debugging interface shown in Fig. 1.
embodiment:
Embodiment: referring to Fig. 1 and Fig. 2.
SWD debugging interface jockey contains five interface lines, wherein: five interface lines be respectively power Vcc, Gnd, data wire SWDIO, clock line SWDCLK and reset control line Reset.
The two-port of five interface lines is respectively jack type structure or plug-type structure.Or a port of five interface lines is jack type structure, another port is plug-type structure.
According to the signal designation shown in Fig. 1, be connected in the signal source that CPU is corresponding, according to the mode of Fig. 2, place PCB encapsulation, carry out PCB drafting.The signal of debugger is transferred according to the mode of Fig. 1, be connected on the pin that the upper Fig. 2 of PCB is corresponding, can debug, convenient and swift.
Claims (3)
1. a SWD debugging interface jockey, contains five interface lines, it is characterized in that: described five interface lines be respectively power Vcc, Gnd, data wire SWDIO, clock line SWDCLK and reset control line Reset.
2. SWD debugging interface jockey according to claim 1, is characterized in that: the two-port of described five interface lines is respectively jack type structure or plug-type structure.
3. SWD debugging interface jockey according to claim 1, is characterized in that: a port of described five interface lines is jack type structure, and another port is plug-type structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320771281.1U CN203774573U (en) | 2013-12-01 | 2013-12-01 | SWD debugging interface device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320771281.1U CN203774573U (en) | 2013-12-01 | 2013-12-01 | SWD debugging interface device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203774573U true CN203774573U (en) | 2014-08-13 |
Family
ID=51291726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320771281.1U Expired - Fee Related CN203774573U (en) | 2013-12-01 | 2013-12-01 | SWD debugging interface device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203774573U (en) |
-
2013
- 2013-12-01 CN CN201320771281.1U patent/CN203774573U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140813 Termination date: 20191201 |