CN203759109U - Online lightning stroke and lightning current detection device - Google Patents

Abstract

The utility model discloses an online lightning stroke and lightning current detection device, which comprises a lightning current collection device, a data collection circuit and a data transferring circuit, wherein the lightning current collection device is electrically connected with the data collection circuit; and the data collection circuit is electrically connected with the data transferring circuit. The voltage and current detection end of the lightning current collection device is adopted for collecting power supply and current information of a test point, the collected data are stored in an information storage device via the data collection circuit, the judged lightning stroke current signals are sent out via the data transferring circuit. Related information can be automatically detected only by adjusting the position of the detection point, the whole device is simple in structure and convenient in operation, accurate lightning stroke information can be obtained, and the place of lightning stroke release can be accurately judged.

Description

A kind of for thunderbolt and lightning current on-line measuring device

Technical field:

The utility model relates to a kind of on-line measuring device; Relate in particular to a kind of on-line measuring device that is exclusively used in thunderbolt and lightning current detection.

Background technology

According to State Grid Corporation of China's production operation situation analysis in recent years, in 110kV～500kV equipment breakdown, lightning stroke trip number of times ratio accounts for first of transmission facility tripping operation total degree, cause the unplanned stoppage in transit number of times of transmission facility ratio (being only second to outside destroy) to account for second, had a strong impact on safety and the reliability service of electrical network; Solve damage to crops caused by thunder problem, the tripping operation of control transmission line lightning stroke, must be after findding out thunderbolt lead wire and earth wire or shaft tower, judgement lightning wave path is on the mechanism of insulator chain flashover and impact, and what in this process, first will judge is exactly the localization of faults and judgement thunderbolt form; Yet existing checkout equipment is the localization of faults accurately and judgement thunderbolt form all, this is very unfavorable on the mechanism of insulator chain flashover and impact on judgement lightning wave path, therefore, design a kind of localization of faults accurately and judge that the pick-up unit of thunderbolt form becomes a kind of inexorable trend.

Put bright content

The purpose of this utility model is, overcomes the deficiency of conventional art, and a kind of simple in structure, easy to operate on-line measuring device is provided, the localization of faults accurately of this device and judgement thunderbolt form.

For achieving the above object, the technical scheme that the utility model is taked is:

For thunderbolt and a lightning current on-line measuring device, comprise that lightning current harvester, data acquisition circuit and data relay circuit; Described lightning current harvester is electrically connected to data acquisition circuit; Described data acquisition circuit relays circuit with data and is electrically connected to;

Described lightning current harvester comprises the first wire, the second wire and annulus skeleton; Described the second wire is arranged on the inner side of annulus skeleton; Described the first wire is arranged on annulus skeleton; Described the first wire and annulus skeleton are intertwined and connected; Described first wire one end is made as current acquisition end; The other end of described the first wire is made as voltage acquisition end;

Described annulus skeleton is nonmagnetic annulus skeleton;

Described data acquisition circuit comprises input modulate circuit and sampling hold circuit; Described input modulate circuit is electrically connected to sampling hold circuit;

Described input modulate circuit comprises operational amplifier U1, operational amplifier U2, operational amplifier U3, resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, resistance R 7, resistance R 8, resistance R 9, resistance R 10, resistance R 11, resistance R 12, resistance R 13, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, bnc interface P1, bnc interface P2 and rotary switch S1; The 2 pin ground connection of described bnc interface P1; 1 pin of described bnc interface P1 is electrically connected to 3 pin of operational amplifier U1,1 pin of resistance R 2 respectively; 2 pin ground connection of described resistance R 2; 2 pin of described operational amplifier U1 are connected with 6 pin; 6 pin of described operational amplifier U1 are electrically connected to 1 pin of resistance R 1; 2 pin of described resistance R 1 are electrically connected to 7 pin of rotary switch S1; 1 pin of described rotary switch S1 is electrically connected to 1 pin of resistance R 7; 2 pin of described resistance R 7 are electrically connected to 1 pin of capacitor C 1,1 pin of capacitor C 2 respectively; 2 pin of described capacitor C 1 are electrically connected to 1 pin of capacitor C 3,1 pin of resistance R 9 respectively; 2 pin ground connection of described capacitor C 3; 2 pin of described resistance R 9 are electrically connected to 1 pin of bnc interface P2; 2 pin of described capacitor C 2 are electrically connected to 1 pin of resistance R 8,1 pin of capacitor C 4 respectively; 2 pin of described capacitor C 4 are electrically connected to 2 pin of rotary switch S1,1 pin of 2 pin of resistance R 9, bnc interface P2 respectively; 2 pin ground connection of described resistance R 8; The 2 pin ground connection of described bnc interface P2; 3 pin of described rotary switch S1 are electrically connected to 1 pin of resistance R 3; 2 pin of described resistance R 3 are electrically connected to 2 pin of resistance R 4,3 pin of operational amplifier U2 respectively; 1 pin ground connection of described resistance R 4; 2 pin of described operational amplifier U2 are electrically connected to 2 pin of resistance R 5,1 pin of resistance R 6 respectively; 1 pin ground connection of described resistance R 5; 2 pin of described resistance R 6 are electrically connected to 6 pin of operational amplifier U2,1 pin of resistance R 12 respectively; 2 pin of described resistance R 12 are electrically connected to 2 pin of resistance R 13,3 pin of operational amplifier U3 respectively; 1 pin ground connection of described resistance R 13; 2 pin of described operational amplifier U3 are electrically connected to 2 pin of resistance R 11; 1 pin of described resistance R 11 is electrically connected to 1 pin of resistance R 10; 1 pin of described resistance R 11 is ground connection also; 2 pin of described resistance R 10 are electrically connected to 1 pin of bnc interface P2,6 pin of operational amplifier U3 respectively; Connect respectively+5V of the 7 pin power supply of 7 pin of described operational amplifier U1,7 pin of operational amplifier U2, operational amplifier U3; Connect respectively-5V of the 4 pin power supply of 4 pin of described operational amplifier U1,4 pin of operational amplifier U2, operational amplifier U3;

Described capacitor C 1 is in parallel with capacitor C 2;

Described sampling hold circuit comprises resistance R 14, resistance R 15, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, resistance R 21, capacitor C 5, capacitor C 6, capacitor C 7, operational amplifier U4, D/A converter module U5 and information-storing device U6; 1 pin of described capacitor C 5 connects Vin signal; 2 pin of described capacitor C 5 are electrically connected to 2 pin of resistance R 16,3 pin of operational amplifier U4 respectively; 1 pin ground connection of described resistance R 16; 2 pin of described operational amplifier U4 are electrically connected to 2 pin of resistance R 14,1 pin of resistance R 15 respectively; 1 pin ground connection of described resistance R 14; 2 pin of described resistance R 15 are electrically connected to 1 pin of resistance R 17,6 pin of operational amplifier U4 respectively; Connect+5V of the 7 pin power supply of described operational amplifier U4; Connect-5V of the 4 pin power supply of described operational amplifier U4; 2 pin of described resistance R 17 respectively with 1 pin of resistance R 18,1 pin of 1 pin of capacitor C 6, resistance R 19,17 pin of 1 pin of resistance R 20, D/A converter module U5 be electrically connected to; 2 pin ground connection of described resistance R 18; 2 pin ground connection of described capacitor C 6; 2 pin of described resistance R 19 are electrically connected to 14 pin of D/A converter module U5; 2 pin of described resistance R 20 are electrically connected to 13 pin of D/A converter module U5; After the 15 pin parallel connections of 16 pin of described D/A converter module U5 and D/A converter module U5, be electrically connected to 2 pin of capacitor C 7; 1 pin ground connection of described capacitor C 7; 18 pin of described D/A converter module U5,1 pin, the equal ground connection of 12 pin; All access+5 power supplys of 19 pin and 11 pin of described D/A converter module U5; The 20 pin access+3.3V power supplys of described D/A converter module U5; 2 pin of described D/A converter module U5 are electrically connected to 1 pin of information-storing device U6; 3 pin of described D/A converter module U5 are electrically connected to 2 pin of information-storing device U6; 4 pin of described D/A converter module U5 are electrically connected to 3 pin of information-storing device U6; 5 pin of described D/A converter module U5 are electrically connected to 4 pin of information-storing device U6; 6 pin of described D/A converter module U5 are electrically connected to 5 pin of information-storing device U6; 7 pin of described D/A converter module U5 are electrically connected to 6 pin of information-storing device U6; 8 pin of described D/A converter module U5 are electrically connected to 7 pin of information-storing device U6; 9 pin of described D/A converter module U5 are electrically connected to 8 pin of information-storing device U6; The 10 pin incoming clock signals of described D/A converter module U5;

Described capacitor C 6 is in parallel with resistance R 18; Described resistance R 19 is in parallel with resistance R 20;

Described data relay circuit and comprise microcontroller U7, communication controler U8, bus driver U10, photoelectrical coupler U9, photoelectrical coupler U11, resistance R 21, resistance R 22, resistance R 23, resistance R 24, resistance R 25, capacitor C 8, capacitor C 9, capacitor C 10, crystal oscillator Y1 and switch S 2; 9 pin of described microcontroller U7 respectively with 17 pin of communication controler U8,1 pin of 2 pin of resistance R 25, capacitor C 10,1 pin of switch S 2 be electrically connected to; Connect+5 power supplys of 1 pin of described resistance R 25; 2 pin of 2 pin of described capacitor C 10 and switch S 2 are ground connection respectively; 12 pin of described microcontroller U7 are electrically connected to 16 pin of communication controler U8; 16 pin of described microcontroller U7 are electrically connected to 6 pin of communication controler U8; 17 pin of described microcontroller U7 are electrically connected to 5 pin of communication controler U8; 18 pin of described microcontroller U7 are electrically connected to 10 pin of communication controler U8,2 pin of 2 pin of crystal oscillator Y1, capacitor C 9 respectively; 19 pin of described microcontroller U7 are electrically connected to 9 pin of communication controler U8,2 pin of 1 pin of crystal oscillator Y1, capacitor C 8 respectively; Ground connection after 1 pin of described capacitor C 8 is in parallel with 1 pin of capacitor C 9; The 20 pin ground connection of described microcontroller U7; 40 pin of described microcontroller U7 and connect respectively+5V of 31 pin power supply; 39 pin of described microcontroller U7 are electrically connected to 23 pin of communication controler U8; 38 pin of described microcontroller U7 are electrically connected to 24 pin of communication controler U8; 37 pin of described microcontroller U7 are electrically connected to 25 pin of communication controler U8; 36 pin of described microcontroller U7 are electrically connected to 26 pin of communication controler U8; 35 pin of described microcontroller U7 are electrically connected to 27 pin of communication controler U8; 34 pin of described microcontroller U7 are electrically connected to 28 pin of communication controler U8; 33 pin of described microcontroller U7 are electrically connected to 1 pin of communication controler U8; 32 pin of described microcontroller U7 are electrically connected to 2 pin of communication controler U8; 30 pin of described microcontroller U7 are electrically connected to 3 pin of communication controler U8; 28 pin of described microcontroller U7 are electrically connected to 4 pin of communication controler U8; 13 pin of described communication controler U8 are electrically connected to 1 pin of resistance R 21; 2 pin of described resistance R 21 are electrically connected to 3 pin of photoelectrical coupler U9; 8 pin of described photoelectrical coupler U9 and all connect+5V of 7 pin power supply; The 5 pin ground connection of described photoelectrical coupler U9; 6 pin of described photoelectrical coupler U9 are electrically connected to 1 pin of bus driver U10; Connect+5V of the 8 pin power supply of described bus driver U10; 7 pin of described bus driver U10 and the equal ground connection of 4 pin; 6 pin of described bus driver U10 connect CH signal; 5 pin of described bus driver U10 connect CL signal; 2 pin of described bus driver U10 are electrically connected to 6 pin, 3 pin of photoelectrical coupler U11 respectively; 6 pin of described photoelectrical coupler U11 and 3 pin are electrically connected to; 7 pin of described photoelectrical coupler U11 and 8 pin are electrically connected to, and connect+5V power supply; The 5 pin ground connection of described photoelectrical coupler U11; 19 pin of described communication controler U8 are electrically connected to 2 pin of resistance R 22; Connect+5V of the 1 pin power supply of described resistance R 22; 20 pin of described communication controler U8 are electrically connected to 2 pin of resistance R 23,2 pin of resistance R 24 respectively; Connect+5V of the 1 pin power supply of described resistance R 23; 1 pin ground connection of described resistance R 24.

Compared with prior art, the beneficial effects of the utility model are: the utility model adopts voltage and the current detecting end of lightning current harvester, the power supply of collecting test point and current information, and deposit collected data in information-storing device by data acquisition circuit, and by data, relay device the thunder-strike current signal judging is broadcasted out; This device, as long as adjust the position of check point, can detect relevant information automatically, and whole apparatus structure is simple, easy to operate; Can access the information of being struck by lightning accurately, the place that judgement thunderbolt is freeed exactly.

Accompanying drawing explanation

Fig. 1 is structured flowchart of the present utility model;

Fig. 2 is the structural representation of lightning current harvester;

Fig. 3 is the A-A face cut-open view of lightning current harvester;

Fig. 4 is the structured flowchart of data acquisition circuit;

Fig. 5 is the circuit theory diagrams of input modulate circuit;

Fig. 6 is the circuit theory diagrams of sampling hold circuit;

Fig. 7 is the circuit theory diagrams that data relay circuit.

Embodiment

The embodiment providing below in conjunction with accompanying drawing is further described the utility model:

As shown in Figure 1, a kind of for thunderbolt and lightning current on-line measuring device, comprise that lightning current harvester 1, data acquisition circuit 2 and data relay circuit 3; Described lightning current harvester 1 is electrically connected to data acquisition circuit 2; Described data acquisition circuit 2 relays circuit 3 with data and is electrically connected to;

As shown in Figure 2 and Figure 3, described lightning current harvester 1 comprises the first wire 4, the second wire 6 and annulus skeleton 5; Described the second wire 6 is arranged on the inside of annulus skeleton 5; Described the first wire 4 is arranged on annulus skeleton 5; Described the first wire 4 is intertwined and connected with annulus skeleton 5; One end of described the first wire 4 is made as current acquisition end; The other end of described the first wire 4 is made as voltage acquisition end;

Described annulus skeleton 5 is nonmagnetic annulus skeleton;

Described lightning current harvester 1 is mainly by electromagnetic induction principle, the first wire 4 to be wrapped on a nonmagnetic annulus skeleton 5, makes the first wire 4 and annulus skeleton 5 form Luo-coil structure; And being set to respectively electric current induction end and voltage induced end at two line ends of the first wire 4, the variation sensing signal of the tested electric current sensing according to electric current induction end and voltage induced end, judges the size of tested current value;

During current detecting, generally need present the second wire 6 energisings, make it produce certain electric current, getting the first wire 4 is r with the radius of annulus skeleton 5 formed Luo-coils, and the method that electric current is judged is as follows:

Suppose on Luo-coil cross section that magnetic flux everywhere all imagines etc., according to electromagnetic induction principle, learn that the electromagnetism intensity on A-A xsect is:

$H_r=\frac{i}{2\mathrm{\πr}}---\left(1\right)$

Judge the magnetic induction density that dissects a r as:

$B_r={\mathrm{\μ}}_0\frac{i}{2\mathrm{\πr}}---\left(2\right)$

By electromagnetic induction principle known when measuring magnetic linkage and the tested electric current of coil institute interlinkage there is linear relation, so in the situation that coiling area very even and that wire turn comprises is very tiny, can show that like this magnetic linkage of institute's interlinkage on unit length coil is when measuring coil:

$\mathrm{d\ψ}=\frac{\mathrm{NS}}{l}\mathrm{Bdl}---\left(3\right)$

In formula (3): the magnetic induction density of the geometric center that B is coil; S is the area that coil encloses; N is the total number of turns of coil; L is the length of coil; So, the magnetic linkage of whole coil institute interlinkage is:

So induction electromotive force is:

$e\left(t\right)=-\frac{\mathrm{d\ψ}}{\mathrm{dt}}=-M\frac{\mathrm{di}\left(t\right)}{\mathrm{dt}}=-\frac{\mathrm{NS}}{l}{\mathrm{\μ}}_0\frac{\mathrm{di}\left(t\right)}{\mathrm{dt}}---\left(5\right)$

The mutual inductance of Luo-coil is

M＝μ ₀NS/l (6)

In formula: above-mentioned various middle M, S, N, l are respectively mutual inductance, area of section, total number of turns and the length of coil; μ ₀for permeability of vacuum.

Hence one can see that, when primary side is I by root-mean-square valve _nsimple sinusoidal alternating current time, the output voltage root-mean-square valve of Luo-coil is:

E＝ωMI _N(7)

Therefore use this Luo-coil directly to measure potential at output two ends and just can judge exactly thunder-strike current size;

As shown in Figure 4, described data acquisition circuit 2 comprises input modulate circuit 7 and sampling hold circuit 8; Described input modulate circuit 7 is electrically connected to sampling hold circuit 8;

As shown in Figure 5, described input modulate circuit 7 comprises operational amplifier U1, operational amplifier U2, operational amplifier U3, resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, resistance R 7, resistance R 8, resistance R 9, resistance R 10, resistance R 11, resistance R 12, resistance R 13, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, bnc interface P1, bnc interface P2 and rotary switch S1; The 2 pin ground connection of described bnc interface P1; 1 pin of described bnc interface P1 is electrically connected to 3 pin of operational amplifier U1,1 pin of resistance R 2 respectively; 2 pin ground connection of described resistance R 2; 2 pin of described operational amplifier U1 are connected with 6 pin; 6 pin of described operational amplifier U1 are electrically connected to 1 pin of resistance R 1; 2 pin of described resistance R 1 are electrically connected to 7 pin of rotary switch S1; 1 pin of described rotary switch S1 is electrically connected to 1 pin of resistance R 7; 2 pin of described resistance R 7 are electrically connected to 1 pin of capacitor C 1,1 pin of capacitor C 2 respectively; 2 pin of described capacitor C 1 are electrically connected to 1 pin of capacitor C 3,1 pin of resistance R 9 respectively; 2 pin ground connection of described capacitor C 3; 2 pin of described resistance R 9 are electrically connected to 1 pin of bnc interface P2; 2 pin of described capacitor C 2 are electrically connected to 1 pin of resistance R 8,1 pin of capacitor C 4 respectively; 2 pin of described capacitor C 4 are electrically connected to 2 pin of rotary switch S1,1 pin of 2 pin of resistance R 9, bnc interface P2 respectively; 2 pin ground connection of described resistance R 8; The 2 pin ground connection of described bnc interface P2; 3 pin of described rotary switch S1 are electrically connected to 1 pin of resistance R 3; 2 pin of described resistance R 3 are electrically connected to 2 pin of resistance R 4,3 pin of operational amplifier U2 respectively; 1 pin ground connection of described resistance R 4; 2 pin of described operational amplifier U2 are electrically connected to 2 pin of resistance R 5,1 pin of resistance R 6 respectively; 1 pin ground connection of described resistance R 5; 2 pin of described resistance R 6 are electrically connected to 6 pin of operational amplifier U2,1 pin of resistance R 12 respectively; 2 pin of described resistance R 12 are electrically connected to 2 pin of resistance R 13,3 pin of operational amplifier U3 respectively; 1 pin ground connection of described resistance R 13; 2 pin of described operational amplifier U3 are electrically connected to 2 pin of resistance R 11; 1 pin of described resistance R 11 is electrically connected to 1 pin of resistance R 10; 1 pin of described resistance R 11 is ground connection also; 2 pin of described resistance R 10 are electrically connected to 1 pin of bnc interface P2,6 pin of operational amplifier U3 respectively; Connect respectively+5V of the 7 pin power supply of 7 pin of described operational amplifier U1,7 pin of operational amplifier U2, operational amplifier U3; Connect respectively-5V of the 4 pin power supply of 4 pin of described operational amplifier U1,4 pin of operational amplifier U2, operational amplifier U3; Described capacitor C 1 is in parallel with capacitor C 2;

Preferably, the model of described operational amplifier U1, U2, U3 is OPA690;

Preferably, described rotary switch is six rotary switches;

This circuit forms signal attenuation network by rotary switch S1, by three operational amplifier U1, U2, U3, form three grades of structure for amplifying, this main circuit will be realized pin and switch by adjusting rotary switch S1, thereby realizes the decay of signal, straight-through and enlarging function; Operational amplifier U1 forms first order amplifier, and operational amplifier U2 forms second level amplifier; Operational amplifier U3 forms third level amplifier; First order amplifier realizes input impedance 3.5M Ω; The amplification that can realize 5 times is amplified in the second level; The third level is amplified the amplification that realizes 10 times, and three-stage cascade can be realized the gain amplifier of 50 times, and final realization remains on 1.6V left and right by the peak value of output voltage;

As shown in Figure 6, described sampling hold circuit 8 comprises resistance R 14, resistance R 15, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, resistance R 21, capacitor C 5, capacitor C 6, capacitor C 7, operational amplifier U4, D/A converter module U5 and information-storing device U6; 1 pin of described capacitor C 5 connects Vin signal; 2 pin of described capacitor C 5 are electrically connected to 2 pin of resistance R 16,3 pin of operational amplifier U4 respectively; 1 pin ground connection of described resistance R 16; 2 pin of described operational amplifier U4 are electrically connected to 2 pin of resistance R 14,1 pin of resistance R 15 respectively; 1 pin ground connection of described resistance R 14; 2 pin of described resistance R 15 are electrically connected to 1 pin of resistance R 17,6 pin of operational amplifier U4 respectively; Connect+5V of the 7 pin power supply of described operational amplifier U4; Connect-5V of the 4 pin power supply of described operational amplifier U4; 2 pin of described resistance R 17 respectively with 1 pin of resistance R 18,1 pin of 1 pin of capacitor C 6, resistance R 19,17 pin of 1 pin of resistance R 20, D/A converter module U5 be electrically connected to; 2 pin ground connection of described resistance R 18; 2 pin ground connection of described capacitor C 6; 2 pin of described resistance R 19 are electrically connected to 14 pin of D/A converter module U5; 2 pin of described resistance R 20 are electrically connected to 13 pin of D/A converter module U5; After the 15 pin parallel connections of 16 pin of described D/A converter module U5 and D/A converter module U5, be electrically connected to 2 pin of capacitor C 7; 1 pin ground connection of described capacitor C 7; 18 pin of described D/A converter module U5,1 pin, the equal ground connection of 12 pin; All access+5 power supplys of 19 pin and 11 pin of described D/A converter module U5; The 20 pin access+3.3V power supplys of described D/A converter module U5; 2 pin of described D/A converter module U5 are electrically connected to 1 pin of information-storing device U6; 3 pin of described D/A converter module U5 are electrically connected to 2 pin of information-storing device U6; 4 pin of described D/A converter module U5 are electrically connected to 3 pin of information-storing device U6; 5 pin of described D/A converter module U5 are electrically connected to 4 pin of information-storing device U6; 6 pin of described D/A converter module U5 are electrically connected to 5 pin of information-storing device U6; 7 pin of described D/A converter module U5 are electrically connected to 6 pin of information-storing device U6; 8 pin of described D/A converter module U5 are electrically connected to 7 pin of information-storing device U6; 9 pin of described D/A converter module U5 are electrically connected to 8 pin of information-storing device U6; The 10 pin incoming clock signals of described D/A converter module U5; Described capacitor C 6 is in parallel with resistance R 18; Described resistance R 19 is in parallel with resistance R 20;

Preferably, the model of described D/A converter module U5 is ADS831;

Described D/A converter module U5 is unipolarity input, and this main circuit will gather the internal reference source REFT (+3V) of ADS831 and the 2.5V constant pressure source that discharge circuit produces, thereby the effective value of sampled voltage is remained on+2.5V; The highest sampling rate of ADS831 can reach 80MHz; This circuit adopts external crystal oscillator 50.0MHz;

As shown in Figure 7, described data relay circuit 3 and comprise microcontroller U7, communication controler U8, bus driver U10, photoelectrical coupler U9, photoelectrical coupler U11, resistance R 21, resistance R 22, resistance R 23, resistance R 24, resistance R 25, capacitor C 8, capacitor C 9, capacitor C 10, crystal oscillator Y1 and switch S 2; 9 pin of described microcontroller U7 respectively with 17 pin of communication controler U8,1 pin of 2 pin of resistance R 25, capacitor C 10,1 pin of switch S 2 be electrically connected to; Connect+5 power supplys of 1 pin of described resistance R 25; 2 pin of 2 pin of described capacitor C 10 and switch S 2 are ground connection respectively; 12 pin of described microcontroller U7 are electrically connected to 16 pin of communication controler U8; 16 pin of described microcontroller U7 are electrically connected to 6 pin of communication controler U8; 17 pin of described microcontroller U7 are electrically connected to 5 pin of communication controler U8; 18 pin of described microcontroller U7 are electrically connected to 10 pin of communication controler U8,2 pin of 2 pin of crystal oscillator Y1, capacitor C 9 respectively; 19 pin of described microcontroller U7 are electrically connected to 9 pin of communication controler U8,2 pin of 1 pin of crystal oscillator Y1, capacitor C 8 respectively; Ground connection after 1 pin of described capacitor C 8 is in parallel with 1 pin of capacitor C 9; The 20 pin ground connection of described microcontroller U7; 40 pin of described microcontroller U7 and connect respectively+5V of 31 pin power supply; 39 pin of described microcontroller U7 are electrically connected to 23 pin of communication controler U8; 38 pin of described microcontroller U7 are electrically connected to 24 pin of communication controler U8; 37 pin of described microcontroller U7 are electrically connected to 25 pin of communication controler U8; 36 pin of described microcontroller U7 are electrically connected to 26 pin of communication controler U8; 35 pin of described microcontroller U7 are electrically connected to 27 pin of communication controler U8; 34 pin of described microcontroller U7 are electrically connected to 28 pin of communication controler U8; 33 pin of described microcontroller U7 are electrically connected to 1 pin of communication controler U8; 32 pin of described microcontroller U7 are electrically connected to 2 pin of communication controler U8; 30 pin of described microcontroller U7 are electrically connected to 3 pin of communication controler U8; 28 pin of described microcontroller U7 are electrically connected to 4 pin of communication controler U8; 13 pin of described communication controler U8 are electrically connected to 1 pin of resistance R 21; 2 pin of described resistance R 21 are electrically connected to 3 pin of photoelectrical coupler U9; 8 pin of described photoelectrical coupler U9 and all connect+5V of 7 pin power supply; The 5 pin ground connection of described photoelectrical coupler U9; 6 pin of described photoelectrical coupler U9 are electrically connected to 1 pin of bus driver U10; Connect+5V of the 8 pin power supply of described bus driver U10; 7 pin of described bus driver U10 and the equal ground connection of 4 pin; 6 pin of described bus driver U10 connect CH signal; 5 pin of described bus driver U10 connect CL signal; 2 pin of described bus driver U10 are electrically connected to 6 pin, 3 pin of photoelectrical coupler U11 respectively; 6 pin of described photoelectrical coupler U11 and 3 pin are electrically connected to; 7 pin of described photoelectrical coupler U11 and 8 pin are electrically connected to, and connect+5V power supply; The 5 pin ground connection of described photoelectrical coupler U11; 19 pin of described communication controler U8 are electrically connected to 2 pin of resistance R 22; Connect+5V of the 1 pin power supply of described resistance R 22; 20 pin of described communication controler U8 are electrically connected to 2 pin of resistance R 23,2 pin of resistance R 24 respectively; Connect+5V of the 1 pin power supply of described resistance R 23; 1 pin ground connection of described resistance R 24;

Preferably, the model of described microcontroller U7 is AT89C51;

Preferably, the model of described communication controler U8 is SJA1000;

Preferably, the model of described photoelectrical coupler U9, U11 is 6N137;

Preferably, the model of described bus driver U10 is 82C250;

Described SJA1000 is a kind of independently CAN controller, and the Local Area Network being mainly used in moving target and general industry environment is controlled; Its support CAN2.0A with CAN2.0B agreement; IML receives the order from CPU, controls the addressing of CAN register and provides interrupting information and status information to control; The control of CPU writes TXB through IML the data that will send, and the data in TXB are processed and outputed to CAN BUS by BTL by BSP; BTL monitors CAN BUS all the time, when detect effective information header " during the conversion of recessive level control level, start receiving course; first the information of reception will be processed by bit stream processor BSP; and filtered by ACF; only have and check while conforming to as the identification code of the information receiving and ACF, reception information is just finally written in RXB or RXFIF0; RXFIF0 at most can buffer memory 64 bytes data, these data can be read by CPU.EML is responsible for the wrong control of modulator in transfer layer, and the error report that it receives BSP, impels BSP and IML to carry out error statistics;

The setting of CAN controller mode of operation, the sending and receiving of data etc. are all realized by BASIC CAN register.Clock division register OCR is used for setting SJA1000 and works in BASIC CAN or PeliCAN, also for the setting of CLKOUT pin output clock frequency, when power-up initializing controller, must first set: under mode of operation, control register CR is for controlling the behavior of CAN controller, readable writing; Command register CMR only reads and writes; Status register SR can only read; And IR, ACR, AMR, BTR0, BTR1, OCR read and write meaningless under mode of operation; Conventionally, when system initialization, first make CR.0=1, SJA1000 enters reset mode; Under this pattern, equal readable the writing of IR, ACR, AMR, BTR0, BTR1 and OCR, now arranges corresponding initial value; When exiting reset mode, the corresponding situation that SJA1000 sets when resetting works in mode of operation, unless again make chip reset, the value that set last time is constant; When needs send information, if transmit-buffer-empty (TBMT) writes TXB by CPU control information, then control and send by CMR; When reception buffer RXFIF0 less than and receive information exchange and cross ACF, the information receiving is written into RXFIF0.Can read the information receiving by two kinds of methods; A kind of method is, in the situation that interrupting being enabled, by SJA1000, to CPU, sends out look-at-me, and CPU can identify this interruptions by SR and IR, and reading out data release reception buffer; Another kind method is directly to read SR, and the state of inquiry RXFIF0, when having information to receive, reads this signal and discharges reception buffer; In reception buffer, during many information, after current information is read, reception buffer useful signal can be again effective, by interrupt mode or inquiry mode reading information again, till the information of finding RXFIF0 is all read.When RXFIF0 is full, as received in also having information, this reception information is not saved, and sends corresponding impact damper spill over and read processing for CPU;

82C250 is the interface of CAN protocol controller and physical bus, and it can provide differential transmittability and the receiving ability of bus, by 8 pin, selects different working methods: at a high speed, slope is controlled and standby; Under high speed operation mode, transmitter output transistor is simply with fast as far as possible speed conducting and cut-off; In this manner, do not take measures to limit rising and descending slope.For underspeeding or shorter total line length, available unshielded twisted pair or parallel lines are made bus; For reducing Radio frequency interference (RFI), should limit and rise and descending slope; Rising and descending slope can be controlled by 8 pin stake resistances; What in native system, adopt is slope working method; In the network system forming at 82C250, when the TXD of 82C250 end is input as high level, its output terminal CANH and CANL are all high-impedance state, and under this state, 82C250 can not exert an influence to whole network, and we claim this node in back-off state; When TXD end is input as low level, CANH and CANL export respectively high level and low level, and at this moment the character of whole transmitted data on network has this node to determine; The RXD output level of 82C250 is consistent with the level of reigning TXD end in network;

In schematic diagram, AT89C51, as the microcontroller of CAN communication module, is responsible for CAN controller to carry out initialization, by controlling CAN controller, realizes the transmission to image data.CAN control interface is comprised of CAN communication controler SJA1000, photoelectrical coupler 6N137 and CAN bus driver 82C250, and wherein SJA1000 is by being connected with 82C250 after high-speed photoelectric coupler 6N137;

The AD0-AD7 of SJA1000 is connected to the P0 mouth of AT89C51, and CS is connected to the P2.0 of 89C51; P2.0 is that SJA1000 can be chosen in 0 o'clock CPU chip external memory address, and CPU can carry out corresponding read/write operation to SJA1000 by these addresses; The RD of SJA1000, WR, ALE are connected with 89C51 corresponding pin respectively, and INT meets the INT0 of 89C51, and 89C51 also can access SJA1000 by interrupt mode;

In order to strengthen the antijamming capability of CAN node, the TX0 of SJA1000 is not to be directly connected with RXD with the TXD of 82C250 with RX0, but be connected with 82C250 by after high-speed photoelectric coupler 6N137, simultaneously, adopt the DC/DC module B0505T of isolation to optocoupler output terminal and the power supply of CAN bus driver, the electrical isolation of each CAN node in bus, the stability and the security that have improved node have so just well been realized;

The CANH of 82C250 has passed through 5 Ω separately resistance with CANL pin is connected with CAN bus, and resistance can play certain metering function, and protection 82C250 avoids the impact of overcurrent; Two little electric capacity in parallel between CANH and CANL and ground, can play the ability of the high frequency interference that leaches in bus and certain anti-electromagnetic radiation; In addition, between two CAN bus input ends and ground, connect respectively an anti-lightning strike pipe, when occurring between two input ends and ground that transition is disturbed, by the electric discharge of anti-lightning strike pipe, can play certain protective effect; It is a kind of conflicting mode main in electromagnetic compatibility field, particularly lightning surge ripple that transition is disturbed, and because the duration is short, pulse amplitude is high, and energy is large, brings great threat to the normal operation of electronic electric equipment; On the RS pin of 82C250, be connected to a slope resistance, make it be operated in slope mode; In CAN bus, be connected to a wire jumper and 120 Ω resistance (communication media is twisted-pair feeder), wherein resistance is the terminal resistance at bus two ends, i.e. terminal build-out resistor, node during as the node of bus termination, is chosen wire jumper to connect, resistance access bus; Otherwise resistance need not access; In bus, being connected to build-out resistor can strengthen antijamming capability, improves communication reliability and extend communication distance.

Claims (5)

1. for thunderbolt and a lightning current on-line measuring device, comprise lightning current harvester (1), data acquisition circuit (2) and data retransmission circuit (3); It is characterized in that: described lightning current harvester (1) is electrically connected to data acquisition circuit (2); Described data acquisition circuit (2) is electrically connected to data retransmission circuit (3), and described lightning current harvester (1) comprises the first wire (4), the second wire (6) and annulus skeleton (5); Described the second wire (6) is arranged on the inside of annulus skeleton (5); Described the first wire (4) is arranged on annulus skeleton (5); Described the first wire (4) is intertwined and connected with annulus skeleton (5); One end of described the first wire (4) is made as current acquisition end; The other end of described the first wire (4) is made as voltage acquisition end, and described annulus skeleton (5) is nonmagnetic annulus skeleton.

2. according to claim 1 a kind of for thunderbolt and lightning current on-line measuring device, it is characterized in that: described data acquisition circuit (2) comprises input modulate circuit (7) and sampling hold circuit (8); Described input modulate circuit (7) is electrically connected to sampling hold circuit (8).

3. according to claim 2 a kind of for thunderbolt and lightning current on-line measuring device, it is characterized in that: described input modulate circuit (7) comprises operational amplifier U1, operational amplifier U2, operational amplifier U3, resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, resistance R 7, resistance R 8, resistance R 9, resistance R 10, resistance R 11, resistance R 12, resistance R 13, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, bnc interface P1, bnc interface P2 and rotary switch S1; The 2 pin ground connection of described bnc interface P1; 1 pin of described bnc interface P1 is electrically connected to 3 pin of operational amplifier U1,1 pin of resistance R 2 respectively; 2 pin ground connection of described resistance R 2; 2 pin of described operational amplifier U1 are connected with 6 pin; 6 pin of described operational amplifier U1 are electrically connected to 1 pin of resistance R 1; 2 pin of described resistance R 1 are electrically connected to 7 pin of rotary switch S1; 1 pin of described rotary switch S1 is electrically connected to 1 pin of resistance R 7; 2 pin of described resistance R 7 are electrically connected to 1 pin of capacitor C 1,1 pin of capacitor C 2 respectively; 2 pin of described capacitor C 1 are electrically connected to 1 pin of capacitor C 3,1 pin of resistance R 9 respectively; 2 pin ground connection of described capacitor C 3; 2 pin of described resistance R 9 are electrically connected to 1 pin of bnc interface P2; 2 pin of described capacitor C 2 are electrically connected to 1 pin of resistance R 8,1 pin of capacitor C 4 respectively; 2 pin of described capacitor C 4 are electrically connected to 2 pin of rotary switch S1,1 pin of 2 pin of resistance R 9, bnc interface P2 respectively; 2 pin ground connection of described resistance R 8; The 2 pin ground connection of described bnc interface P2; 3 pin of described rotary switch S1 are electrically connected to 1 pin of resistance R 3; 2 pin of described resistance R 3 are electrically connected to 2 pin of resistance R 4,3 pin of operational amplifier U2 respectively; 1 pin ground connection of described resistance R 4; 2 pin of described operational amplifier U2 are electrically connected to 2 pin of resistance R 5,1 pin of resistance R 6 respectively; 1 pin ground connection of described resistance R 5; 2 pin of described resistance R 6 are electrically connected to 6 pin of operational amplifier U2,1 pin of resistance R 12 respectively; 2 pin of described resistance R 12 are electrically connected to 2 pin of resistance R 13,3 pin of operational amplifier U3 respectively; 1 pin ground connection of described resistance R 13; 2 pin of described operational amplifier U3 are electrically connected to 2 pin of resistance R 11; 1 pin of described resistance R 11 is electrically connected to 1 pin of resistance R 10; 1 pin of described resistance R 11 is ground connection also; 2 pin of described resistance R 10 are electrically connected to 1 pin of bnc interface P2,6 pin of operational amplifier U3 respectively; Connect respectively+5V of the 7 pin power supply of 7 pin of described operational amplifier U1,7 pin of operational amplifier U2, operational amplifier U3; Connect respectively-5V of the 4 pin power supply of 4 pin of described operational amplifier U1,4 pin of operational amplifier U2, operational amplifier U3; Described capacitor C 1 is in parallel with capacitor C 2.

4. according to claim 2 a kind of for thunderbolt and lightning current on-line measuring device, it is characterized in that: described sampling hold circuit (8) comprises resistance R 14, resistance R 15, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, resistance R 21, capacitor C 5, capacitor C 6, capacitor C 7, operational amplifier U4, D/A converter module U5 and information-storing device U6; 1 pin of described capacitor C 5 connects Vin signal; 2 pin of described capacitor C 5 are electrically connected to 2 pin of resistance R 16,3 pin of operational amplifier U4 respectively; 1 pin ground connection of described resistance R 16; 2 pin of described operational amplifier U4 are electrically connected to 2 pin of resistance R 14,1 pin of resistance R 15 respectively; 1 pin ground connection of described resistance R 14; 2 pin of described resistance R 15 are electrically connected to 1 pin of resistance R 17,6 pin of operational amplifier U4 respectively; Connect+5V of the 7 pin power supply of described operational amplifier U4; Connect-5V of the 4 pin power supply of described operational amplifier U4; 2 pin of described resistance R 17 respectively with 1 pin of resistance R 18,1 pin of 1 pin of capacitor C 6, resistance R 19,17 pin of 1 pin of resistance R 20, D/A converter module U5 be electrically connected to; 2 pin ground connection of described resistance R 18; 2 pin ground connection of described capacitor C 6; 2 pin of described resistance R 19 are electrically connected to 14 pin of D/A converter module U5; 2 pin of described resistance R 20 are electrically connected to 13 pin of D/A converter module U5; After the 15 pin parallel connections of 16 pin of described D/A converter module U5 and D/A converter module U5, be electrically connected to 2 pin of capacitor C 7; 1 pin ground connection of described capacitor C 7; 18 pin of described D/A converter module U5,1 pin, the equal ground connection of 12 pin; All access+5 power supplys of 19 pin and 11 pin of described D/A converter module U5; The 20 pin access+3.3V power supplys of described D/A converter module U5; 2 pin of described D/A converter module U5 are electrically connected to 1 pin of information-storing device U6; 3 pin of described D/A converter module U5 are electrically connected to 2 pin of information-storing device U6; 4 pin of described D/A converter module U5 are electrically connected to 3 pin of information-storing device U6; 5 pin of described D/A converter module U5 are electrically connected to 4 pin of information-storing device U6; 6 pin of described D/A converter module U5 are electrically connected to 5 pin of information-storing device U6; 7 pin of described D/A converter module U5 are electrically connected to 6 pin of information-storing device U6; 8 pin of described D/A converter module U5 are electrically connected to 7 pin of information-storing device U6; 9 pin of described D/A converter module U5 are electrically connected to 8 pin of information-storing device U6; The 10 pin incoming clock signals of described D/A converter module U5; Described capacitor C 6 is in parallel with resistance R 18; Described resistance R 19 is in parallel with resistance R 20.

5. according to claim 1 a kind of for thunderbolt and lightning current on-line measuring device, it is characterized in that: described data retransmission circuit (3) comprises microcontroller U7, communication controler U8, bus driver U10, photoelectrical coupler U9, photoelectrical coupler U11, resistance R 21, resistance R 22, resistance R 23, resistance R 24, resistance R 25, capacitor C 8, capacitor C 9, capacitor C 10, crystal oscillator Y1 and switch S 2; 9 pin of described microcontroller U7 respectively with 17 pin of communication controler U8,1 pin of 2 pin of resistance R 25, capacitor C 10,1 pin of switch S 2 be electrically connected to; Connect+5 power supplys of 1 pin of described resistance R 25; 2 pin of 2 pin of described capacitor C 10 and switch S 2 are ground connection respectively; 12 pin of described microcontroller U7 are electrically connected to 16 pin of communication controler U8; 16 pin of described microcontroller U7 are electrically connected to 6 pin of communication controler U8; 17 pin of described microcontroller U7 are electrically connected to 5 pin of communication controler U8; 18 pin of described microcontroller U7 are electrically connected to 10 pin of communication controler U8,2 pin of 2 pin of crystal oscillator Y1, capacitor C 9 respectively; 19 pin of described microcontroller U7 are electrically connected to 9 pin of communication controler U8,2 pin of 1 pin of crystal oscillator Y1, capacitor C 8 respectively; Ground connection after 1 pin of described capacitor C 8 is in parallel with 1 pin of capacitor C 9; The 20 pin ground connection of described microcontroller U7; 40 pin of described microcontroller U7 and connect respectively+5V of 31 pin power supply; 39 pin of described microcontroller U7 are electrically connected to 23 pin of communication controler U8; 38 pin of described microcontroller U7 are electrically connected to 24 pin of communication controler U8; 37 pin of described microcontroller U7 are electrically connected to 25 pin of communication controler U8; 36 pin of described microcontroller U7 are electrically connected to 26 pin of communication controler U8; 35 pin of described microcontroller U7 are electrically connected to 27 pin of communication controler U8; 34 pin of described microcontroller U7 are electrically connected to 28 pin of communication controler U8; 33 pin of described microcontroller U7 are electrically connected to 1 pin of communication controler U8; 32 pin of described microcontroller U7 are electrically connected to 2 pin of communication controler U8; 30 pin of described microcontroller U7 are electrically connected to 3 pin of communication controler U8; 28 pin of described microcontroller U7 are electrically connected to 4 pin of communication controler U8; 13 pin of described communication controler U8 are electrically connected to 1 pin of resistance R 21; 2 pin of described resistance R 21 are electrically connected to 3 pin of photoelectrical coupler U9; 8 pin of described photoelectrical coupler U9 and all connect+5V of 7 pin power supply; The 5 pin ground connection of described photoelectrical coupler U9; 6 pin of described photoelectrical coupler U9 are electrically connected to 1 pin of bus driver U10; Connect+5V of the 8 pin power supply of described bus driver U10; 7 pin of described bus driver U10 and the equal ground connection of 4 pin; 6 pin of described bus driver U10 connect CH signal; 5 pin of described bus driver U10 connect CL signal; 2 pin of described bus driver U10 are electrically connected to 6 pin, 3 pin of photoelectrical coupler U11 respectively; 6 pin of described photoelectrical coupler U11 and 3 pin are electrically connected to; 7 pin of described photoelectrical coupler U11 and 8 pin are electrically connected to, and connect+5V power supply; The 5 pin ground connection of described photoelectrical coupler U11; 19 pin of described communication controler U8 are electrically connected to 2 pin of resistance R 22; Connect+5V of the 1 pin power supply of described resistance R 22; 20 pin of described communication controler U8 are electrically connected to 2 pin of resistance R 23,2 pin of resistance R 24 respectively; Connect+5V of the 1 pin power supply of described resistance R 23; 1 pin ground connection of described resistance R 24.