CN203746827U - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- CN203746827U CN203746827U CN201420122157.7U CN201420122157U CN203746827U CN 203746827 U CN203746827 U CN 203746827U CN 201420122157 U CN201420122157 U CN 201420122157U CN 203746827 U CN203746827 U CN 203746827U
- Authority
- CN
- China
- Prior art keywords
- insulating barrier
- wiring layer
- insulating
- semiconductor device
- insulating component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000001746 injection moulding Methods 0.000 claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims description 45
- 239000002184 metal Substances 0.000 description 10
- 239000011347 resin Substances 0.000 description 9
- 229920005989 resin Polymers 0.000 description 9
- 239000000463 material Substances 0.000 description 5
- 230000008719 thickening Effects 0.000 description 5
- 230000035882 stress Effects 0.000 description 4
- 208000034189 Sclerosis Diseases 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model provides a semiconductor device, comprising an insulating layer, a plurality of wiring layers disposed on the insulating layer at equal intervals, a semiconductor element disposed on the wiring layer, and an injection molding part covering the insulating layer, the wiring layer and the semiconductor element. The insulating layer is configured in that an interval part disposed among a plurality of wiring layers is thicker than a part having the wiring layer. The semiconductor device is advantageous in that the injection molding part among the wiring layer can be prevented from being peeled off from the insulating layer.
Description
Technical field
The utility model relates to a kind of semiconductor device.
Background technology
In the past, possesses the semiconductor device of the injection molding part being formed by resin known.For example, in the disclosed semiconductor module of patent documentation 1 (semiconductor device), on sheet metal part (metallic plate), be provided with dielectric film (insulating barrier), on dielectric film, be provided with multiple metal derbies (wiring layer), on metal derby, be provided with semiconductor element.Dielectric film is processed to smooth tabular, and multiple metal derbies are configured in the surface of dielectric film separated by a certain intervally.And in such semiconductor module, dielectric film, metal derby and semiconductor element are all covered with by resin mold portion (injection molding part).Particularly, resin injection molding part, in covering metal piece and semiconductor element, is also filled the interval between metal derby.Therefore, the dielectric film between metal derby can contact with resin injection molding part.
But in the semiconductor module of above-mentioned prior art, the shrinkage stress producing because of resin injection molding partially hardened may cause the resin injection molding part between metal derby to be peeled off from dielectric film.
[patent documentation 1]: No. 2012/029165 communique of PCT International Publication
Utility model content
For above-mentioned technical problem, the purpose of this utility model is, the semiconductor device that provides a kind of injection molding part that can prevent the interval between wiring layer to peel off from insulating barrier.
As the technical scheme solving the problems of the technologies described above, the utility model provides a kind of semiconductor device.This semiconductor device has, insulating barrier, at a distance of predetermined distance be arranged on multiple wiring layers on described insulating barrier, be arranged on the semiconductor element on described wiring layer and cover the injection molding part of described insulating barrier, described wiring layer and described semiconductor element, it is characterized in that: described insulating barrier is constituted as, the part at the interval between described multiple wiring layers is thicker than the segment thickness that disposes described wiring layer.
The advantage with the semiconductor device of the present utility model of said structure is, by thickening the thickness of insulating barrier at the interval between multiple wiring layers, compared with the situation of the insulating barrier having an even surface with employing, sclerosis shrinkage stress that can the injection molding part of peptizaiton on the surface of insulating layer at the interval between multiple wiring layers, therefore can prevent that the injection molding part between wiring layer from peeling off from insulating barrier.
In above-mentioned semiconductor device, described insulating barrier also can comprise, is processed into smooth the 1st tabular insulating component and is arranged on the 2nd insulating component on described the 1st insulating component.
The advantage with the semiconductor device of the present utility model of said structure is, is convenient to realize the part thickening of insulating barrier.
Brief description of the drawings
What Fig. 1 represented is the profile of the semiconductor device of execution mode.
What Fig. 2 represented is the profile of the semiconductor device of the 1st kind of variation of execution mode.
What Fig. 3 represented is the profile of the semiconductor device of the 2nd kind of variation of execution mode.
What Fig. 4 represented is the profile of the semiconductor device of the 3rd kind of variation of execution mode.
Embodiment
Below, with reference to accompanying drawing, execution mode of the present utility model is described.But the utility model is not by following execution mode is limited.And the size relationship (length and width etc.) in each figure does not reflect actual size relationship yet.
First, with reference to Fig. 1, the semiconductor device 100 of a kind of execution mode of the present utility model is described.This semiconductor device 100 is for example for controlling the frequency changer circuit of automobile motor.
As shown in Figure 1, semiconductor device 100 has, metallic plate 1, insulating barrier 2, wiring layer 3, scolder 4, semiconductor element 5 and injection molding part 6.
On the surface of metallic plate 1, be provided with insulating barrier 2.On the surface of insulating barrier 2, separate predetermined distance and be provided with multiple wiring layers 3.On the surface of wiring layer 3, be connected with semiconductor element 5 by scolder 4.In addition, injection molding part 6 is injected into and is molded over the face side of metallic plate 1 to cover the mode of insulating barrier 2, wiring layer 3, scolder 4 and semiconductor element 5.Conventionally,, in order to improve the heat dispersion of semiconductor device 100, adopt so-called half injection-molded structure (structure that the rear side of metallic plate 1 exposes).
Insulating barrier 2 is processed to, and the part at the interval between multiple wiring layers 3 is thicker than the segment thickness that disposes wiring layer 3.That is, insulating barrier 2 is processed to, the part projection upward at the interval between multiple wiring layers 3.Particularly, insulating barrier 2 comprises, is processed into smooth the 1st tabular insulating component 21 and is arranged on the 2nd insulating component 22 on the 1st insulating component 21.
The 1st insulating component 21 is for example the dielectric film being formed from a resin, and it has high-insulativity and high-termal conductivity.More than the thermal conductivity of the 1st insulating component 21 is preferably 3W/mK.
The 2nd insulating component 22 is for example the dielectric film being formed from a resin, and it has high-insulativity.The cross section of the 2nd insulating component 22 is rectangle, and its bottom surface engages with the end face of the 1st insulating component 21.And the 2nd insulating component 22 and the 1st insulating component 21 are processed by different materials.Specifically, due to different from the 1st insulating component 21, the 2nd insulating component 22 does not need to have thermal conductivity, therefore can adopt the material of thermal conductivity lower than the 1st insulating component 21.Thereby, in the 2nd insulating component 22, do not add the filler that improves thermal conductivity, in addition, the 2nd insulating component 22 to the 1 insulating component 21 hardness are harder.
On the surface of the 1st insulating component 21, multiple wiring layers 3 are separated by predetermined distance along this surperficial a direction (left and right directions in Fig. 1) and are configured.And, between these wiring layers 3, configuring the 2nd insulating component 22.In addition, between wiring layer 3 and the 2nd insulating component 22, leave certain interval, this gap is injection moulded part 6 and fills.
Each wiring layer 3 is for example the tabular component being made of metal, and has the function distributing after heat absorption.Therefore the heat that, semiconductor element 5 produces is easily via wiring layer 3 and the 1st insulating component 21 and be passed on metallic plate 1.
Semiconductor element 5 is connected with wiring layer 3 by scolder 4.In addition, on wiring layer 3, both can connect a semiconductor element 5, also can connect multiple semiconductor elements 5.This semiconductor element 5 is for example IGBT(insulated gate bipolar transistor) etc. power semiconductor element.In addition, on the surface of semiconductor element 5, be connected with Wiring construction element (diagram is omitted).
Injection molding part 6 is for example to be formed by the process of resin that contains mould release.Injection molding part 6 is in covering wiring layer 3 and semiconductor element 5, also by the space-filling between each wiring layer 3.Therefore, the insulating barrier 2 at the interval between wiring layer 3 contacts with injection molding part 6.Particularly, the surface of the 1st insulating component 21 between the 2nd insulating component 22 and wiring layer 3 contacts with injection molding part 6, and the surface of the 2nd insulating component 22 and side also contact with injection molding part 6.
In the present embodiment, by as described above, by the part thickening at the interval between multiple wiring layers 3 in insulating barrier 2, compared with adopting smooth tabular insulating barrier 2, the surface of insulating layer being thickened between wiring layer can the interval of peptizaiton between wiring layer 3 the sclerosis shrinkage stress of the lip-deep injection molding part 6 of insulating barrier 2, thereby can prevent that the injection molding part 6 at the interval between wiring layer 3 from peeling off from insulating barrier 2.And, add thick dielectric layer 2, can also make corresponding the reducing of volume of injection molding part 6, thereby reduce sclerosis shrinkage stress.Thus, can effectively prevent that the injection molding part 6 between wiring layer 3 from peeling off from insulating barrier 2.
In addition, by injecting injection molding part 6 in the gap of (between the 2nd insulating component 22 and wiring layer 3) between the part and wiring layer 3 that are thickened at insulating barrier 2, utilize grappling effect can make the adhesion strength of injection molding part 6 improve.There is the situation that injection molding part 6 is peeled off from insulating barrier 2 in the thermal stress producing therefore, can prevent from working because of semiconductor device 100 time.
In addition, add thick dielectric layer 2 by part, compared with the situation that shows smooth tabular insulating barrier with employing, can increase the creepage distance between wiring layer 3, therefore, even if injection molding part 6 is peeled off from insulating barrier 2, be also not easy to cause insulation damages.
In addition, in the present embodiment, by the 2nd insulating component 22 being set being processed on smooth the 1st tabular insulating component 21, can easily realize the part thickening of insulating barrier 2.
In addition, in the present embodiment, because the 1st insulating component 21 and the 2nd insulating component 22 are processed by different materials, therefore, in having improved the thermal conductivity of the 1st insulating component 21, can make the 2nd insulating component 22 to the 1 insulating components 21 harder.
In addition, in the present embodiment, by multiple wiring layers 3 are set, with compared with independent each wiring layer encapsulation modularization, can realize miniaturization.
In addition, in the present embodiment, by multiple wiring layers 3 are set on an insulating barrier 2, compared with each wiring layer being arranged respectively to the situation of insulating barrier, can consider the position deviation between these insulating barriers.
In addition, in the present embodiment, show the application examples that insulating barrier 2 is set on the surface of metallic plate 1, but be not limited to this, the semiconductor device 200 of the 1st variation is as shown in Figure 2 such, and insulating barrier 2 also can be set on the surface of radiator 201.Radiator 201 comprises, metallic plate 201a and multiple fin 201b.On the surface of metallic plate 201a, be provided with insulating barrier 2.These fins 201b is processed to, and extends downwards from the rear side of metallic plate 201a.By this structure, can improve thermal diffusivity.
In addition, the semiconductor device 300 of the 2nd variation is as shown in Figure 3 such, and insulating barrier 2 also can be set on the surface of cooler 301.Cooler 301 comprises, is provided with the metallic plate 301a of insulating barrier 2 on table.By this structure, can improve thermal diffusivity.
In addition, in the present embodiment, show by the 1st insulating component 21 is engaged with the 2nd insulating component 22, and the application examples of thickening the insulating barrier 2 at the interval between wiring layer 3, but be not limited to this, the semiconductor device 400 of the 3rd variation is as shown in Figure 4 such, also can, by smear the 2nd insulating component 402 on the 1st insulating component 21, thicken the insulating barrier 401 at the interval between wiring layer 3.
In addition, in the present embodiment, the application examples that the cross section that shows the 2nd insulating component 22 is rectangle, but being not limited to this, the cross section of the 2nd insulating component also can be circular shape.,, as long as can make the thickness of the insulating barrier between wiring layer increase, the cross section of the 2nd insulating component can be any shape.
In addition, in the present embodiment, show the application examples that the 1st insulating component 21 and the 2nd insulating component 22 are processed by different materials, but be not limited to this, the 1st insulating component and the 2nd insulating component also can be processed by same material.And the 1st insulating component and the 2nd insulating component also can be processed into one.
Claims (2)
1. a semiconductor device, have insulating barrier, at a distance of predetermined distance be arranged on multiple wiring layers on described insulating barrier, be arranged on the semiconductor element on described wiring layer and cover the injection molding part of described insulating barrier, described wiring layer and described semiconductor element, it is characterized in that:
Described insulating barrier is constituted as, and the part at the interval between described multiple wiring layers is thicker than the segment thickness that disposes described wiring layer.
2. semiconductor device as claimed in claim 1, is characterized in that:
Described insulating barrier comprises, is processed into smooth the 1st tabular insulating component and is arranged on the 2nd insulating component on described the 1st insulating component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420122157.7U CN203746827U (en) | 2014-03-18 | 2014-03-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420122157.7U CN203746827U (en) | 2014-03-18 | 2014-03-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203746827U true CN203746827U (en) | 2014-07-30 |
Family
ID=51346590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420122157.7U Expired - Lifetime CN203746827U (en) | 2014-03-18 | 2014-03-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203746827U (en) |
-
2014
- 2014-03-18 CN CN201420122157.7U patent/CN203746827U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140730 |
|
| CX01 | Expiry of patent term |