CN203733452U - Array substrate, display panel and display apparatus - Google Patents
Array substrate, display panel and display apparatus Download PDFInfo
- Publication number
- CN203733452U CN203733452U CN201420135253.5U CN201420135253U CN203733452U CN 203733452 U CN203733452 U CN 203733452U CN 201420135253 U CN201420135253 U CN 201420135253U CN 203733452 U CN203733452 U CN 203733452U
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- gate driver
- driver circuit
- array base
- base palte
- viewing area
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- 239000000758 substrate Substances 0.000 title abstract 5
- 239000010409 thin film Substances 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 210000003141 lower extremity Anatomy 0.000 description 5
- 230000002146 bilateral effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005549 size reduction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The utility model provides an array substrate, a display panel and a display apparatus, belongs to the technical field of display apparatus manufacture, and helps to solve the problem that the border width of a conventional display panel is wide. The array substrate comprises a display area and a non-display area. The non-display area comprises at least one column of gate drive circuit; and in the column direction, the size of the at least one column of gate drive circuit is larger than that of the display area. The display panel comprises the array substrate above. The display apparatus comprises the display panel above. According to the array substrate, the display panel and the display apparatus, the border width of the display panel can be reduced.
Description
Technical field
The utility model belongs to display technique field, is specifically related to a kind of array base palte, display panel and display device.
Background technology
At Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, be called for short TFT-LCD) in, have and a kind ofly directly gate driver circuit is produced on to the technology (Gate Driver on Array, GOA) on array base palte.This technology is formed directly into gate driver circuit around the viewing area of array base palte by composition technique, thereby can further simplify manufacture craft, improve the integrated level of the display panel of TFT-LCD, reduce the frame size of display device, make display panel more frivolous, also reduced the production cost of product simultaneously.
While making array base palte, can make one group of gate driver circuit in a side of its viewing area, form the array base palte of monolateral driving, also can make another group gate driver circuit at the opposite side of viewing area simultaneously, form the array base palte of bilateral driving.With respect to the array base palte of monolateral driving, it is existing to the thin film transistor (TFT) bad problem of charging that the array base palte of bilateral driving can improve the array base palte of monolateral driving, thereby promote the display quality of display panel.
Inventor finds that in prior art, at least there are the following problems: the array base palte of existing employing grid Driving technique, as shown in Figure 1, described array base palte 1 comprises the non-display area (for lead-in wire and driving circuit etc. are set) of viewing area 5 and viewing area surrounding, in viewing area 5, be provided with multirow pixel cell 4, each pixel cell 4 is for independently showing, in the non-display area in 5 left sides, viewing area, be provided with a row gate driver circuit, wherein each gate driver circuit 3 (is that each gate driver circuit 3 is connected with clock circuit 2 with one-row pixels unit 4 correspondences, also connect a gate line simultaneously, this gate line connects the grid of the thin film transistor (TFT) of one-row pixels unit 4), and the size of the size of each gate driver circuit 3 and corresponding pixel cell 4 is the same on column direction, this row gate driver circuit " aligns " with viewing area 5 on column direction like this, in the non-display area of both sides Shang Xia 5, viewing area, be provided with the structures such as data cable connector, but be not provided with useful structure in the non-display area of these row gate driver circuit both sides Shang Xia 3 (i.e. hatched area in figure), therefore this region is underutilized, cause the utilization factor of array base palte 1 to reduce, simultaneously, each gate driver circuit 3 obviously comprises some devices and lead-in wire etc., due to its limited space on column direction, therefore these devices are set and go between and just must occupy in the row direction larger space, this just causes gate driver circuit 3 size on column direction less, and it is larger to go up in the row direction size, make the wider width of the non-display area in array base palte 1 left side, be unfavorable for the design of the narrower frame of display panel realization.
Utility model content
Technical problem to be solved in the utility model comprises, for the wider problem of the border width of existing display panel, provides a kind of array base palte, display panel and display device, and it has the narrower frame of width.
The technical scheme that solution the utility model technical matters adopts is a kind of array base palte, comprises a kind of array base palte, comprising:
Viewing area and non-display area;
Described non-display area comprises at least one row gate driver circuit;
It is characterized in that, on column direction, the size of the described gate driver circuit of at least one row is greater than the size of described viewing area.
The size of array base palte gate driver circuit of the present utility model is greater than the size of described sub-pixel unit, the left side of array base palte has obtained and has made full use of near the non-display area of lower limb on array base palte like this, make the narrowed width of the non-display area in array base palte left side, thereby can make display panel there is the narrower frame of width.
Preferably, at least one end of the described gate driver circuit of at least one row exceeds viewing area.
Further preferably, each two ends that are listed as described gate driver circuit all exceeds viewing area, and exceeds the measure-alike of viewing area.
Preferably, described array base palte comprises first row gate driver circuit and secondary series gate driver circuit, outside the described first row gate driver circuit both sides of being located at viewing area relative to secondary series gate driver circuit;
The two ends of the two ends of described first row gate driver circuit and described secondary series gate driver circuit are totally four ends, in described four ends, have at least one end to exceed viewing area.
Further preferably, described four ends all exceed viewing area, and exceed the measure-alike of viewing area.
Preferably, described array base palte also comprises many data lines and multiple thin film transistor (TFT), and the source electrode of each thin film transistor (TFT) is connected with a described data line, and its drain electrode is connected with the electrode in a described pixel cell.
Preferably, described viewing area comprises multirow pixel cell;
The each described gate driver circuit of the described gate driver circuit of every row and one-row pixels unit correspondence;
Described array base palte also comprises many grid lines, every the corresponding one-row pixels of grid line unit, and the each gate driver circuit in every row gate driver circuit connects a grid line.
Preferably, described gate driver circuit comprises shifting deposit unit and output buffer cell, the input end of described shifting deposit unit is connected with clock circuit, its output terminal is connected with the input end of the shifting deposit unit of next stage gate driver circuit, the output terminal of shifting deposit unit is also connected with the input end of output buffer cell, and the output terminal of output buffer cell connects a line display unit.
The technical scheme that solution the utility model technical matters adopts is a kind of display panel, and described display panel comprises above-mentioned array base palte.
The technical scheme that solution the utility model technical matters adopts is a kind of display device, and described display device comprises above-mentioned display panel.
Display panel of the present utility model comprises above-mentioned array base palte, and display device comprises above-mentioned array base palte, and therefore the width of the frame of display device is narrower, and outward appearance is more attractive in appearance.
Brief description of the drawings
Fig. 1 is the structural representation of existing array base palte;
Fig. 2 is the structural representation of the array base palte of embodiment 1 of the present utility model;
Fig. 3 is the another kind of structural representation of the array base palte of embodiment 1 of the present utility model;
Fig. 4 is the composition schematic diagram of the gate driver circuit of embodiment 1 of the present utility model.
Wherein Reference numeral is: 1, array base palte; 2, clock circuit; 3, gate driver circuit; 4, pixel cell; 5, viewing area.
Embodiment
For making those skilled in the art understand better technical scheme of the present invention, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.Obviously, described embodiment is a part of embodiment of the present utility model, instead of whole embodiment.Based on described embodiment of the present utility model, those of ordinary skill in the art, without paying the every other embodiment obtaining under the prerequisite of creative work, belong to the scope of the utility model protection.
Embodiment 1:
The present embodiment provides a kind of array base palte, can be used for making thin-film transistor LCD device.As shown in Figures 2 and 3, array base palte 1 is divided into the non-display area of viewing area 5 and viewing area 5 surroundings, and non-display area is used for arranging lead-in wire and driving circuit etc. is set.In the present embodiment, non-display area comprises at least one row gate driver circuit; On column direction, the size of at least one row gate driver circuit is greater than the size of viewing area 5.In accompanying drawing 2, illustrate that non-display area is provided with the situation of a row gate driver circuit, this row gate driver circuit comprises multiple gate driver circuits 3, this row gate driver circuit is located at outside 5 first sides of viewing area, also be located in the non-display area of array base palte 1 left side (also can be located at array base palte 1 right side), wherein, in the viewing area 5 of array base palte 1, be provided with multiple pixel cells 4, it is ranks and arranges, each gate driver circuit 3 and one-row pixels unit 4 correspondences, on column direction (being the column direction of ranks in arranging with pixel cell is same direction), the size of gate driver circuit 3 is greater than the size of pixel cell 4.
The size of the gate driver circuit 3 of the array base palte 1 of the present embodiment is greater than the size of pixel cell 4 on column direction, also be that gate driver circuit 3 size on column direction becomes large, thereby (with the perpendicular direction of column direction) upper size reduction in the row direction, thereby this row gate driver circuit is greater than the size of viewing area 5 on column direction, the left side of array base palte 1 has obtained and has made full use of near the non-display area of lower limb on array base palte 1 like this, make the narrowed width of the non-display area in array base palte 1 left side, thereby can make display panel there is the narrower frame of width.
Preferably, at least one end of at least one row gate driver circuit exceeds viewing area 5.
Further preferred, the two ends of each row gate driver circuit exceed viewing area 5, and exceed the measure-alike of viewing area 5.Can make full use of like this left side of array base palte 1 near the non-display area of lower limb on array base palte 1, realize the design of narrower frame, can also make the width of array base palte frame of both sides Shang Xia 1 be consistent.
Preferably, as shown in Figure 3, array base palte 1 comprises first row gate driver circuit and secondary series gate driver circuit, first row gate driver circuit two outsides being located at viewing area relative to secondary series gate driver circuit.Also be located at outside the left and right sides of viewing area 5.
Preferably, first row and secondary series gate driver circuit include multiple gate driver circuits 3, each gate driver circuit 3 and one-row pixels unit 4 correspondences.That is to say under this kind of situation, array base palte 1 comprises first row gate driver circuit and secondary series gate driver circuit.The array base palte 1 of this kind of situation is that bilateral grid drives, and it is existing to the thin film transistor (TFT) bad problem of charging that the array of bilateral driving can improve the array base palte 1 of monolateral driving, thereby promotes the display quality of display panel.
Wherein, preferred, the two ends of the two ends of first row gate driver circuit and secondary series gate driver circuit totally four ends, four ends have at least one end to exceed viewing area 5.
Further preferred, four ends all exceed viewing area 5, and exceed the measure-alike of viewing area 5.Can make full use of like this left and right sides of array base palte 1 near the non-display area of lower limb on array base palte 1, realize the design of narrower frame, can also make the width of array base palte frame of both sides Shang Xia 1 be consistent.
Because the size of the each gate driver circuit 3 on array base palte 1 is greater than the size of pixel cell 4, gate driver circuit 3 size on column direction becomes large, and go up in the row direction size reduction, the left and right sides of array base palte 1 has obtained and has made full use of near the non-display area of lower limb on array base palte 1 like this, make the narrowed width of the non-display area of array base palte 1 left and right sides, thereby can make display panel there is the narrower frame of width.
Preferably, viewing area 5 comprises multirow pixel cell 4, each gate driver circuit 3 of every row gate driver circuit and one-row pixels unit 4 correspondences, array base palte 1 also comprises many grid lines, every the corresponding one-row pixels of grid line unit 4, the each gate driver circuit 3 in every row gate driver circuit 3 connects a grid line.Like this, the driving signal that gate driver circuit 3 sends imports to the grid of the thin film transistor (TFT) in pixel cell 4 by grid line, thereby controls the conducting of thin film transistor (TFT) and close.
Array base palte 1 also comprises many data lines and multiple thin film transistor (TFT) (attached not shown), and the source electrode of each thin film transistor (TFT) is connected with a data line, and its drain electrode is connected with the electrode in a pixel cell 4.Like this, in the time that thin film transistor (TFT) is opened, data line signal drives pixel cell 4 by the data line corresponding with it, controls the deflection of liquid crystal molecule, and then realizes the demonstration of different GTGs.
Preferably, as shown in Figure 4, described gate driver circuit comprises shifting deposit unit and output buffer cell, the input end of described shifting deposit unit is connected with clock circuit, its output terminal is connected with the input end of the shifting deposit unit of next stage gate driver circuit, the output terminal of shifting deposit unit is also connected with the input end of output buffer cell, and the output terminal of output buffer cell connects a line display unit.
Embodiment 2:
The present embodiment provides a kind of display panel, and display panel comprises the array base palte 1 in embodiment 1, certainly also should comprise that other,, as known structures such as driving circuits, are no longer described in detail at this.
The present embodiment also provides a kind of display device, and display device comprises above-mentioned display panel, and display device also should comprise that other,, as known structures such as backlight modules, are no longer described in detail at this certainly.
Display device in the present embodiment is liquid crystal indicator.In addition, display device can also be: any product or parts with Presentation Function such as Electronic Paper, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
The display device of the present embodiment comprises above-mentioned display panel, and therefore, the width of the frame of display device is narrower, and outward appearance is more attractive in appearance.
Be understandable that, above embodiment is only used to principle of the present utility model is described and the illustrative embodiments that adopts, but the utility model is not limited to this.For those skilled in the art, in the situation that not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection domain of the present utility model.
Claims (10)
1. an array base palte, comprising: viewing area and non-display area, and described non-display area comprises at least one row gate driver circuit; It is characterized in that,
On column direction, the size of described at least one row gate driver circuit is greater than the size of described viewing area.
2. array base palte according to claim 1, is characterized in that, at least one end of described at least one row gate driver circuit exceeds described viewing area.
3. array base palte according to claim 2, is characterized in that, each two ends that are listed as described gate driver circuit all exceeds viewing area, and exceeds the measure-alike of viewing area.
4. array base palte according to claim 1, is characterized in that,
Described array base palte comprises first row gate driver circuit and secondary series gate driver circuit, outside the described first row gate driver circuit both sides of being located at viewing area relative to secondary series gate driver circuit;
The two ends of the two ends of described first row gate driver circuit and described secondary series gate driver circuit are totally four ends, in described four ends, have at least one end to exceed viewing area.
5. array base palte according to claim 4, is characterized in that, described four ends all exceed viewing area, and exceeds the measure-alike of viewing area.
6. array base palte according to claim 1, it is characterized in that, described array base palte also comprises many data lines and multiple thin film transistor (TFT), and the source electrode of each thin film transistor (TFT) is connected with a described data line, and its drain electrode is connected with the electrode in a described pixel cell.
7. array base palte according to claim 1, is characterized in that,
Described viewing area comprises multirow pixel cell;
The each described gate driver circuit of the described gate driver circuit of every row and one-row pixels unit correspondence;
Described array base palte also comprises many grid lines, every the corresponding one-row pixels of grid line unit, and the each gate driver circuit in every row gate driver circuit connects a grid line.
8. according to the array base palte described in claim 1 to 7 any one, it is characterized in that, described gate driver circuit comprises shifting deposit unit and output buffer cell, the input end of described shifting deposit unit is connected with clock circuit, its output terminal is connected with the input end of the shifting deposit unit of next stage gate driver circuit, the output terminal of shifting deposit unit is also connected with the input end of output buffer cell, and the output terminal of output buffer cell connects a line display unit.
9. a display panel, is characterized in that, described display panel comprises the array base palte as described in claim 1 to 8 any one.
10. a display device, is characterized in that, described display device comprises display panel as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420135253.5U CN203733452U (en) | 2014-03-24 | 2014-03-24 | Array substrate, display panel and display apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420135253.5U CN203733452U (en) | 2014-03-24 | 2014-03-24 | Array substrate, display panel and display apparatus |
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| Publication Number | Publication Date |
|---|---|
| CN203733452U true CN203733452U (en) | 2014-07-23 |
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| CN201420135253.5U Expired - Lifetime CN203733452U (en) | 2014-03-24 | 2014-03-24 | Array substrate, display panel and display apparatus |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020147479A1 (en) * | 2019-01-17 | 2020-07-23 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display device |
| CN113140175A (en) * | 2021-04-07 | 2021-07-20 | 武汉华星光电技术有限公司 | Display panel and display device |
| CN114550670A (en) * | 2022-03-02 | 2022-05-27 | 广州华星光电半导体显示技术有限公司 | Display panel |
-
2014
- 2014-03-24 CN CN201420135253.5U patent/CN203733452U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020147479A1 (en) * | 2019-01-17 | 2020-07-23 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display device |
| US11467456B2 (en) | 2019-01-17 | 2022-10-11 | Chongqing Boe Optoelectronics Technology Co., Ltd. | Array substrate, display panel and display apparatus |
| CN113140175A (en) * | 2021-04-07 | 2021-07-20 | 武汉华星光电技术有限公司 | Display panel and display device |
| CN113140175B (en) * | 2021-04-07 | 2023-04-07 | 武汉华星光电技术有限公司 | Display panel and display device |
| CN114550670A (en) * | 2022-03-02 | 2022-05-27 | 广州华星光电半导体显示技术有限公司 | Display panel |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
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Granted publication date: 20140723 |
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| CX01 | Expiry of patent term |