CN203720560U - Hardware-in-loop simulation test card for motor - Google Patents
Hardware-in-loop simulation test card for motor Download PDFInfo
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- CN203720560U CN203720560U CN201320774696.4U CN201320774696U CN203720560U CN 203720560 U CN203720560 U CN 203720560U CN 201320774696 U CN201320774696 U CN 201320774696U CN 203720560 U CN203720560 U CN 203720560U
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- 238000012360 testing method Methods 0.000 title claims abstract description 31
- 238000004088 simulation Methods 0.000 title claims abstract description 9
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 5
- 238000011161 development Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000013178 mathematical model Methods 0.000 description 2
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Abstract
The utility model discloses a hardware-in-loop simulation test card for a motor, and the test card comprises a field programmable gate array chip, a digital I/O interface device, analog input/output devices, an analog encoder output device, a bus interface device, an IO interface device, an IO carrier plate interface, a user signal interface, and a bus interface. The digital I/O interface device is connected with the field programmable gate array chip, the IO carrier plate interface, and the user signal interface. The analog input device is connected with the field programmable gate array chip and the user signal interface. The analog output device is connected with the field programmable gate array chip and the user signal interface. The analog encoder output device is connected with the field programmable gate array chip and the user signal interface. The bus interface device is connected with the field programmable gate array chip and the bus interface. The test card provided by the utility model can enable a developer for a motor algorithm not to use a debugging algorithm of a rear motor, thereby reducing the danger in a process of debugging, and improving the efficiency.
Description
Technical field
The utility model relates to Real-time Simulation Technology field, more particularly, relates to a kind of motor hardware-in-the-loop test card.
Background technology
At present, exploitation Electric Machine Control product often adopts traditional development scheme, utilizes real controller to control real inverter, motor and load.Yet motor body is a typical non-linear and strongly coupled system, and rotor may be High Rotation Speed, also possibility bringing onto load, realize the control of safety and steady and be not easy, and the electronic power switch device in inverter need to be considered dead band and switching frequency.What in control, proportional integral parameter arranged is unreasonable, and the improper setting of inverter switching frequency and Dead Time all likely causes controlled device in the hole, and damage equipment, even can hurt people.
Utility model content
In view of this, the utility model provides a kind of motor hardware-in-the-loop test card, by with real-time simulation machine system compatible, by the algorithm of the mathematical models such as parallel running motor body, inverter, load and scrambler, the systems such as motor body, inverter are carried out to emulation, make motor algorithm development person can avoid using true motor debugging algorithm, reduce the danger in debug process and improved efficiency.
For solving the problems of the technologies described above, the technical solution adopted in the utility model is: a kind of motor hardware-in-the-loop test card, comprising: field programmable gate array chip, digital I/O interface arrangement, analogue input unit, analogue output unit, analog encoder output unit, bus interface devices, IO support plate interface, subscriber signal interface and bus interface; Wherein:
Described digital I/O interface arrangement is connected with subscriber signal interface with described field programmable gate array chip, IO support plate interface respectively;
Described analogue input unit is connected with subscriber signal interface with described field programmable gate array chip respectively;
Described analogue output unit is connected with subscriber signal interface with described field programmable gate array chip respectively;
Described analog encoder output unit is connected with subscriber signal interface with described field programmable gate array chip respectively;
Described bus interface devices is connected with bus interface with described field programmable gate array chip.
Preferably, described bus interface devices comprises bridging chip.
Preferably, described digital I/O interface arrangement comprises signal condition chip.
Preferably, described analogue input unit comprises 14 bit resolution modulus signal conversion chips.
Preferably, described analogue output unit comprises 16 bit resolution digital and analogue signals conversion chips.
From above-mentioned technical scheme, can find out, the disclosed a kind of motor hardware-in-the-loop test card of the utility model, by utilizing the powerful concurrent operation function of field programmable gate array chip, and be equipped with digital I/O interface arrangement, analogue input unit, analogue output unit, analog encoder output unit and bus interface devices, characteristic that can the actual controlled device of real time modelling is tested, and has reduced dangerous in debug process and has improved efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the structural representation of the disclosed a kind of motor hardware-in-the-loop test card of the utility model.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only a part of embodiment of the present utility model, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
The utility model embodiment discloses a kind of motor hardware-in-the-loop test card, by with real-time simulation machine system compatible, by the algorithm of the mathematical models such as parallel running motor body, inverter, load and scrambler, the systems such as motor body, inverter are carried out to emulation, make motor algorithm development person can avoid using true motor debugging algorithm, reduce the danger in debug process and improved efficiency.
As shown in Figure 1, a motor hardware-in-the-loop test card, comprising: field programmable gate array chip, digital I/O interface arrangement, analogue input unit, analogue output unit, analog encoder output unit, bus interface devices, IO support plate interface, subscriber signal interface and bus interface; Wherein:
Numeral I/O interface arrangement is connected with subscriber signal interface with field programmable gate array chip, IO support plate interface respectively;
Analogue input unit is connected with subscriber signal interface with field programmable gate array chip respectively;
Analogue output unit is connected with subscriber signal interface with field programmable gate array chip respectively;
Analog encoder output unit is connected with subscriber signal interface with field programmable gate array chip respectively;
Bus interface devices is connected with bus interface with field programmable gate array chip.
Wherein, the core of above-mentioned bus interface devices is bus interface bridge chip, is responsible for bus timing logical transition.Above-mentioned bus interface essence is hardware connector.Above-mentioned IO support plate interface refers to that test card has the ability of expansion, i.e. reserved interface.Above-mentioned subscriber signal interface refers to the user of test card, i.e. Emulation of Electrical Machinery user's interface, for the input and output between Emulation of Electrical Machinery user and test card.
The disclosed motor hardware-in-the-loop test of the utility model card, field programmable gate array chip is as the host processor chip of emulation testing card, and host processor chip provides a large amount of programmable logic resource and multiplier arithmetic element for moving complicated model algorithm.The utility model adopts bus interface devices and bus interface and real-time simulation machine system to realize seamless link.Because the core of this emulation testing card is field programmable gate array chip, be adapted to multiple bus interface exploitation, all core datas are processed by field programmable gate array chip, therefore for different host computers, can develop different bus interface, for realize host computer to the control of emulation testing card and host computer the acquisition monitoring to all data.
The communication modes of this emulation testing card and host computer can have multiple, common as cPCI, USB etc.Bus interface devices can adopt PCI9030, as bridging chip, cPCI bus is changed to Local Bus, realizes the data interaction of field programmable gate array chip and cPCI bus.Therefore, the real-time simulation machine system model data in monitoring site programmable gate array chip in real time.
Integrated multipath high-speed numeral I/O in digital I/O interface arrangement in this emulation testing card, the 3.3V numeral I/O signal of field programmable gate array chip is by special signal conditioning chip, as signal condition chip SN74ABT541, convert the 5V signal of standard to, by subscriber signal interface and I/O support plate interface, input or output digital signal.Analogue input unit and analogue output unit are respectively by 14 bit resolution modulus signal conversion chips, as modulus signal conversion chip AD7357, with 16 bit resolution digital and analogue signals conversion chips, as digital and analogue signals conversion chip DAC8811, thereby adopt SPI mouth to set up to communicate by letter with field programmable gate array chip, realize collection and the output of simulating signal.Wherein, the digital I/O of part, analog input and simulation output are analog encoder output unit by secondary development, for increment/Hall/revolve changes/sinusoidal coder signal to export.
The disclosed field programmable gate array chip of the utility model can to DIO AD the signal such as DA encapsulate, for user's Electric Machine Control algorithm provides enough signaling interfaces: the output of threephase stator electric current, scrambler output, PWM input etc.Wherein, the output of threephase stator electric current is the DA output of use, scrambler IO and two kinds of outputs of DA, and wherein incremental encoder, Hall element are the IO output of use, rotary transformer Yong Liao mono-road AD input He Yi road DA output, PWM is IO input.These signals are all the conventional signals of Electric Machine Control, and in test card, field programmable gate array chip can be compatible.User can observe test data by upper computer software, the online ginseng of adjusting, thus check and system optimizing control, adapted to the interface signal demand of multiple electric machine controller.
Plant model development process is started by Simulink modeling.Adopt in Simulink module library and support the module modeling that HDL code generates, the interface module that the interface of required input/output/pilot signal can directly call in motor HIL module library is configured.By configuration interface module, signal can peripheral satellite interface or bus communication port association automatic and emulation testing card get up.When the interface configuration of Simulink modeling and I/O/pilot signal all finishes, use with the matching used key download software HAC of the utility model and just all model conversion can be become to HDL code compilation, download and move.
In this instructions, each embodiment adopts the mode of going forward one by one to describe, and each embodiment stresses is the difference with other embodiment, between each embodiment identical similar part mutually referring to.
Above-mentioned explanation to the disclosed embodiments, makes professional and technical personnel in the field can realize or use the utility model.To the multiple modification of these embodiment, will be apparent for those skilled in the art, General Principle as defined herein can, in the situation that not departing from spirit or scope of the present utility model, realize in other embodiments.Therefore, the utility model will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (6)
1. a motor hardware-in-the-loop test card, it is characterized in that, comprising: field programmable gate array chip, digital I/O interface arrangement, analogue input unit, analogue output unit, analog encoder output unit, bus interface devices, IO support plate interface, subscriber signal interface and bus interface; Wherein:
Described digital I/O interface arrangement is connected with subscriber signal interface with described field programmable gate array chip, IO support plate interface respectively;
Described analogue input unit is connected with subscriber signal interface with described field programmable gate array chip respectively;
Described analogue output unit is connected with subscriber signal interface with described field programmable gate array chip respectively;
Described analog encoder output unit is connected with subscriber signal interface with described field programmable gate array chip respectively;
Described bus interface devices is connected with bus interface with described field programmable gate array chip, and described bus interface is the interface of described motor hardware-in-the-loop test card and real-time simulation machine system.
2. motor hardware-in-the-loop test card according to claim 1, is characterized in that, described bus interface devices comprises bridging chip.
3. motor hardware-in-the-loop test card according to claim 1, is characterized in that, described digital I/O interface arrangement comprises signal condition chip.
4. motor hardware-in-the-loop test card according to claim 1, is characterized in that, described analogue input unit comprises 14 bit resolution modulus signal conversion chips.
5. motor hardware-in-the-loop test card according to claim 1, is characterized in that, described analogue output unit comprises 16 bit resolution digital and analogue signals conversion chips.
6. motor hardware-in-the-loop test card according to claim 1, is characterized in that, integrated high speed digital I/O in described digital I/O interface arrangement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320774696.4U CN203720560U (en) | 2013-11-29 | 2013-11-29 | Hardware-in-loop simulation test card for motor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320774696.4U CN203720560U (en) | 2013-11-29 | 2013-11-29 | Hardware-in-loop simulation test card for motor |
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| CN203720560U true CN203720560U (en) | 2014-07-16 |
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| CN201320774696.4U Expired - Lifetime CN203720560U (en) | 2013-11-29 | 2013-11-29 | Hardware-in-loop simulation test card for motor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104158460A (en) * | 2014-08-15 | 2014-11-19 | 深圳大学 | Semi-physical motor control simulation method and semi-physical motor control simulation system |
| CN104765616A (en) * | 2015-04-29 | 2015-07-08 | 北京经纬恒润科技有限公司 | Method and system for generating IO model automatically |
| CN114489003A (en) * | 2021-12-31 | 2022-05-13 | 上海科梁信息科技股份有限公司 | Motor controller testing device and testing method, and computer-readable storage medium |
-
2013
- 2013-11-29 CN CN201320774696.4U patent/CN203720560U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104158460A (en) * | 2014-08-15 | 2014-11-19 | 深圳大学 | Semi-physical motor control simulation method and semi-physical motor control simulation system |
| CN104765616A (en) * | 2015-04-29 | 2015-07-08 | 北京经纬恒润科技有限公司 | Method and system for generating IO model automatically |
| CN104765616B (en) * | 2015-04-29 | 2018-04-20 | 北京经纬恒润科技有限公司 | A kind of method and system for automatically generating I/O model |
| CN114489003A (en) * | 2021-12-31 | 2022-05-13 | 上海科梁信息科技股份有限公司 | Motor controller testing device and testing method, and computer-readable storage medium |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 4 / F, building 1, No.14 Jiuxianqiao Road, Chaoyang District, Beijing 100020 Patentee after: Beijing Jingwei Hirain Technologies Co.,Inc. Address before: 100101 Beijing city Chaoyang District Anxiang Beili 11 B block 8 layer Patentee before: Beijing Jingwei HiRain Technologies Co.,Ltd. |
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| CP03 | Change of name, title or address | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140716 |
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| CX01 | Expiry of patent term |