CN203563055U - Novel automatic zero-setting circuit - Google Patents
Novel automatic zero-setting circuit Download PDFInfo
- Publication number
- CN203563055U CN203563055U CN201320727229.6U CN201320727229U CN203563055U CN 203563055 U CN203563055 U CN 203563055U CN 201320727229 U CN201320727229 U CN 201320727229U CN 203563055 U CN203563055 U CN 203563055U
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- comparator
- digital potentiometer
- operational amplifier
- circuit
- zero
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Abstract
The utility model relates to a novel automatic zero-setting circuit, wherein a summing circuit is composed of an R1, an R2, an R3 and an operational amplifier (5). The output end of a comparator (4) is connected with the U/D end of a digital potentiometer (1). The input end of the comparator (4) is connected with the Vout of the operational amplifier (5), and the other end of the comparator (4) is grounded. The CS end of the digital potentiometer (1) is connected with a switch (3). The CLK end of the digital potentiometer (1) is connected with an oscillator (2), and the V0 end of the digital potentiometer (1) is connected with the R3 of the summing circuit. The VH end of the digital potentiometer (1) is connected with the positive electrode of a power supply, and the VL end of the digital potentiometer (1) is connected with the negative electrode of the power supply. The R2 and the R3 are connected in parallel. The output end of the operational amplifier (5) is connected with the comparator (4). According to the technical scheme of the utility model, by means of the novel automatic zero-setting circuit, the functions of monitoring in real time and adjusting the zero drift can be realized, so that the authenticity and the validity of test data are greatly improved. Meanwhile, the fussy zero adjustment is free from being manually operated. In the aspects of real-time monitoring and adjustment, operators can conveniently and really know the running condition.
Description
Technical field
The present invention relates to electronic information field, be specifically related to a kind of novel automatic zero set circuit.
Background technology
At present, in scientific research and testing, need to use various kinds of sensors, in the process of test data, the phenomenon of zero drift often can occur, cause the data of test to occur deviation, have influence on the authenticity of test.Be mainly manifested in:
One, zero drift is not pointed out, and affects data validity.
There is no the prompting of zero drift, easily cause man-made failure operation, can not correct in time and correct.
Two, complex operation, is inconvenient to operate.
In the process of hand reset, often need first to remember the data value of null offset, and then open zeroing interface, data value is before inserted, get back to data acquisition interface, reexamine zero point, can start data acquisition.But after sometimes having detected zero point, also have trickle Zero change, need the operation of returning to zero again, so zeroing process is somewhat loaded down with trivial details.
Three, the effective means that lacks monitoring in real time and adjust.
Summary of the invention
Object of the present invention is exactly for needing to use various kinds of sensors in current scientific research and testing; in the process of test data, often can there is the phenomenon of zero drift, cause the data of test to occur deviation; have influence on the above-mentioned deficiency of authenticity of test, and a kind of novel automatic zero set circuit is provided.
The present invention is by executive circuit, add circuit, form with comparator, executive circuit is by digital regulation resistance, oscillator and switch form, add circuit is by R1, R2, R3 and operational amplifier form, the output of comparator is received the U/D end of digital regulation resistance, the Vout of the input termination operational amplifier of comparator, other end ground connection, the CS end of digital regulation resistance is connected with switch, CLK end is connected with oscillator, V0 end joins with the R3 of add circuit, VH end connects the positive level of power supply, VL end connects power-level, R2 and R3 are in parallel, the output of operational amplifier is connected with comparator.
Advantage of the present invention is: can Real-Time Monitoring and adjust null offset, increase substantially authenticity and the validity of test data, and avoid adjust loaded down with trivial details manual zero point simultaneously.Aspect monitoring and adjustment in real time, convenient operation personnel understand ruuning situation really.
accompanying drawing explanation
Fig. 1 is structural representation of the present invention.
Embodiment
As shown in Figure 1, the present invention is by executive circuit, add circuit, form with comparator 4, executive circuit is by digital regulation resistance 1, oscillator 2 and switch 3 form, add circuit is by R1, R2, R3 and operational amplifier 5 form, the output of comparator 4 is received the U/D end of digital regulation resistance 1, the Vout of the input termination operational amplifier 5 of comparator 4, other end ground connection, the CS end of digital regulation resistance 1 is connected with switch 3, CLK end is connected with oscillator 2, V0 end joins with the R3 of add circuit, VH end connects the positive level of power supply, VL end connects power-level, R2 and R3 are in parallel, the output of operational amplifier 5 is connected with comparator 4.
Operation principle is as follows:
When the output of amplifier is not no-voltage, the output of comparator is just high or low level, the U/D end of digital regulation resistance is equivalent to the cursor slide end of common potentiometer, upward sliding during high level, down sliding during low level, causes the output Vo of digital regulation resistance to change, press the button S, CS end is low level, and circuit is selected starts working, amplifier output Vout automatic balancing.Digital regulation resistance has maintenance function, unless again press S button, Vo voltage is constant, has realized automatic zero set.
Claims (1)
1. a novel automatic zero set circuit, it is characterized in that it is by executive circuit, add circuit, and comparator (4) forms, executive circuit is by digital regulation resistance (1), oscillator (2) and switch (3) form, add circuit is by R1, R2, R3 and operational amplifier (5) form, the output of comparator (4) is received the U/D end of digital regulation resistance (1), the Vout of the input termination operational amplifier (5) of comparator (4), other end ground connection, the CS end of digital regulation resistance (1) is connected with switch (3), CLK end is connected with oscillator (2), V0 end joins with the R3 of add circuit, VH end connects the positive level of power supply, VL end connects power-level, R2 and R3 are in parallel, the output of operational amplifier (5) is connected with comparator (4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320727229.6U CN203563055U (en) | 2013-11-18 | 2013-11-18 | Novel automatic zero-setting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320727229.6U CN203563055U (en) | 2013-11-18 | 2013-11-18 | Novel automatic zero-setting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203563055U true CN203563055U (en) | 2014-04-23 |
Family
ID=50512750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320727229.6U Withdrawn - After Issue CN203563055U (en) | 2013-11-18 | 2013-11-18 | Novel automatic zero-setting circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203563055U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103840828A (en) * | 2013-11-18 | 2014-06-04 | 中国特种飞行器研究所 | Novel automatic zeroing circuit |
-
2013
- 2013-11-18 CN CN201320727229.6U patent/CN203563055U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103840828A (en) * | 2013-11-18 | 2014-06-04 | 中国特种飞行器研究所 | Novel automatic zeroing circuit |
| CN103840828B (en) * | 2013-11-18 | 2016-08-03 | 中国特种飞行器研究所 | A kind of automatic zero set circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20140423 Effective date of abandoning: 20160803 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |