CN203563054U - Clock synchronizing system - Google Patents
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- CN203563054U CN203563054U CN201320414485.XU CN201320414485U CN203563054U CN 203563054 U CN203563054 U CN 203563054U CN 201320414485 U CN201320414485 U CN 201320414485U CN 203563054 U CN203563054 U CN 203563054U
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Abstract
The utility model provides a clock synchronizing system, applied in a multimode redundant system. The multimode redundant system comprises at least two independent synchronization modules, and each synchronization module comprises a clock synchronizing system. The clock synchronizing system comprises a two-out of three functional device, a first all-digital phase-locked loop connected with the two-out of three functional device, a synchronous counter connected with the first all-digital phase-locked loop, a first Manchester encoder connected with the first all-digital phase-locked loop and the synchronous counter, a processor connected with the two-out of three functional device, and a synchronous determining device connected with the processor and the synchronous counter. The system realizes counting clock signal synchronization of all clock synchronizing systems and clock synchronization of all synchronization modules in the multimode redundant system.
Description
Technical field
The application relates to clock synchronous field, particularly a kind of clock system.
Background technology
Triple-modular redundancy system comprises three synchronization modules, and these three synchronization modules have same structure, and three synchronization modules are independent mutually, because two synchronization modules occur that wrong probability is very little simultaneously, therefore can greatly improve the credibility of system.Simultaneously, for ensureing the reliability of each synchronization module, guarantee to process in time primary fault, system also has fault-detecting ability, and periodicity or when needed detection failure are found can locate in time after fault, carry out troubleshooting, reduce secondary failure probability of happening, therefore, triple-modular redundancy system is the redundant system structure of a high reliability and high security.
Wherein three synchronization modules in triple-modular redundancy system can be three identical parts or three identical computers.The core of triple-modular redundancy system is the synchronous operation of three synchronization modules, and the core of the synchronous operation of three synchronization modules is clock synchronous of three synchronization modules.
Technology while realizing at present the clock alignment school that the clock synchronous of three synchronization modules can be by software protocol, but during clock alignment school by software protocol, to realize the clock synchronous of three synchronization modules be software synchronization mode to technology, and error is large, therefore still there is not at present a kind of method of synchronization that realizes three synchronization module clock synchronous in triple-modular redundancy system by hardware.
Utility model content
For solving the problems of the technologies described above, the embodiment of the present application provides a kind of clock system, to reach the object of the clock synchronous of all synchronization modules in the synchronous and multimode redundant system of counting clock signal of all clock systems in multimode redundant system, technical scheme is as follows:
A kind of clock system, is applied to multimode redundant system, and described multimode redundant system comprises at least two separate synchronization modules, and each described synchronization module comprises a described clock system, and described clock system comprises:
For extracting a clock signal from each clock system clock signal separately, as three of feedback clock signal, get two effectors;
Get two effectors and be connected with described three, be used for receiving input clock signal, described input clock signal is processed and generated counting clock signal, state transition clock signal, sampled clock signal and the clock signal that is 90 degree with described counting clock signal phase difference, and follow the tracks of described feedback clock signal, until the cycle of described counting clock signal and described feedback clock signal is identical, phase difference keeps changeless the first all-digital phase-locked loop, when the phase difference of described counting clock signal and described feedback clock signal keeps immobilizing, described all-digital phase-locked loop in described multimode redundant system in all clock systems generates identical counting clock signal,
Be connected with described the first all-digital phase-locked loop, for calculating the number of described counting clock signal same type hopping edge, generate the coincidence counter of synchronometer numerical value;
Be connected with described the first all-digital phase-locked loop, described coincidence counter, for the state value according to described synchronometer numerical value, described state transition clock signal, described sampled clock signal and described clock system, generate synchronization output signal, wherein said state value is used for the first manchester encoder of the operation order of describing described clock system;
Get two effectors and be connected with described three, for obtaining the synchronization output signal of other each clock systems, respectively the synchronization output signal of other each clock systems is resolved, obtain the each self-corresponding counting clock signal of other each synchronization output signals, the processor with the each self-corresponding counting clock signal phase difference of described other each synchronization output signals be 90 degree clock signal, synchronometer numerical value and state value;
Be connected with described processor, described coincidence counter, for the synchronometer numerical value to same clock system and state value combination, generate each clock system synchronometer numerical value to be judged separately, from synchronometer numerical value to be judged described in all, extract the synchronous determining device of a synchronometer numerical value as the current synchronometer numerical value of each clock system.
Preferably, described processor comprises:
Be used for the synchronization output signal of a clock system that obtains other each clock systems, and resolve this synchronization output signal, obtain clock signal, the counting clock signal of the clock system that this synchronization output signal is corresponding, the clock signal of clock system corresponding this synchronization output signal is sent to described three the second all-digital phase-locked loops of getting two effectors;
Be connected with described the second all-digital phase-locked loop, for receiving the synchronization output signal of described the second all-digital phase-locked loop parsing and the counting clock signal that described the second all-digital phase-locked loop obtains, according to this synchronization output signal and this counting clock signal, extract clock system synchronometer numerical value and the state value that this synchronization output signal is corresponding, and send this synchronometer numerical value and extremely the second manchester decoder device of described synchronous determining device of this state value;
Wherein, the number of described the second all-digital phase-locked loop and described the second manchester decoder device is that in described multimode redundant system, total number of clock system subtracts 1.
Preferably, described the first all-digital phase-locked loop comprises:
For calculating the counting clock signal of described digital vco transmission and the phase difference of described feedback clock signal, and generate the phase discriminator of the phase signal that described phase difference is corresponding;
Be connected with described phase discriminator, the described phase signal sending for receiving described phase discriminator, and the digital rings mode filter of the generation pulse signal corresponding with described phase signal;
With described phase discriminator, described digital rings mode filter is connected, be used for receiving input clock signal, input clock signal is carried out to frequency division and obtain counting clock signal, state transition signal, sampled clock signal and the clock signal that is 90 degree with described counting clock signal phase difference, and receive the described pulse signal that described digital rings mode filter sends, according to described pulse signal and described input clock signal, adjust the phase place of described counting clock signal, until the difference of the phase place of described counting clock signal and the phase place of described feedback clock signal keeps changeless digital vco.
Preferably, described synchronometer numerical value and the described state value of the clock system that described the first manchester encoder is positioned at described the first manchester encoder respectively specifically for use pseudo random sequence are encrypted, and according to state value, described state transition clock signal and described sampled clock signal after synchronometer numerical value, encryption after encrypting, generate synchronization output signal;
Further, described the first manchester encoder is also for storing the synchronometer numerical value of the described clock system that described the first manchester encoder is positioned at, and the synchronometer numerical value of storage is carried out to cyclic redundancy check (CRC) computing, generation cycle redundancy check code, and described cyclic redundancy check (CRC) code is sent to other each clock systems;
Whether the described cyclic redundancy check (CRC) code that described processor sends specifically for receiving other each clock systems the first manchester encoder is separately correct to verify the each self-corresponding synchronometer numerical value of other each clock systems that obtain.
Preferably, described synchronous determining device comprises:
For the synchronometer numerical value to same clock system and state value combination, generate the combiner of each clock system synchronometer numerical value to be judged separately;
Be connected with described combiner, for being chosen the synchronometer numerical value to be judged of numerical value maximum as the comparator of synchronometer numerical value current to be judged from need to be judged synchronometer numerical value;
Be connected with described comparator, for extracting synchronometer numerical value from described current synchronometer numerical value to be judged, and the extractor of the current synchronometer numerical value using the synchronometer numerical value extracting as each clock system.
Preferably, described multimode redundant system comprises three separate synchronization modules, described three get two effectors comprises the first port and the second port, described the first port and described the second port receive the clock signal of other each clock systems separately, and described the first port and described the second port only receive the clock signal of a clock system;
Described three get two effectors specifically for when the first port receives clock signal, and the clock signal that extraction the first port receives is as feedback clock signal; When the first port does not receive clock signal, and the second port is while receiving clock signal, extracts clock signal that the second port receives as feedback clock signal; When the first port and the second port do not receive clock signal, using described three clock signals of getting the clock system that two effectors are positioned at as feedback clock signal.
Preferably, described counting clock signal absolute value identical with described state transition clock signal frequency, phase difference is 180 degree;
The corresponding described state transition signal high level centre position of rising edge or the low level centre position of described sampled clock signal.
Compared with prior art, the application's beneficial effect is:
The application provides a kind of clock system that is applied to multimode redundant system, can realize the clock synchronous of at least two synchronization modules in multimode redundant system.In clock system, the first all-digital phase-locked loop receives input clock signal, described input clock signal is processed and generated counting clock signal, state transition clock signal and sampled clock signal, and follow the tracks of three and get the feedback clock signal identical with the counting clock signal cycle that two effectors extract from other clock systems, until the phase difference of described counting clock signal and described feedback clock signal keeps immobilizing.When the phase difference of described counting clock signal and described feedback clock signal keeps immobilizing, the counting clock signal that the described all-digital phase-locked loop in multimode redundant system in all clock systems generates is identical.Therefore, in multimode redundant system, the counting clock signal of all clock systems is realized synchronous.
Simultaneously, synchronometer numerical value and the state value combination of synchronous determining device to same clock system, generate each clock system synchronometer numerical value to be judged separately, from synchronometer numerical value to be judged described in all, extract the current synchronometer numerical value of a synchronometer numerical value as each clock system, make the synchronometer numerical value of each clock system in multimode redundant system identical, can realize the clock synchronous of all synchronization modules in multimode redundant system.
Further, in this application, it is synchronous that all clock systems are realized counting clock signal, and synchronometer numerical value is identical, make all clock systems to obtain identical synchronometer numerical value in the same moment, realized all synchronization module high precision clocks synchronous.In all clock system runnings, even if all clock systems obtain the asynchronism(-nization) of identical synchronometer numerical value, but it is very short that the counting clock signal of all clock systems synchronously makes all clock systems obtain time interval of identical synchronometer numerical value, thereby realize the clock synchronous that in redundant system, all synchronization module errors are little, precision is high.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present application, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiment of the application, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is a kind of structural representation of a kind of clock system of providing of the application;
Fig. 2 is the waveform schematic diagram of each clock signal of the first all-digital phase-locked loop generation;
Fig. 3 is a kind of structural representation of a kind of the first all-digital phase-locked loop of providing of the application;
Fig. 4 is a kind of waveform schematic diagram of phase signal;
Fig. 5 is the another kind of waveform schematic diagram of phase signal;
Fig. 6 is another waveform schematic diagram of phase signal;
Fig. 7 is a kind of waveform schematic diagram of synchronization output signal;
Fig. 8 is structure and the course of work schematic diagram of the clock system in triple-modular redundancy system;
The schematic diagram of three synchronization module data interactions in Fig. 9 triple-modular redundancy system;
Figure 10 is a kind of structural representation of triple-modular redundancy system.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment is only the application's part embodiment, rather than whole embodiment.Based on the embodiment in the application, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the application's protection.
An embodiment
The clock system that the application provides is applied in multimode redundant system, and this multimode redundant system comprises at least two separate synchronization modules, and each synchronization module comprises a clock system, now as an example of a clock system example, is introduced.
Refer to Fig. 1, a kind of structural representation that it shows a kind of clock system that the application provides, comprising: three get two effectors 101, the first all-digital phase-locked loop 102, coincidence counter 103, the first manchester encoder 104, processor 105 and synchronous determining device 106.
Three get two effectors 101, for extracting a clock signal as feedback clock signal from each clock system clock signal separately.
In the present embodiment, three get two effectors 101 has multiple ports, the number of port is that the number of clock system in multimode redundant system subtracts 1, and each port is corresponding one by one with the clock signal in three clock systems of getting the clock system at two effector 101 places.For example, multimode redundant system comprises three separate synchronization modules, the clock system that three modules comprise is respectively clock system A, clock system B and clock system C, being positioned at three of clock system A gets two effectors 101 and has two ports, be respectively port one, port 2, the wherein corresponding clock system B of port one, for the clock signal of receive clock synchro system B, the corresponding clock system C of port 2, for the clock signal of receive clock synchro system C.
In the present embodiment, if three get two effectors 101 and there is n port, be respectively port one, port 2 ... port n-1, port n.Three get two effectors 101 extracts a clock signal and as the process of feedback clock signal can be from each clock system clock signal separately: check whether port one receives clock signal, if have, using the clock signal of port one as feedback clock signal, if nothing, check whether port 2 receives clock signal, if have, using the clock signal of port 2 as feedback clock signal, if nothing, check whether port 3 receives clock signal, ... check whether port n-1 receives clock signal, if have, using the clock signal of port n-1 as feedback clock signal, if nothing, check whether port n receives clock signal, if have, using the clock signal of port n as feedback clock signal, if nothing, using three clock signals of clock system of getting two effector 101 places as feedback clock signal.
Still using multimode redundant system, comprise that three clock systems get two effectors 101 as example to three and from each clock system clock signal separately, extract a clock signal and describe as feedback clock signal.Three clock systems that multimode redundant system comprises are respectively A, B and C, three to get two effector 101 place clock systems be clock system A, three get two effectors 101 comprises the first port and the second port, the corresponding clock system B of the first port, the corresponding clock system C of the second port, three get two effectors 101 checks whether the first port receives clock signal, if receive, using the clock signal of clock system B as feedback clock signal, if do not receive, check whether the second port receives clock signal, if receive, using the clock signal of clock system C as feedback clock signal, if do not receive, using the clock signal of clock system A as feedback clock signal.
The first all-digital phase-locked loop 102, be used for receiving input clock signal, described input clock signal is processed and generated counting clock signal, state transition clock signal, sampled clock signal and the clock signal that is 90 degree with described counting clock signal phase difference, and follow the tracks of described feedback clock signal, until the cycle of described counting clock signal and described feedback clock signal is identical, phase difference keeps immobilizing, when the phase difference of described counting clock signal and described feedback clock signal keeps immobilizing, described all-digital phase-locked loop in described multimode redundant system in all clock systems generates identical counting clock signal.
In the present embodiment, the counting clock signal absolute value identical with state transition clock signal frequency, phase difference that the first all-digital phase-locked loop 102 is processed generation to input clock signal is 180 degree.Rising edge corresponding states redirect clock signal high level centre position or the low level centre position of the sampled clock signal that the first all-digital phase-locked loop 102 generates, wherein, the rising edge corresponding states redirect signal high level centre position of sampled clock signal or low level centre position can guarantee stable sampling.Counting clock signal and feedback clock signal phase difference keep 90 degree to immobilize.The first all-digital phase-locked loop 102 is processed the counting clock signal, state transition clock signal, sampled clock signal that generate and can be referring to Fig. 2 with the output waveform of the described counting clock signal phase difference clock signal that is 90 degree to input clock signal, and shown in Fig. 2 is the waveform schematic diagram of each clock signal of generating of the first all-digital phase-locked loop.
In the present embodiment, the input clock signal that the first all-digital phase-locked loop 102 receives is high-frequency signal, can be set as the clock signal of 80MHZ.And the input clock signal frequency of each clock system is identical, and phase place is difference to some extent.
Wherein, the structure of the first all-digital phase-locked loop 102 can be referring to Fig. 3, shown in Fig. 3 is a kind of structural representation of a kind of the first all-digital phase-locked loop 102 of providing of the application, can comprise: phase discriminator 301, digital rings mode filter 302 and digital vco 303.Wherein:
Phase discriminator 301, for calculating the phase difference of described counting clock signal and described feedback clock signal, and generates the phase signal that described phase difference is corresponding.
Wherein, phase discriminator 301 when the phase difference of described counting clock signal and described feedback clock signal is different, the phase signal difference of generation.
At the phase difference of described counting clock signal and described feedback clock signal, be 90 while spending, as shown in Figure 4, shown in Fig. 4 is a kind of waveform schematic diagram of phase signal to the phase signal of generation.At the phase difference of described counting clock signal and described feedback clock signal, be 180 while spending, the phase signal generating as shown in Figure 5, shown in Fig. 5 is the another kind of waveform schematic diagram of phase signal, wherein in Fig. 5, phase signal is high level signal, amplitude that can this high level signal is set to 1, can certainly be set to other numerical value.When the phase difference of described counting clock signal and described feedback clock signal is 0 while spending, the phase signal generating as shown in Figure 6, shown in Fig. 6 is another waveform schematic diagram of phase signal, wherein in Fig. 6, phase signal is low level signal, amplitude that can this low level signal is set to 0, can certainly be set to other numerical value.
Wherein, when the phase difference of described counting clock signal and described feedback clock signal keeps immobilizing, the phase difference of described counting clock signal and described feedback clock signal is 90 degree.Therefore, phase discriminator 301 is 90 while spending at the phase difference that calculates described counting clock signal and described feedback clock signal, and the phase signal of generation is invalid signals, can't work by triggered digital loop filter 302.The described counting clock signal that phase discriminator 301 only calculates and the phase difference of described feedback clock signal are not 90 while spending, and the phase signal of generation is just useful signal, and triggered digital loop filter 302 carries out work.
Digital rings mode filter 302, the phase signal sending for receiving phase discriminator 301, and the generation pulse signal corresponding with described phase signal.
In the present embodiment, if it is to be greater than 90 in the phase place of feedback clock signal than the phase place of counting clock signal to be obtained by phase discriminator 301 while spending that digital rings mode filter 302 receives phase signal that phase discriminator 301 sends, digital rings mode filter 302 generates subtract pulse signal.If it is to be less than 90 in the phase place of the feedback clock signal phase place super than counting clock signal to be obtained by phase discriminator 301 while spending that digital rings mode filter 302 receives phase signal that phase discriminator 301 sends, digital rings mode filter 302 generates and adds pulse signal.
Digital vco 303, be used for receiving input clock signal, input clock signal is carried out to the clock signal that frequency division obtains counting clock signal, state transition signal, sampled clock signal and be 90 degree with described counting clock signal phase difference, and receive the pulse signal that digital rings mode filter 302 sends, according to described pulse signal and described input clock signal, adjust the phase place of described counting clock signal, until the difference of the phase place of described counting clock signal and the phase place of described feedback clock signal keeps immobilizing.
Digital vco 303 is when receiving the subtract pulse signal that digital rings mode filter 302 sends, digital vco 303 deducts a pulse signal in described input clock signal, adjust the phase place of described input clock signal, digital vco 303 receive that digital rings mode filter 302 sends add pulse signal time, digital vco 303 increases a pulse signal in described input clock signal, adjusts the phase place of described input clock signal.
Digital vco 303 carries out frequency division to the input clock signal after adjusting, obtain current counting clock signal, current state redirect signal, current sampled clock signal and the clock signal that is 90 degree with current counting clock signal phase difference, current counting clock signal is adjusted than the phase place of counting clock signal before, then digital vco 303 is sent to phase discriminator 301 by current counting clock signal, phase discriminator 301 continues the phase difference of more current counting clock signal and described feedback clock signal, and carry out corresponding operating, until the difference of the phase place of current counting clock signal and the phase place of feedback clock signal keeps immobilizing.
In the present embodiment, digital vco 303 can carry out 64 frequency divisions to input clock signal, obtains counting clock signal, state transition signal, the sampled clock signal after frequency division and the clock signal that is 90 degree with described counting clock signal phase difference.The frequency division of other multiples that certainly, digital vco 303 also can be except 64 frequency divisions.
Coincidence counter 103, for the number of count clock signal same type hopping edge, generates synchronometer numerical value.Wherein same type hopping edge can be rising edge or trailing edge.
The first manchester encoder 104, for the state value according to described synchronometer numerical value, described state transition clock signal, described sampled clock signal and described clock system, generate synchronization output signal, wherein said state value is for describing the operation order of described clock system.
In the present embodiment, synchronometer numerical value and the state value of the clock system that the first manchester encoder 104 is positioned at described the first manchester encoder respectively specifically for use pseudo random sequence are encrypted, and according to state value, state transition clock signal and sampled clock signal after synchronometer numerical value, encryption after encrypting, generate synchronization output signal.
Its detailed process that generates synchronization output signal can be: the first manchester encoder 104 combines synchronometer numerical value and the state value of the clock system at the first manchester encoder 104 places, obtain combined value, and state value is positioned at a high position in the combined value obtaining.Then use the rising edge of sampled clock signal to sample to state transition signal, data and combined value that sampling obtains carry out logical operation, generate synchronization output signal.Wherein, the state value of clock system is for describing the operation order of clock system.
If the waveform of counting clock signal, the waveform of state transition clock signal and the waveform of sampled clock signal are as shown in Figure 2, and the combined value that the first manchester encoder 101 obtains is 10101101, the wherein one-period of corresponding states redirect clock signal successively of each data in combined value 10101101, use the rising edge of sampled clock signal to sample to state transition clock signal, the data and 10101101 that sampling obtains are carried out the logical operation of XOR negate, generate synchronization output signal, as shown in Figure 7, shown in Fig. 7 is a kind of waveform schematic diagram of synchronization output signal.
The synchronization output signal of the first manchester encoder 104 not carries the state value of the clock system that synchronometer numerical value and the first manchester encoder 104 be positioned at always, when the synchronization output signal of the first manchester encoder 104 does not carry the state value of the clock system that synchronometer numerical value and the first manchester encoder 104 be positioned at, the synchronization output signal of the first manchester encoder 104 is identical with counting clock signal frequency, and phase difference is the pulse signal of 90 degree.The synchronometer numerical value of the clock system that therefore the first manchester encoder 104 is positioned at and state value at set intervals, are sent to other each clock systems.And the counting clock signal of the clock system that the first manchester encoder 104 is positioned at is always all to other each clock system transmission.
In the present embodiment, the first manchester encoder 104 can be set arbitrarily generate the cycle of the synchronization output signal that carries synchronometer numerical value and state value.
Processor 105, for obtaining the synchronization output signal of other each clock systems, respectively the synchronization output signal of other each clock systems is resolved, obtain the each self-corresponding counting clock signal of other each synchronization output signals, with the each self-corresponding counting clock signal phase difference of described other each synchronization output signals be 90 degree clock signal, synchronometer numerical value and state value.
In the present embodiment, processor 105 is obtaining after the synchronization output signal of other each clock systems, respectively the synchronization output signal of other each clock systems is resolved, obtain counting clock signal that other each synchronization output signals are corresponding, with counting clock signal phase difference be clock signal, the state value of 90 degree, then use the counting clock signal of each clock system from the synchronization output signal of each clock system, to extract respectively the synchronometer numerical value of each clock system.
Processor 105 can but be not limited to and comprise the second all-digital phase-locked loop and the second manchester decoder device, and the number of the second all-digital phase-locked loop and the second manchester decoder device is that in multimode redundant system, total number of clock system subtracts 1.For example, in multimode redundant system, total number of clock system is n, and the number of the second all-digital phase-locked loop is n-1, and the number of the second manchester decoder device is n-1.
Each the second all-digital phase-locked loop is corresponding one by one with the clock system except processor 105 place clock systems, and each the second manchester decoder device is corresponding one by one with the clock system except processor 105 place clock systems.For example, multimode redundant system comprises three clock systems, be respectively A, B and C, processor 105 place clock systems are clock system A, processor 105 comprises two the second all-digital phase-locked loops, be respectively the second all-digital phase-locked loop 1 and the second all-digital phase-locked loop 2, processor 105 comprises two the second manchester decoder devices, be respectively the second manchester decoder device 1 and the second manchester decoder device 2, the second all-digital phase-locked loop 1 and the second manchester decoder device 1 are corresponding with clock system B, the second all-digital phase-locked loop 2 and the second manchester decoder device 2 are corresponding with clock system C.
The second all-digital phase-locked loop, be used for the synchronization output signal of a clock system that obtains other each clock systems, and resolve this synchronization output signal, obtain clock signal, the counting clock signal of the clock system that this synchronization output signal is corresponding, the clock signal of clock system corresponding this synchronization output signal is sent to three and gets two effectors 101, the state value of clock system corresponding this synchronization output signal is sent to synchronous determining device 106.
The second manchester decoder device, for receiving the synchronization output signal of described the second all-digital phase-locked loop parsing and the counting clock signal that described the second all-digital phase-locked loop obtains, according to this synchronization output signal and this counting clock signal, extract synchronometer numerical value and the state value of the clock system that this synchronization output signal is corresponding, and send this synchronometer numerical value and the extremely synchronous determining device 106 of this state value.
Synchronous determining device 106, for the synchronometer numerical value to same clock system and state value combination, generate each clock system synchronometer numerical value to be judged separately, from synchronometer numerical value to be judged described in all, extract the current synchronometer numerical value of a synchronometer numerical value as each clock system.
In the present embodiment, synchronous determining device 106 can comprise: combiner, comparator and extractor, wherein:
Combiner, for the synchronometer numerical value to same clock system and state value combination, generates each clock system synchronometer numerical value to be judged separately.
Comparator, for from need to be judged that synchronometer numerical value to be judged that synchronometer numerical value chooses numerical value maximum is as synchronometer numerical value current to be judged.
Extractor, for extracting synchronometer numerical value from synchronometer numerical value current to be judged, and the current synchronometer numerical value using the synchronometer numerical value extracting as each clock system.
Certainly, coincidence counter 106 is just chosen current being not limited to when judging simultaneous techniques value from need the to be judged synchronometer numerical value to be judged that extracts maximum synchronometer numerical value as this kind of form of synchronometer numerical value current to be judged.
In the present embodiment, due to the synchronometer numerical value of this clock system and state value at set intervals, be sent to other each clock systems, but the counting clock signal of this clock system is always all to other each clock system transmission, therefore, first the counting clock signal of each clock system may be realized synchronously, then the synchronometer numerical value of each clock system is realized synchronous, certainly, counting clock signal and the synchronometer numerical value of not getting rid of each clock system are realized synchronous situation simultaneously.
It should be noted that, clock system in different synchronization modules realizes that counting clock signal is synchronous and synchronometer numerical value is synchronous, with respect to the clock system in different synchronization modules, only realize synchronometer numerical value synchronous, synchronous error reduces, and precision improves.
Wherein, synchronous error reduces, precision improves former because: the clock system in different synchronization modules is only realized the one-period that the synchronous error value of synchronometer numerical value when synchronous is counting clock signal to the maximum, clock system in different synchronization modules is realized the one-period that the synchronous error value of the synchronous and synchronometer numerical value of counting clock signal when synchronous is input clock signal to the maximum, because counting clock signal is obtained by input clock signal frequency division, therefore the frequency of counting clock signal is less than the frequency of input clock signal, because the frequency of counting clock signal is less than the frequency of input clock signal, therefore the cycle of counting clock signal is greater than the cycle of input clock signal, therefore the clock system in different synchronization modules is only realized the synchronous error value of synchronometer numerical value when synchronous and is greater than clock system in different synchronization modules and realizes the synchronous error value of the synchronous and synchronometer numerical value of counting clock signal when synchronous, so the clock system in different synchronization modules is realized counting clock signal synchronously and the synchronous synchronous error of synchronometer numerical value reduces, precision improves.
Clock system in any one synchronization module in multimode redundant system includes above-mentioned three and gets two effectors 101, the first all-digital phase-locked loop 102, coincidence counter 103, the first manchester encoder 104, processor 105 and synchronous determining device 106.
Because each synchronization module in multimode redundant system comprises clock system separately, and the clock system of each synchronization module is identical, therefore can realize the clock synchronous of each synchronization module in multimode redundant system.In clock system, the first all-digital phase-locked loop receives input clock signal, described input clock signal is processed to the clock signal that generates counting clock signal, state transition clock signal, sampled clock signal and be 90 degree with described counting clock signal phase difference, and follow the tracks of three and get the feedback clock signal identical with the counting clock signal cycle that two effectors extract from other clock systems, until the phase difference of described counting clock signal and described feedback clock signal keeps immobilizing.When the phase difference of described counting clock signal and described feedback clock signal keeps immobilizing, the counting clock signal that the described all-digital phase-locked loop in multimode redundant system in all clock systems generates is identical.Therefore, in multimode redundant system, the counting clock signal of all clock systems is realized synchronous.
Simultaneously, synchronometer numerical value and the state value combination of synchronous determining device to same clock system, generate each clock system synchronometer numerical value to be judged separately, from synchronometer numerical value to be judged described in all, extract the current synchronometer numerical value of a synchronometer numerical value as each clock system, make the synchronometer numerical value of each clock system in multimode redundant system identical, can realize the clock synchronous of all synchronization modules in multimode redundant system.
Further, in this application, it is synchronous that all clock systems are realized counting clock signal, and synchronometer numerical value is identical, make all clock systems to obtain identical synchronometer numerical value in the same moment, realized all synchronization module high precision clocks synchronous.In all clock system runnings, even if all clock systems obtain the asynchronism(-nization) of identical synchronometer numerical value, but it is very short that the counting clock signal of all clock systems synchronously makes all clock systems obtain time interval of identical synchronometer numerical value, thereby realize the clock synchronous that in redundant system, all synchronization module errors are little, precision is high.
In addition, the first manchester encoder 104 in above-described embodiment is also for storing the synchronometer numerical value of the clock system that the first manchester encoder 104 is positioned at, and the synchronometer numerical value of storage is carried out to cyclic redundancy check (CRC) computing, generation cycle redundancy check code, and described cyclic redundancy check (CRC) code is sent to other each clock systems.Whether the processor 105 of the clock system that the first manchester encoder 104 is positioned at also can receive other clock systems cyclic redundancy check (CRC) code separately, correct to verify the each self-corresponding synchronometer numerical value of other each clock systems that obtain.
By comprising that take multimode redundant system two separate synchronization modules are example, the course of work of the clock system of one of them synchronization module in two synchronization modules is described below.Suppose that multimode redundant system comprises synchronization module A and synchronization module B, synchronization module A comprises clock system A, and synchronization module B comprises clock system B.Now the course of work of clock system is described.Wherein, the processor of clock system A comprises second all-digital phase-locked loop and a second manchester decoder device.
The first all-digital phase-locked loop of clock system A, be used for receiving input clock signal, input clock signal is processed to the clock signal that generates counting clock signal, state transition signal, sampled clock signal and be 90 degree with described counting clock signal phase difference, counting clock signal is sent to coincidence counter, state transition signal and sampled clock signal are sent to the first manchester encoder, by being sent to three with the described counting clock signal phase difference clock signal that is 90 degree, get two effectors.
Coincidence counter is receiving after counting clock signal, and the number of count rising edge clock signal generates synchronometer numerical value, and the synchronometer numerical value of generation is sent to the first manchester encoder.
The first manchester encoder, generates synchronization output signal according to the state value of synchronometer numerical value, state transition clock signal, sampled clock signal and clock system A, and synchronization output signal is sent to clock system B.
The second all-digital phase-locked loop obtains the synchronization output signal of clock system B, and resolves this synchronization output signal, obtains clock signal, the counting clock signal of clock system B, the clock signal of clock system B is sent to three and gets two effectors.
The second manchester decoder device receives the synchronization output signal of clock system B that the second all-digital phase-locked loop resolves and the counting clock signal that the second all-digital phase-locked loop obtains, according to the synchronization output signal of clock system B and the counting clock signal of clock system B, extract synchronometer numerical value and the state value of clock system B, and send synchronometer numerical value and the extremely synchronous determining device of state value of clock system B.
Three get two effectors, from the clock signal of clock system A and the clock signal of clock system B, extract a clock signal as feedback clock signal, and feedback clock signal is sent to the first all-digital phase-locked loop, the first all-digital phase-locked loop is receiving after feedback clock signal, following feedback clock signal, until the cycle of counting clock signal and feedback clock signal is identical, phase difference keeps immobilizing, when the phase difference of counting clock signal and feedback clock signal keeps immobilizing, the counting clock signal that the first all-digital phase-locked loop of the counting clock signal that in clock system A, the first all-digital phase-locked loop generates and clock system B generates is identical.
Synchronous determining device, synchronometer numerical value to clock system A and state value combination, generate synchronometer numerical value A to be judged, synchronometer numerical value to clock system B and state value combination, generate synchronometer numerical value B to be judged, from synchronometer numerical value A to be judged and synchronometer numerical value B to be judged, extract the current synchronometer numerical value of a maximum synchronometer numerical value as clock system A and clock system B.
Take multimode redundant system, comprise that three separate synchronization modules are as example, the course of work of the clock system of one of them synchronization module in three synchronization modules is described.Wherein, when multimode redundant system comprises three separate synchronization modules, multimode redundant system is triple-modular redundancy system.Suppose that multimode redundant system comprises synchronization module A, synchronization module B and synchronization module C, synchronization module A comprises clock system A, and synchronization module B comprises clock system B, and synchronization module C comprises clock system C.Now with clock system A, the course of work of clock system is described.Wherein, clock system A comprises that the first all-digital phase-locked loop A, coincidence counter A, the first manchester encoder A, three get two effector A, processor A and synchronous determining device A, processor A comprises two the second all-digital phase-locked loops and two the second manchester decoder devices, two the second all-digital phase-locked loops are respectively the second all-digital phase-locked loop 1 and 2, two the second manchester decoder devices of the second all-digital phase-locked loop are respectively the second manchester decoder device 1 and the second manchester decoder device 2.
The first all-digital phase-locked loop A, receive input clock signal A, to input clock signal A process generate counting clock signal A, state transition signal A, sampled clock signal A and with described counting clock signal A phase difference be the clock signal A of 90 degree, counting clock signal A is sent to coincidence counter A, state transition signal A and sampled clock signal A are sent to the first manchester encoder A, clock signal A are sent to three and get two effector A.
Coincidence counter A is receiving after counting clock signal A, and the number of count clock signal A rising edge generates synchronometer numerical value A, and the synchronometer numerical value A of generation is sent to the first manchester encoder A.
The first manchester encoder A, state value A according to synchronometer numerical value A, state transition clock signal A, sampled clock signal A and clock system A generates synchronization output signal A, and synchronization output signal A is sent to clock system B and clock system C.
The second all-digital phase-locked loop 1 obtains the synchronization output signal B of clock system B, and resolves synchronization output signal B, obtains clock signal B, the counting clock signal B of clock system B, clock signal B is sent to three and gets two effector A.
The second manchester decoder device 1 receives the synchronization output signal B of the clock system B that the second all-digital phase-locked loop 1 resolves and the counting clock signal B that the second all-digital phase-locked loop 1 obtains, according to synchronization output signal B and counting clock signal B, extract synchronometer numerical value B and the state value B of clock system B, and send synchronous counting value B and the extremely synchronous determining device A of state value B.
The second all-digital phase-locked loop 2 obtains the synchronization output signal C of clock system C, and resolves synchronization output signal C, obtains clock signal C, the counting clock signal C of clock system C, clock signal C is sent to three and gets two effector A.
The second manchester decoder device 2 receives the synchronization output signal C of the clock system C that the second all-digital phase-locked loop 2 resolves and the counting clock signal C that the second all-digital phase-locked loop 2 obtains, according to synchronization output signal C and counting clock signal C, extract synchronometer numerical value C and the state value C of clock system C, and send synchronous counting value C and the extremely synchronous determining device A of state value C.
Three get two effector A, from clock signal B, clock signal C and clock signal A, extract a clock signal as feedback clock signal, and feedback clock signal is sent to the first all-digital phase-locked loop A, the first all-digital phase-locked loop A is receiving after feedback clock signal, following feedback clock signal, until the cycle of counting clock signal A and feedback clock signal is identical, phase difference keeps immobilizing, when the phase difference of counting clock signal A and feedback clock signal keeps immobilizing, counting clock signal B, counting clock signal C are identical with counting clock signal A.Because counting clock signal B, counting clock signal C are identical with counting clock signal A, therefore the counting clock signal of three synchronization modules is realized synchronous.
Synchronous determining device A, to synchronometer numerical value A and state value A combination, generate synchronometer numerical value A to be judged, to synchronometer numerical value B and state value B combination, generate synchronometer numerical value B to be judged, and to synchronometer numerical value C and state value C combination, generate synchronometer numerical value C to be judged, from synchronometer numerical value A to be judged, synchronometer numerical value B to be judged and synchronometer numerical value C to be judged, extract the current synchronometer numerical value of a maximum synchronometer numerical value as clock system A, clock system B and clock system C.The current synchronometer numerical value of clock system A, clock system B and clock system C reaches consistent, has realized the clock synchronous of three synchronization modules.
Structure and the course of work for above-mentioned clock system A can be referring to Fig. 8, and shown in Fig. 8 is structure and the course of work schematic diagram of the clock system in triple-modular redundancy system.
Data interaction between synchronization module A, synchronization module B and synchronization module C can be referring to Fig. 9, and shown in Fig. 9 is the schematic diagram of three synchronization module data interactions in triple-modular redundancy system.In Fig. 9, what the data interaction between synchronization module A, synchronization module B and synchronization module C was synchronization output signal is mutual, each synchronization module is sent to other two synchronization modules by synchronization output signal separately, and receives other two synchronization modules synchronization output signal separately.
Triple-modular redundancy system is a kind of redundant system in multimode redundant system, this triple-modular redundancy system comprises three separate synchronization modules, three synchronization modules comprise respectively the clock system that an above-described embodiment is set forth, and clock system are applied in to the clock synchronous that also can realize all synchronization modules in triple-modular redundancy system in triple-modular redundancy system.Wherein application has the structural representation of the triple-modular redundancy system of the clock system of above-described embodiment elaboration to refer to shown in Figure 10, each synchronization module comprises a clock system separately, the function of all parts in the triple-modular redundancy system shown in Figure 10 except clock system is identical with the function of all parts in prior art, does not repeat them here.
It should be noted that, in this article, relational terms such as the first and second grades is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply and between these entities or operation, have the relation of any this reality or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby the process, method, article or the equipment that make to comprise a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or be also included as the intrinsic key element of this process, method, article or equipment.The in the situation that of more restrictions not, the key element being limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
A kind of clock system above the application being provided is described in detail, applied principle and the execution mode of specific case to the application herein and set forth, the explanation of above embodiment is just for helping to understand the application's method and core concept thereof; , for one of ordinary skill in the art, according to the application's thought, all will change in specific embodiments and applications, in sum, this description should not be construed as the restriction to the application meanwhile.
Claims (6)
1. a clock system, is applied to multimode redundant system, and described multimode redundant system comprises at least two separate synchronization modules, and each described synchronization module comprises a described clock system, it is characterized in that, described clock system comprises:
For extracting a clock signal from each clock system clock signal separately, as three of feedback clock signal, get two effectors;
Get two effectors and be connected with described three, be used for receiving input clock signal, described input clock signal is processed and generated counting clock signal, state transition clock signal, sampled clock signal and the clock signal that is 90 degree with described counting clock signal phase difference, and follow the tracks of described feedback clock signal, until the cycle of described counting clock signal and described feedback clock signal is identical, phase difference keeps changeless the first all-digital phase-locked loop, when the phase difference of described counting clock signal and described feedback clock signal keeps immobilizing, described all-digital phase-locked loop in described multimode redundant system in all clock systems generates identical counting clock signal,
Be connected with described the first all-digital phase-locked loop, for calculating the number of described counting clock signal same type hopping edge, generate the coincidence counter of synchronometer numerical value;
Be connected with described the first all-digital phase-locked loop, described coincidence counter, for the state value according to described synchronometer numerical value, described state transition clock signal, described sampled clock signal and described clock system, generate synchronization output signal, wherein said state value is used for the first manchester encoder of the operation order of describing described clock system;
Get two effectors and be connected with described three, for obtaining the synchronization output signal of other each clock systems, respectively the synchronization output signal of other each clock systems is resolved, obtain the each self-corresponding counting clock signal of other each synchronization output signals, the processor with the each self-corresponding counting clock signal phase difference of described other each synchronization output signals be 90 degree clock signal, synchronometer numerical value and state value;
Be connected with described processor, described coincidence counter, for the synchronometer numerical value to same clock system and state value combination, generate each clock system synchronometer numerical value to be judged separately, from synchronometer numerical value to be judged described in all, extract the synchronous determining device of a synchronometer numerical value as the current synchronometer numerical value of each clock system.
2. clock system according to claim 1, is characterized in that, described processor comprises:
Be used for the synchronization output signal of a clock system that obtains other each clock systems, and resolve this synchronization output signal, obtain clock signal, the counting clock signal of the clock system that this synchronization output signal is corresponding, the clock signal of clock system corresponding this synchronization output signal is sent to described three the second all-digital phase-locked loops of getting two effectors;
Be connected with described the second all-digital phase-locked loop, for receiving the synchronization output signal of described the second all-digital phase-locked loop parsing and the counting clock signal that described the second all-digital phase-locked loop obtains, according to this synchronization output signal and this counting clock signal, extract clock system synchronometer numerical value and the state value that this synchronization output signal is corresponding, and send this synchronometer numerical value and extremely the second manchester decoder device of described synchronous determining device of this state value;
Wherein, the number of described the second all-digital phase-locked loop and described the second manchester decoder device is that in described multimode redundant system, total number of clock system subtracts 1.
3. clock system according to claim 1, is characterized in that, described the first all-digital phase-locked loop comprises:
For calculating the counting clock signal of described digital vco transmission and the phase difference of described feedback clock signal, and generate the phase discriminator of the phase signal that described phase difference is corresponding;
Be connected with described phase discriminator, the described phase signal sending for receiving described phase discriminator, and the digital rings mode filter of the generation pulse signal corresponding with described phase signal;
With described phase discriminator, described digital rings mode filter is connected, be used for receiving input clock signal, input clock signal is carried out to frequency division and obtain counting clock signal, state transition signal, sampled clock signal and the clock signal that is 90 degree with described counting clock signal phase difference, and receive the described pulse signal that described digital rings mode filter sends, according to described pulse signal and described input clock signal, adjust the phase place of described counting clock signal, until the difference of the phase place of described counting clock signal and the phase place of described feedback clock signal keeps changeless digital vco.
4. clock system according to claim 1, is characterized in that, described synchronous determining device comprises:
For the synchronometer numerical value to same clock system and state value combination, generate the combiner of each clock system synchronometer numerical value to be judged separately;
Be connected with described combiner, for being chosen the synchronometer numerical value to be judged of numerical value maximum as the comparator of synchronometer numerical value current to be judged from need to be judged synchronometer numerical value;
Be connected with described comparator, for extracting synchronometer numerical value from described current synchronometer numerical value to be judged, and the extractor of the current synchronometer numerical value using the synchronometer numerical value extracting as each clock system.
5. clock system according to claim 1, it is characterized in that, described multimode redundant system comprises three separate synchronization modules, described three get two effectors comprises the first port and the second port, described the first port and described the second port receive the clock signal of other each clock systems separately, and described the first port and described the second port only receive the clock signal of a clock system;
Described three get two effectors specifically for when the first port receives clock signal, and the clock signal that extraction the first port receives is as feedback clock signal; When the first port does not receive clock signal, and the second port is while receiving clock signal, extracts clock signal that the second port receives as feedback clock signal; When the first port and the second port do not receive clock signal, using described three clock signals of getting the clock system that two effectors are positioned at as feedback clock signal.
6. according to the clock system described in claim 1 to 5 any one, it is characterized in that, described counting clock signal is identical with described state transition clock signal frequency, the absolute value of phase difference is 180 degree;
The corresponding described state transition signal high level centre position of rising edge or the low level centre position of described sampled clock signal.
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| CN201320414485.XU CN203563054U (en) | 2013-07-11 | 2013-07-11 | Clock synchronizing system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103326716A (en) * | 2013-07-11 | 2013-09-25 | 杭州和利时自动化有限公司 | Clock synchronization system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103326716A (en) * | 2013-07-11 | 2013-09-25 | 杭州和利时自动化有限公司 | Clock synchronization system |
| CN103326716B (en) * | 2013-07-11 | 2016-06-15 | 杭州和利时自动化有限公司 | A kind of clock system |
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