CN203535414U - Thick yarn detection processing circuit - Google Patents
Thick yarn detection processing circuit Download PDFInfo
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- CN203535414U CN203535414U CN201320628219.7U CN201320628219U CN203535414U CN 203535414 U CN203535414 U CN 203535414U CN 201320628219 U CN201320628219 U CN 201320628219U CN 203535414 U CN203535414 U CN 203535414U
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Abstract
The utility model discloses a thick yarn detection processing circuit. A video sync separator chip LM1881 separates odd and even field signals from camera video signals and produces square wave output to a single-chip microcomputer. A control chip STC12C5628AD is a high-performance single-chip microcomputer low in power consumption and having an internally integrated multi-circuit AD, and can conveniently and flexibly output square-wave signals of an adjustable duty ratio, so that positive and reverse directions of an external motor are controlled. The video sync separator chip transmits the square-wave signals separated from the camera video signals to the control chip; and the control chip processes and converts the signals into a yarn diameter through an AD converter and an internal program, and outputs the square-wave signals of an adjustable duty ratio to control the positive and reverse directions of the motor by comparing the yarn diameter to a set value and analyzing errors, so that yarns are processed.
Description
Technical field
The utility model belongs to embedded system technology field, relates to a kind of circuit, specifically a kind of thick line Check processing circuit.
Background technology
Electronic yarn clearer is a kind of electro-mechanical device that detects and cut off yarn defect.By sensor, the thickness of yarn is changed and converts corresponding electric signal to, signal is controlled after treatment topworks and is cut off surpassing thick (carefully) degree of setting and the yarn defect of length, removes the influential yarn defect of product quality.It is recurrent in the resultant yarn process of yarn, being subject to the yarn fault that affects of many factors, no matter is traditional Yarn spinning method or all kinds of spinning method, and yarn fault is also inevitable.In order to improve the quality of products, increase economic benefit, weave gratifying quality product, this just has higher requirement to electronic yarn clearer.
The electronic yarn clearer of supply is embodied as master with mimic channel in the market, and its shortcoming is that the parameter variation that device aging causes causes cutting rate of false alarm rising by mistake, and accuracy of detection is not high simultaneously.
Summary of the invention
The utility model is that the yarn detection failure and the accuracy of detection that for current yarn clearer device aging, cause are too low, designs electronic yarn clearer that a kind of precision the is higher Check processing circuit to thick line.
The concrete technical scheme that the utility model technical solution problem is taked is:
A kind of thick line Check processing of the utility model circuit comprises the first serial line interface JP1(HD-2), the 3rd filter capacitor C3, Video Sync Separator Chip U1(LM1881), the 4th filter capacitor C4, the first resistance R 1, control chip U5(STC12C5628AD), the 3rd resistance R 3, the 5th filter capacitor C5, the 6th electrolytic capacitor filter C6, the 7th filter capacitor C7, the 8th filter capacitor C8, clock crystal oscillator Y1, first drives chip U2(IR2103), the first diode D1, the first electrolytic capacitor filter C1, second drives chip U3(IR2104), the second diode D2, the second electrolytic capacitor filter C2, the first Sheffer stroke gate U4A(SN74L S00N), the 4th Sheffer stroke gate U4D(SN74L S00N), the 3rd Sheffer stroke gate U4C(SN74L S00N), the second resistance R 2, the 4th resistance R 4, the second Sheffer stroke gate U4B(SN74L S00N), the 5th resistance R 5, the first N-channel MOS pipe Q1 (IRF540), the 6th resistance R 6, the second N-channel MOS pipe Q2(IRF540), the 9th filter capacitor C9, the 8th resistance R 8, the nine resistance R 9, the 11 resistance R 11, the second positive-negative-positive triode Q5(2N3906), the 3rd N-channel MOS pipe Q3(IRF540), the 12 resistance R 12, the 4th N-channel MOS pipe Q6 (IRF540), the 7th resistance R 7, the tenth resistance R 10, the first positive-negative-positive triode Q4(2N3906) and the second serial line interface JP2(HD-2).
No. 1 pin ground connection of the first serial line interface JP1, No. 2 pins of the first serial line interface JP1 are connected with one end of the 3rd filter capacitor C3, the other end of the 3rd filter capacitor C3 is connected with No. 2 pins of Video Sync Separator Chip U1, No. 1 pin of Video Sync Separator Chip U1 is connected with No. 8 pins of control chip U5, No. 3 pins of Video Sync Separator Chip U1 are connected with No. 9 pins of control chip U5, No. 4 pin ground connection of Video Sync Separator Chip U1, No. 6 pins of Video Sync Separator Chip U1 and one end of the first resistance R 1, one end of the 4th filter capacitor C4 connects, the other end of the 4th filter capacitor C4 electric capacity is connected with the other end of the first resistance R 1, No. 7 pins of Video Sync Separator Chip U1 are connected with No. 15 pins of control chip U5, No. 8 pins of Video Sync Separator Chip U1 connect 5V operating voltage,
One end ground connection of the 3rd resistance R 3, the other end of the R3 of the 3rd resistance is connected with No. 3 pins of control chip U5, one end ground connection of one end of the 7th filter capacitor C7 and the 8th filter capacitor C8, one end of the other end of the 7th filter capacitor C7 and clock crystal oscillator Y1, No. 6 pins of control chip U5 connect, the other end of another termination clock crystal oscillator Y1 of the 8th filter capacitor C8, No. 7 pins of control chip U5 connect, No. 11 pins of control chip U5 connect one end of the 11 resistance R 11, an input end of the first Sheffer stroke gate U4A connects, No. 12 pins of control chip U5 and one end of the tenth resistance R 10, an input end of the 4th Sheffer stroke gate U4D connects, No. 14 pin ground connection of control chip U5, No. 17 pins of control chip U5 and another input end of the first Sheffer stroke gate U4A, another input end of the 4th Sheffer stroke gate U4D connects, No. 28 pins of control chip U5, the anodal termination 5V operating voltage of one end of the 5th filter capacitor C5 and the 6th electrolytic capacitor filter C6, the other end of the 5th filter capacitor C5, the negative pole end ground connection of the 6th electrolytic capacitor filter C6,
First drives No. 1 pin of chip U2 to connect 12V operating voltage, first drives No. 2 pins of chip U2 and the output terminal of the first Sheffer stroke gate U4A, one end of the second resistance R 2, the input end of the second Sheffer stroke gate U4B connects, first drives No. 3 pins of chip U2 to be connected with the output terminal of the second Sheffer stroke gate U4B, first drives No. 4 pin ground connection of chip U2, first drives No. 6 pins of chip U2 and the negative pole of the first electrochemical capacitor C1, the source electrode of the first N-channel MOS pipe Q1, the drain electrode of the 3rd N-channel MOS pipe Q3, one end of the 9th filter capacitor C9 connects, first drives No. 8 pins of chip U2 and the negative electrode of the first diode D1, the positive pole of the first electrochemical capacitor C1 connects, first drives No. 7 pins of chip U2 to be connected with one end of the 5th resistance R 5, the anode of the first diode D1 connects the operating voltage of 12V, second drives No. 1 pin of chip U3 to connect 12V operating voltage, second drives No. 2 pins of chip U3 and the output terminal of the 4th Sheffer stroke gate U4D, one end of the 4th resistance R 4, the input end of the second Sheffer stroke gate U4B connects, second drives No. 3 pins of chip U3 to be connected with the output terminal of the second Sheffer stroke gate U4B, second drives No. 4 pin ground connection of chip U3, second drives No. 6 pins of chip U3 and the negative pole of the second electrochemical capacitor C2, the source electrode of the second N-channel MOS pipe Q2, the drain electrode of the 4th N-channel MOS pipe Q6, the other end of the 9th filter capacitor C9 connects, second drives No. 8 pins of chip U3 and the negative electrode of the second diode D2, the positive pole of the second electrochemical capacitor C2 connects, second drives No. 7 pins of chip U3 to be connected with one end of the 6th resistance R 6, the anode of the second diode D2 connects the operating voltage of 12V, another termination VCC power supply of the second resistance R 2, another termination VCC power supply of the 4th resistance R 4, two input end groundings of the 3rd Sheffer stroke gate U4C, the output termination VCC power supply of the 3rd Sheffer stroke gate U4C,
The grid of another termination first N-channel MOS pipe Q1 of the 5th resistance R 5, the drain electrode of the drain electrode of the first N-channel MOS pipe Q1 and the second N-channel MOS pipe Q2 connects 7.2V operating voltage, the grid of another termination second N-channel MOS pipe Q2 of the 6th resistance R 6, one termination 12V operating voltage of the 8th resistance R 8, the other end of the 8th resistance R 8, one end of the 9th resistance R 9 is connected with the emitter of the second positive-negative-positive triode Q5, the other end of the 9th resistance R 9 is connected with the grid of the 3rd N-channel MOS pipe Q3, the base stage of another termination second positive-negative-positive triode Q5 of the 11 resistance R 11, one end of the 12 resistance R 12, one end of the 7th resistance R 7 is connected with the emitter of the first positive-negative-positive triode Q4, the other end of the 12 resistance R 12 is connected with the grid of the 4th N-channel MOS pipe Q6, another termination 12V operating voltage of the 7th resistance R 7, the other end of the tenth resistance R 10 is connected with the base stage of the first positive-negative-positive triode Q4, the collector of the first positive-negative-positive triode Q4, the collector of the second positive-negative-positive triode Q5, the source electrode of the 3rd N-channel MOS pipe Q3, the source ground of the 4th N-channel MOS pipe Q6, No. 1 pin of the second serial line interface JP2 connects the source electrode of the second N-channel MOS pipe Q2, the drain electrode of the 4th N-channel MOS pipe Q6, No. 2 pin of the second serial line interface JP2 connect the source electrode of the first N-channel MOS pipe Q1, the drain electrode of the 3rd N-channel MOS pipe Q3.Video Sync Separator Chip U1, first drives chip U2, second to drive chip U3 and control chip U5, and NM pin is built on stilts hereinbefore.
The utility model has following beneficial effect with respect to prior art: system adopts Video Sync Separator Chip to carry out audio video synchronization separation to camera output signal, by the electrical signal transfer producing to controller, control chip is converted into this electric signal through the yarn diameter parameter between transmitter and receiver via the operational processes of AD conversion and program inside, thereby can change and judge whether to occur yarn fault according to the yarn diameter detecting, according to the setting value of system and actual value, contrast, controller judges, output signal drive motor is to there being the yarn of yarn defect to process accordingly simultaneously.
Accompanying drawing explanation
The circuit theory diagrams of Fig. 1 thick line Check processing.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in further detail.
As shown in Figure 1, a kind of thick line Check processing of the utility model circuit comprises the first serial line interface JP1(HD-2), the 3rd filter capacitor C3, Video Sync Separator Chip U1(LM1881), the 4th filter capacitor C4, the first resistance R 1, control chip U5(STC12C5628AD), the 3rd resistance R 3, the 5th filter capacitor C5, the 6th electrolytic capacitor filter C6, the 7th filter capacitor C7, the 8th filter capacitor C8, clock crystal oscillator Y1, first drives chip U2(IR2103), the first diode D1, the first electrolytic capacitor filter C1, second drives chip U3(IR2104), the second diode D2, the second electrolytic capacitor filter C2, the first Sheffer stroke gate U4A(SN74L S00N), the 4th Sheffer stroke gate U4D(SN74L S00N), the 3rd Sheffer stroke gate U4C(SN74L S00N), the second resistance R 2, the 4th resistance R 4, the second Sheffer stroke gate U4B(SN74L S00N), the 5th resistance R 5, the first N-channel MOS pipe Q1 (IRF540), the 6th resistance R 6, the second N-channel MOS pipe Q2(IRF540), the 9th filter capacitor C9, the 8th resistance R 8, the 9th resistance R 9, the 11 resistance R 11, the second positive-negative-positive triode Q5(2N3906), the 3rd N-channel MOS pipe Q3(IRF540), the 12 resistance R 12, the 4th N-channel MOS pipe Q6 (IRF540), the 7th resistance R 7, the tenth resistance R 10, the first positive-negative-positive triode Q4(2N3906), the second serial line interface JP2(HD-2).
No. 1 pin ground of the first serial line interface JP1, No. 2 pins of the first serial line interface JP1 are connected with one end of the 3rd filter capacitor C3, the other end of the 3rd filter capacitor C3 is connected with No. 2 pins of Video Sync Separator Chip U1, No. 1 pin of Video Sync Separator Chip U1 is connected with No. 8 pins of control chip U5, No. 3 pins of Video Sync Separator Chip U1 are connected with No. 9 pins of control chip U5, No. 4 pin ground connection of Video Sync Separator Chip U1, No. 6 pins of Video Sync Separator Chip U1 and one end of the first resistance R 1, one end of the 4th filter capacitor C4 connects, the other end of the 4th filter capacitor C4 electric capacity is connected with the other end of the first resistance R 1, No. 7 pins of Video Sync Separator Chip U1 are connected with No. 15 pins of control chip U5, No. 8 pins of Video Sync Separator Chip U1 connect 5V operating voltage,
One end ground connection of the 3rd resistance R 3, the other end of the R3 of the 3rd resistance is connected with No. 3 pins of control chip U5, one end ground connection of one end of the 7th filter capacitor C7 and the 8th filter capacitor C8, one end of the other end of the 7th filter capacitor C7 and clock crystal oscillator Y1, No. 6 pins of control chip U5 connect, the other end of another termination clock crystal oscillator Y1 of the 8th filter capacitor C8, No. 7 pins of control chip U5 connect, No. 11 pins of control chip U5 connect one end of the 11 resistance R 11, an input end of the first Sheffer stroke gate U4A connects, No. 12 pins of control chip U5 and one end of the tenth resistance R 10, an input end of the 4th Sheffer stroke gate U4D connects, No. 14 pin ground connection of control chip U5, No. 17 pins of control chip U5 and another input end of the first Sheffer stroke gate U4A, another input end of the 4th Sheffer stroke gate U4D connects, No. 28 pins of control chip U5, the anodal termination 5V operating voltage of one end of the 5th filter capacitor C5 and the 6th electrolytic capacitor filter C6, the other end of the 5th filter capacitor C5, the negative pole end ground connection of the 6th electrolytic capacitor filter C6,
First drives No. 1 pin of chip U2 to connect 12V operating voltage, first drives No. 2 pins of chip U2 and the output terminal of the first Sheffer stroke gate U4A, one end of the second resistance R 2, the input end of the second Sheffer stroke gate U4B connects, first drives No. 3 pins of chip U2 to be connected with the output terminal of the second Sheffer stroke gate U4B, first drives No. 4 pin ground connection of chip U2, first drives No. 6 pins of chip U2 and the negative pole of the first electrochemical capacitor C1, the source electrode of the first N-channel MOS pipe Q1, the drain electrode of the 3rd N-channel MOS pipe Q3, one end of the 9th filter capacitor C9 connects, first drives No. 8 pins of chip U2 and the negative electrode of the first diode D1, the positive pole of the first electrochemical capacitor C1 connects, first drives No. 7 pins of chip U2 to be connected with one end of the 5th resistance R 5, the anode of the first diode D1 connects the operating voltage of 12V, second drives No. 1 pin of chip U3 to connect 12V operating voltage, second drives No. 2 pins of chip U3 and the output terminal of the 4th Sheffer stroke gate U4D, one end of the 4th resistance R 4, the input end of the second Sheffer stroke gate U4B connects, second drives No. 3 pins of chip U3 to be connected with the output terminal of the second Sheffer stroke gate U4B, second drives No. 4 pin ground connection of chip U3, second drives No. 6 pins of chip U3 and the negative pole of the second electrochemical capacitor C2, the source electrode of the second N-channel MOS pipe Q2, the drain electrode of the 4th N-channel MOS pipe Q6, the other end of the 9th filter capacitor C9 connects, second drives No. 8 pins of chip U3 and the negative electrode of the second diode D2, the positive pole of the second electrochemical capacitor C2 connects, second drives No. 7 pins of chip U3 to be connected with one end of the 6th resistance R 6, the anode of the second diode D2 connects the operating voltage of 12V, another termination VCC power supply of the second resistance R 2, another termination VCC power supply of the 4th resistance R 4, two input end groundings of the 3rd Sheffer stroke gate U4C, the output termination VCC power supply of the 3rd Sheffer stroke gate U4C,
The grid of another termination first N-channel MOS pipe Q1 of the 5th resistance R 5, the drain electrode of the drain electrode of the first N-channel MOS pipe Q1 and the second N-channel MOS pipe Q2 connects 7.2V operating voltage, the grid of another termination second N-channel MOS pipe Q2 of the 6th resistance R 6, one termination 12V operating voltage of the 8th resistance R 8, the other end of the 8th resistance R 8, one end of the 9th resistance R 9 is connected with the emitter of the second positive-negative-positive triode Q5, the other end of the 9th resistance R 9 is connected with the grid of the 3rd N-channel MOS pipe Q3, the base stage of another termination second positive-negative-positive triode Q5 of the 11 resistance R 11, one end of the 12 resistance R 12, one end of the 7th resistance R 7 is connected with the emitter of the first positive-negative-positive triode Q4, the other end of the 12 resistance R 12 is connected with the grid of the 4th N-channel MOS pipe Q6, another termination 12V operating voltage of the 7th resistance R 7, the other end of the tenth resistance R 10 is connected with the base stage of the first positive-negative-positive triode Q4, the collector of the first positive-negative-positive triode Q4, the collector of the second positive-negative-positive triode Q5, the source electrode of the 3rd N-channel MOS pipe Q3, the source ground of the 4th N-channel MOS pipe Q6, No. 1 pin of the second serial line interface JP2 connects the source electrode of the second N-channel MOS pipe Q2, the drain electrode of the 4th N-channel MOS pipe Q6, No. 2 pin of the second serial line interface JP2 connect the source electrode of the first N-channel MOS pipe Q1, the drain electrode of the 3rd N-channel MOS pipe Q3.
Video Sync Separator Chip LM1881 of the present utility model isolates parity field signal from camera video signal, produces square wave and exports to single-chip microcomputer.Control chip STC12C5628AD is the High Performance SCM of a kind of low-power consumption, chip internal integrated multipath AD, simultaneously it can be for convenience of and the adjustable square-wave signal of output duty cycle flexibly, to realize the forward and reverse control to external motor.The square-wave signal that Video Sync Separator Chip is separated camera shooting and video signal is passed to control chip, control chip is converted into yarn diameter by AD converter and internal processes operational processes by this signal, then by contrasting with setting value, error analysis, the square-wave signal that output duty cycle is adjustable is controlled the forward and reverse of motor, thereby realizes the processing to yarn.
Claims (1)
1. thick line Check processing circuit, comprises the first serial line interface JP1, the 3rd filter capacitor C3, Video Sync Separator Chip U1, the 4th filter capacitor C4, the first resistance R 1, control chip U5, the 3rd resistance R 3, the 5th filter capacitor C5, the 6th electrolytic capacitor filter C6, the 7th filter capacitor C7, the 8th filter capacitor C8, clock crystal oscillator Y1, first drives chip U2, the first diode D1, the first electrolytic capacitor filter C1, second drives chip U3, the second diode D2, the second electrolytic capacitor filter C2, the first Sheffer stroke gate U4A, the 4th Sheffer stroke gate U4D, the 3rd Sheffer stroke gate U4C, the second resistance R 2, the 4th resistance R 4, the second Sheffer stroke gate U4B, the 5th resistance R 5, the first N-channel MOS pipe Q1, the 6th resistance R 6, the second N-channel MOS pipe Q2, the 9th filter capacitor C9, the 8th resistance R 8, the nine resistance R 9, the 11 resistance R 11, the second positive-negative-positive triode Q5, the 3rd N-channel MOS pipe Q3, the 12 resistance R 12, the 4th N-channel MOS pipe Q6, the 7th resistance R 7, the tenth resistance R 10, the first positive-negative-positive triode Q4 and the second serial line interface JP2,
It is characterized in that: No. 1 pin ground connection of the first described serial line interface JP1, No. 2 pins of the first serial line interface JP1 are connected with one end of the 3rd filter capacitor C3, the other end of the 3rd filter capacitor C3 is connected with No. 2 pins of Video Sync Separator Chip U1, No. 1 pin of Video Sync Separator Chip U1 is connected with No. 8 pins of control chip U5, No. 3 pins of Video Sync Separator Chip U1 are connected with No. 9 pins of control chip U5, No. 4 pin ground connection of Video Sync Separator Chip U1, No. 6 pins of Video Sync Separator Chip U1 and one end of the first resistance R 1, one end of the 4th filter capacitor C4 connects, the other end of the 4th filter capacitor C4 electric capacity is connected with the other end of the first resistance R 1, No. 7 pins of Video Sync Separator Chip U1 are connected with No. 15 pins of control chip U5, No. 8 pins of Video Sync Separator Chip U1 connect 5V operating voltage,
One end ground connection of the 3rd resistance R 3, the other end of the R3 of the 3rd resistance is connected with No. 3 pins of control chip U5, one end ground connection of one end of the 7th filter capacitor C7 and the 8th filter capacitor C8, one end of the other end of the 7th filter capacitor C7 and clock crystal oscillator Y1, No. 6 pins of control chip U5 connect, the other end of another termination clock crystal oscillator Y1 of the 8th filter capacitor C8, No. 7 pins of control chip U5 connect, No. 11 pins of control chip U5 connect one end of the 11 resistance R 11, an input end of the first Sheffer stroke gate U4A connects, No. 12 pins of control chip U5 and one end of the tenth resistance R 10, an input end of the 4th Sheffer stroke gate U4D connects, No. 14 pin ground connection of control chip U5, No. 17 pins of control chip U5 and another input end of the first Sheffer stroke gate U4A, another input end of the 4th Sheffer stroke gate U4D connects, No. 28 pins of control chip U5, the anodal termination 5V operating voltage of one end of the 5th filter capacitor C5 and the 6th electrolytic capacitor filter C6, the other end of the 5th filter capacitor C5, the negative pole end ground connection of the 6th electrolytic capacitor filter C6,
First drives No. 1 pin of chip U2 to connect 12V operating voltage, first drives No. 2 pins of chip U2 and the output terminal of the first Sheffer stroke gate U4A, one end of the second resistance R 2, the input end of the second Sheffer stroke gate U4B connects, first drives No. 3 pins of chip U2 to be connected with the output terminal of the second Sheffer stroke gate U4B, first drives No. 4 pin ground connection of chip U2, first drives No. 6 pins of chip U2 and the negative pole of the first electrochemical capacitor C1, the source electrode of the first N-channel MOS pipe Q1, the drain electrode of the 3rd N-channel MOS pipe Q3, one end of the 9th filter capacitor C9 connects, first drives No. 8 pins of chip U2 and the negative electrode of the first diode D1, the positive pole of the first electrochemical capacitor C1 connects, first drives No. 7 pins of chip U2 to be connected with one end of the 5th resistance R 5, the anode of the first diode D1 connects the operating voltage of 12V, second drives No. 1 pin of chip U3 to connect 12V operating voltage, second drives No. 2 pins of chip U3 and the output terminal of the 4th Sheffer stroke gate U4D, one end of the 4th resistance R 4, the input end of the second Sheffer stroke gate U4B connects, second drives No. 3 pins of chip U3 to be connected with the output terminal of the second Sheffer stroke gate U4B, second drives No. 4 pin ground connection of chip U3, second drives No. 6 pins of chip U3 and the negative pole of the second electrochemical capacitor C2, the source electrode of the second N-channel MOS pipe Q2, the drain electrode of the 4th N-channel MOS pipe Q6, the other end of the 9th filter capacitor C9 connects, second drives No. 8 pins of chip U3 and the negative electrode of the second diode D2, the positive pole of the second electrochemical capacitor C2 connects, second drives No. 7 pins of chip U3 to be connected with one end of the 6th resistance R 6, the anode of the second diode D2 connects the operating voltage of 12V, another termination VCC power supply of the second resistance R 2, another termination VCC power supply of the 4th resistance R 4, two input end groundings of the 3rd Sheffer stroke gate U4C, the output termination VCC power supply of the 3rd Sheffer stroke gate U4C,
The grid of another termination first N-channel MOS pipe Q1 of the 5th resistance R 5, the drain electrode of the drain electrode of the first N-channel MOS pipe Q1 and the second N-channel MOS pipe Q2 connects 7.2V operating voltage, the grid of another termination second N-channel MOS pipe Q2 of the 6th resistance R 6, one termination 12V operating voltage of the 8th resistance R 8, the other end of the 8th resistance R 8, one end of the 9th resistance R 9 is connected with the emitter of the second positive-negative-positive triode Q5, the other end of the 9th resistance R 9 is connected with the grid of the 3rd N-channel MOS pipe Q3, the base stage of another termination second positive-negative-positive triode Q5 of the 11 resistance R 11, one end of the 12 resistance R 12, one end of the 7th resistance R 7 is connected with the emitter of the first positive-negative-positive triode Q4, the other end of the 12 resistance R 12 is connected with the grid of the 4th N-channel MOS pipe Q6, another termination 12V operating voltage of the 7th resistance R 7, the other end of the tenth resistance R 10 is connected with the base stage of the first positive-negative-positive triode Q4, the collector of the first positive-negative-positive triode Q4, the collector of the second positive-negative-positive triode Q5, the source electrode of the 3rd N-channel MOS pipe Q3, the source ground of the 4th N-channel MOS pipe Q6, No. 1 pin of the second serial line interface JP2 connects the source electrode of the second N-channel MOS pipe Q2, the drain electrode of the 4th N-channel MOS pipe Q6, No. 2 pin of the second serial line interface JP2 connect the source electrode of the first N-channel MOS pipe Q1, the drain electrode of the 3rd N-channel MOS pipe Q3.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320628219.7U CN203535414U (en) | 2013-10-12 | 2013-10-12 | Thick yarn detection processing circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320628219.7U CN203535414U (en) | 2013-10-12 | 2013-10-12 | Thick yarn detection processing circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103543647A (en) * | 2013-10-12 | 2014-01-29 | 新昌县锦马科技有限公司 | Thick yarn detection processing circuit |
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| CN103543647A (en) * | 2013-10-12 | 2014-01-29 | 新昌县锦马科技有限公司 | Thick yarn detection processing circuit |
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