CN203521430U - Thin film transistor, array substrate, and display device - Google Patents
Thin film transistor, array substrate, and display device Download PDFInfo
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- CN203521430U CN203521430U CN201320613545.0U CN201320613545U CN203521430U CN 203521430 U CN203521430 U CN 203521430U CN 201320613545 U CN201320613545 U CN 201320613545U CN 203521430 U CN203521430 U CN 203521430U
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Abstract
The utility model belongs to the technical field of display, and specifically relates to a thin film transistor, an array substrate, and a display device. The thin film transistor comprises a substrate and a grid electrode disposed on the substrate, a source electrode and a drain electrode which are disposed at the same layer, and an insulation layer between the grid electrode and the source electrode and the drain electrode, wherein the grid electrode pre-forming layer is disposed at the same layer with the grid electrode, and the grid electrode is formed in the grid electrode performing layer; and/or the source and drain performing layer is disposed at the same layer with the source electrode and the drain electrode, and the source electrode and the drain electrode are formed in the source and drain performing layer. The film transistor, the array substrate, and the display device are beneficial in that: by employing the thin film transistor structure and the corresponding substrate, negative effects of the grid electrode or the source electrode or drain electrode caused by etching defects at a slope are alleviated effectively, the possibility of discontinuity caused by subsequent film layer convex and concave is reduced, and the quality of the display device is improved.
Description
Technical field
The utility model belongs to Display Technique field, is specifically related to a kind of thin-film transistor, array base palte and display unit.
Background technology
Along with scientific and technical development, panel display apparatus has replaced heavy CRT (Cathode Ray Tube, cathode ray tube) display unit to be goed deep in daily life day by day.Liquid crystal indicator) and OLED(Organic Light-Emitting Diode at present, conventional panel display apparatus comprises LCD(Liquid Crystal Display:: Organic Light Emitting Diode) display unit.
In imaging process, LCD and active matrix drive type OLED(Active Matrix Organic Light Emission Display, be called for short AMOLED) all comprise the thin-film transistor (Thin Film Transistor: be called for short TFT) being formed in array base palte in display unit.Thin-film transistor is the key that realizes LCD and the demonstration of active matrix drive type OLED display unit, is directly connected to the developing direction of high-performance display device.
As shown in Figure 1, a kind of typical structure of thin-film transistor comprises substrate 1 and the grid 2, gate insulation layer 4, active layer 5, the etching barrier layer 6 that on substrate, form and be formed on source electrode 7 and the drain electrode 8 above etching barrier layer 6.At present, the technical process of preparing thin-film transistor is generally and adopts composition technique, preparation forms the figure that comprises each rete successively from below to up, because the rete number of thin-film transistor is more, therefore adopting composition technique to form in the process of each rete, for example, in deposition and etch step, be easy to because first certain rete of formation is in sudden change place of figure, for example: place, slope shown in Fig. 1 forms the defect 15(of small protrusion or depression because etching is irregular certain, also likely for being recessed to the defect of whole layer).In Fig. 1, gate insulation layer 4 is formed depression because being to carve, dark or excessive if caved in, carrying out along with plated film, while depositing due to subsequent film, be all difficult to enter top and have the position stopping, defect can not filled, and the part producing during etching is spent quarter and just the rete of deposition is etched away very easily, form more and more serious defect, between the rete that finally causes originally should not connecting, be in contact with one another, for example may form active layer 5 in Fig. 1 and in correspondence, the discontinuous situation in region of this defect, and then cause source electrode 7 destroyed with the insulation of grid 2, cause being connected of source electrode 7 and grid 2.Can infer, once there is protrusion or the depression of certain rete in sudden change place of figure, accumulation along with a plurality of composition techniques, further aggravation of the discontinuous situation that the protrusion situation of subsequent film or depression cause, cause the bad of display floater, especially the connection between the metal electrode causing because of depression, causes display floater electric leakage the most at last.Once and display floater electric leakage will cause scrapping of monoblock display floater, cause the significant wastage of production cost.
Therefore, design each rete in thin-film transistor and can not be prepared technogenic influence and occur Insulation Problems, especially anti-creeping structure effectively between metal electrode, improves the quality of products and becomes current industry problem demanding prompt solution.
Utility model content
Technical problem to be solved in the utility model is for above shortcomings in prior art, a kind of thin-film transistor, array base palte and display unit are provided, in this thin-film transistor and corresponding array base palte, can effectively slow down the counter productive that grid or source electrode and drain electrode bring because of the etching defect at slope place, stop the discontinuous possibility of subsequent film, improve the quality of display unit.
The technical scheme that solution the utility model technical problem adopts is this thin-film transistor, comprise substrate and be arranged at grid on described substrate, the source electrode and the drain electrode that with layer, arrange and be arranged at described grid and described source electrode and described drain electrode between insulating barrier, with layer, be provided with the pre-formed layer of grid with described grid, described grid is formed in the pre-formed layer of described grid; And/or, with layer, the pre-formed layer of active leakage being set with described source electrode and described drain electrode, described source electrode and described drain electrode are formed on described source and leak in pre-formed layer.
Preferably, described grid is arranged on described substrate, described source electrode and described drain electrode are arranged on the top of described grid, and the region that the pre-formed layer of described grid formation grid in correspondence offers grid embedded groove, and described grid is arranged in described grid embedded groove; And/or, described source is leaked pre-formed layer and in correspondence, that the region that forms described source electrode offers source electrode embedded groove, corresponding the region that forms described drain electrode offers drain electrode embedded groove, described source electrode is arranged in described source electrode embedded groove, and described drain electrode is arranged in described drain electrode embedded groove.
Preferably, described source electrode and described drain electrode are arranged on described substrate, described grid is arranged on the top of described source electrode and described drain electrode, described source is leaked pre-formed layer and in correspondence, that the region that forms described source electrode offers source electrode embedded groove, corresponding the region that forms described drain electrode offers drain electrode embedded groove, described source electrode is arranged in described source electrode embedded groove, and described drain electrode is arranged in described drain electrode embedded groove; And/or the region that the pre-formed layer of described grid the described grid of formation in correspondence offers grid embedded groove, described grid is arranged in described grid embedded groove.
Preferably, the pre-formed layer of described grid leaks pre-formed layer with described source and all adopts inorganic material to form, and described inorganic material comprises silicon nitride, silica or silicon oxynitride.
Preferably, the thickness of described grid is identical with the thickness of the pre-formed layer of described grid, and the thickness of described source electrode and described drain electrode is identical with the thickness that pre-formed layer is leaked in described source.
Further preferably, between described source electrode and described drain electrode, be also provided with active layer, and described active layer is overlapping at least partly in orthographic projection direction with described source electrode and described drain electrode respectively, described active layer adopts amorphous silicon material to form; Or described active layer adopts indium oxide gallium zinc, indium zinc oxide, tin indium oxide or indium oxide gallium tin to form.
An array base palte, comprises grid line, data wire and is arranged on the thin-film transistor in the pixel region being intersected to form by described grid line and described data wire, described thin-film transistor adopts above-mentioned thin-film transistor.
Preferably, the pre-formed layer of described grid also extends to described pixel region correspondence and described thin-film transistor other regions in addition, and described grid line and described grid arrange and are electrically connected to described grid with layer; Or described source is leaked pre-formed layer and is also extended to described pixel region correspondence and other regions beyond described thin-film transistor, described data wire with described source electrode with layer setting and be electrically connected to described source electrode.
Preferably, the region that the pre-formed layer of described grid formation grid line in correspondence offers grid line embedded groove, and described grid line is arranged in described grid line embedded groove; Or the region that leakage pre-formed layer in described source formation data wire in correspondence offers data wire embedded groove, described data wire is arranged in described data wire embedded groove.
Preferably, the thickness of described grid equates with the thickness of described grid, and the thickness of described data wire equates with the thickness of described source electrode.
A display unit, comprises above-mentioned array base palte.
The beneficial effects of the utility model are: the thin-film transistor in the utility model, by inorganic material is formed on substrate, forms the groove identical with gate patterns by exposure, development, etching; Then form grid, and make the thickness of grid and the degree of depth of groove in full accord, form and to be filled to the full graphics in groove with gate metal material; And then other retes of formation thin-film transistor; And/or, make source electrode and drain electrode there is similar layer structure, this structure can effectively slow down the counter productive that grid or source electrode and drain electrode bring because of the etching defect at slope place, while relating to gate metal tunic, source leakage metal tunic deposition and etching for solution, there is less desirable defect effective especially, can fundamentally stop the protrusion situation of thin-film transistor subsequent film or the possibility of the discontinuous situation that depression causes, improve the quality of display unit.
Accompanying drawing explanation
Fig. 1 is the cutaway view of thin-film transistor in prior art;
Fig. 2 is the cutaway view of a kind of thin-film transistor structure in the utility model example 1;
Fig. 3 is the cutaway view of a kind of thin-film transistor structure in the utility model example 1;
Fig. 4 is the cutaway view of a kind of thin-film transistor structure in the utility model example 1;
Fig. 5 A-5H is that in Fig. 4, thin-film transistor comprises the process cutaway view that the figure of grid forms;
Fig. 6 is the structural representation that in the utility model example 1, grid has protruding defect;
Fig. 7 is the structural representation that in the utility model example 1, grid has depression defect;
Fig. 8 is the cutaway view of a kind of thin-film transistor structure in the utility model example 2;
Fig. 9 is the cutaway view of a kind of array base-plate structure in the utility model example 3;
Reference numeral: 1-substrate; 2-grid; 20-gate metal tunic; 21-the second photoresist layer; The pre-formed layer of 3-grid; The pre-formed tunic of 30-grid; 31-the first photoresist layer; 32-grid embedded groove; 4-gate insulation layer; 5-active layer; 6-etching barrier layer; 7-source electrode; 8-drain electrode; Pre-formed layer is leaked in 9-source; 10-passivation layer; 11-pixel electrode; 15-defect.
Embodiment
For making those skilled in the art understand better the technical solution of the utility model, below in conjunction with the drawings and specific embodiments, the utility model film transistor, array base palte and display unit are described in further detail.
A kind of thin-film transistor, comprise substrate and be arranged at grid on described substrate, the source electrode and the drain electrode that with layer, arrange and be arranged at described grid and described source electrode and described drain electrode between insulating barrier, wherein, with layer, be provided with the pre-formed layer of grid with described grid, described grid is formed in the pre-formed layer of described grid; And/or, with layer, the pre-formed layer of active leakage being set with described source electrode and described drain electrode, described source electrode and described drain electrode are formed on described source and leak in pre-formed layer.
An array base palte, comprises grid line, data wire and is arranged on the thin-film transistor in the pixel region being intersected to form by described grid line and described data wire, described thin-film transistor adopts above-mentioned thin-film transistor.
A display unit, comprises above-mentioned array base palte.
Embodiment 1:
A kind of thin-film transistor, the insulating barrier that comprises substrate and be arranged at grid on substrate, the source electrode and the drain electrode that arrange with layer and be arranged at grid with source electrode and between draining, wherein, be provided with the pre-formed layer of grid with grid with layer, grid is formed in the pre-formed layer of grid; And/or, with layer, the pre-formed layer of active leakage being set with source electrode and drain electrode, source electrode and drain electrode are formed on source and leak in pre-formed layer.
In the present embodiment, thin-film transistor is bottom gate type structure, and grid is arranged on substrate, and source electrode and drain electrode are arranged on the top of grid, and concrete is on substrate, to be disposed with grid, gate insulation layer, active layer, source electrode and drain electrode.Wherein, active layer is overlapping at least partly in orthographic projection direction with source electrode and drain electrode respectively.According to grid, specifically form the different of technique from source electrode and drain electrode, in the present embodiment, thin-film transistor specifically comprises following three kinds of structures.
As shown in Figure 2, a kind of structure of thin-film transistor is, grid 2 is arranged on substrate 1, and the pre-formed layer 3 of grid in correspondence the region that forms grid 2 and offered grid embedded groove, and grid 2 is arranged in grid embedded groove; Grid 2 tops are disposed with gate insulation layer 4, active layer 5, source electrode 7 and drain electrode 8.
As shown in Figure 3, a kind of structure of thin-film transistor is, on substrate 1, be disposed with grid 2, gate insulation layer 4, active layer 5, source is leaked pre-formed layer 9 and in correspondence, that the region that forms source electrode 7 offers source electrode embedded groove, corresponding the region that forms drain electrode 8 offers drain electrode embedded groove, source electrode 7 is arranged in source electrode embedded groove, and drain electrode 8 is arranged in drain electrode embedded groove.
Or as shown in Figure 4, a kind of structure of thin-film transistor is, grid 2 is arranged on substrate 1, and the pre-formed layer 3 of grid in correspondence the region that forms grid 2 and offered grid embedded groove, and grid 2 is arranged in grid embedded groove; Grid 2 tops are gate insulation layer 4 and active layer 5, source is leaked pre-formed layer 9 and in correspondence, that the region that forms source electrode 7 offers source electrode embedded groove, corresponding the region that forms drain electrode 8 offers drain electrode embedded groove, source electrode 7 is arranged in source electrode embedded groove, and drain electrode 8 is arranged in drain electrode embedded groove.
Wherein, in the above-mentioned thin-film transistor structure of Fig. 2-Fig. 4, the pre-formed layer 3 of grid leaks pre-formed layer 9 with source and all adopts inorganic material to form, and inorganic material comprises silicon nitride, silica or silicon oxynitride.Preferably, the thickness of grid 2 is identical with the thickness of the pre-formed layer 3 of grid, and the thickness that the thickness of source electrode 7 and drain electrode 8 leaks pre-formed layer 9 with source is identical.
In the present embodiment, grid 2 adopts molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium or copper to form.Gate insulation layer 4 is individual layer, bilayer or multilayer, adopts Si oxide, silicon nitride, hafnium oxide, silicon nitrogen oxide or aluminum oxide to form.In order to guarantee active layer 5 and the good contact of source electrode 7 with drain electrode 8, active layer 5 also further arranges ohmic contact layer with source electrode 7 and drain electrode 8, active layer 5 adopts amorphous silicon material to form, ohmic contact layer adopts the amorphous silicon material of Doping Phosphorus element to form, and the electron mobility between source electrode 7 and drain electrode 8 is relatively little; Or, in order to guarantee that active layer 5 is not damaged when forming grid 2, the top of active layer 5 also further arranges etching barrier layer 6, active layer 5 adopts metal-oxide semiconductor (MOS), for example indium oxide gallium zinc, indium zinc oxide, tin indium oxide or indium oxide gallium tin form, electron mobility between source electrode 7 and drain electrode 8 is increased, therefore can obtain the electron mobility between good source electrode 7 and drain electrode 8, etching barrier layer 6 adopts Si oxide, silicon nitride, hafnium oxide or aluminum oxide to form.Source electrode 7 and drain electrode 8 all adopt molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium or copper to form.
Accordingly, the preparation method of above-mentioned thin-film transistor, be included in the step that forms the gate insulation layer 4 between grid 2, formation source electrode 7 and drain electrode 8 and formation grid 2 and source electrode 7 and drain electrode 8 on substrate 1, also comprise and forming and the grid pre-formed layer 3 of grid 2 with layer, and grid 2 is formed on to the step in the pre-formed layer 3 of grid; And/or, comprise that forming source electrode 7 leaks pre-formed layer 9 with the sources of same layer of drain electrode 8, and by source electrode 7 and 8 steps that are formed in the pre-formed layer 9 of source leakage that drain.
In brief, corresponding diagram 2, before forming grid 2, first forms and comprises the pre-formed layer 3 of grid and the figure that is opened in the grid embedded groove in the pre-formed layer 3 of grid; Then, in grid embedded groove, form the figure that comprises grid 2.Or corresponding diagram 3, before forming source electrode 7 and drain electrode 8, first forms and comprises that source leaks pre-formed layer 9 and the source that is opened in and leak source electrode embedded groove in pre-formed layer and the figure of drain electrode embedded groove; Then, in source electrode embedded groove, form the figure that comprises source electrode 7, and form the figure that comprises drain electrode 8 in drain electrode embedded groove.Or corresponding diagram 4, before forming grid 2, first forms and comprises the pre-formed layer 3 of grid and the figure that is opened in the grid embedded groove in the pre-formed layer 3 of grid; Then, in grid embedded groove, form the figure that comprises grid 2; Meanwhile, before forming source electrode 7 and drain electrode 8, first form and comprise that source leaks pre-formed layer 9 and the source that is opened in and leak source electrode embedded groove in pre-formed layer 9 and the figure of drain electrode embedded groove; Then, in source electrode embedded groove, form the figure that comprises source electrode 7, and form the figure that comprises drain electrode 8 in drain electrode embedded groove
Thin-film transistor of the present utility model adopts composition technique to form.In composition technique of the present utility model, can only include photoetching process, or, comprise photoetching process and etch step, can also comprise printing, ink-jet etc. other are used to form the technique of predetermined pattern simultaneously; Photoetching process, refers to that utilize photoresist, mask plate, the exposure machine etc. of technical processs such as comprising film forming (or plated film), exposure, development form the technique of figure.Can be according to the corresponding composition technique of formed structure choice in the utility model.
In the present embodiment, employing composition technique forms the figure that comprises the pre-formed layer of grid and grid, forms the pre-formed layer of grid and formation grid and adopts same mask plate; Or, adopt composition technique to form the figure that comprises the pre-formed layer of grid, and adopt melting reperfusion mode that grid is formed in the pre-formed layer of grid; In like manner, can adopt the formation of composition technique to comprise the figure of the pre-formed layer of source leakage and source electrode and drain electrode, pre-formed layer is leaked in formation source and formation source electrode adopts same mask plate with drain electrode; Or employing composition technique forms the figure that comprises the pre-formed layer of source leakage, and adopt melting reperfusion mode that source electrode and drain electrode are formed in the pre-formed layer of source leakage.
In Fig. 4, the preparation method of thin-film transistor specifically comprises the steps:
Step S1): on substrate 1, form the figure that comprises grid 2.
In this step, specifically comprise following sub-step:
Step S11): first form the pre-formed tunic 30 of grid, as shown in Figure 5A.
Step S12): above the pre-formed tunic 30 of grid, form the first photoresist layer 31, as shown in Figure 5 B.
Step S13): by exposure, developing process for the first time, in the pre-formed tunic 30 of grid, form and comprise the pre-formed layer 3 of grid and the figure that is opened in the grid embedded groove 32 in the pre-formed layer of grid, as shown in Figure 5 C.
Step S14): remove the first photoresist layer 31, as shown in Figure 5 D.
Step S15): above the pre-formed layer 3 of grid and grid embedded groove 32, form gate metal tunic 20, as shown in Fig. 5 E.
Step S16): above gate metal tunic 20, form the second photoresist layer 21, as shown in Fig. 5 F.
Step S17): by exposure, developing process for the second time, retain corresponding the part of grid embedded groove 32 in gate metal tunic 20, remove other parts, thereby form the figure that comprises grid 2, as shown in Fig. 5 G.
Step S18): remove the second photoresist layer 21, as shown in Fig. 5 H.
In this step: adopt the method for deposition, sputter or thermal evaporation to form the pre-formed tunic 30 of grid or gate metal tunic 20.Wherein, the pre-formed tunic 30 of grid adopts inorganic material to form, and inorganic material comprises silicon nitride, silica or silicon oxynitride; The thickness of grid 2 is identical with the thickness of the pre-formed layer 3 of grid.
In this step, in the composition technique of the pre-formed layer 3 of grid and grid 2, adopt same mask board to explosure; Meanwhile, in order to guarantee the correctness of exposure technology figure, the preferred exposure incompatibility of photoresist in the exposure character of photoresist and the second photoresist layer 21 in the first photoresist layer 31.For example: in the first photoresist 31, photoresist is negative photoresist, in the second photoresist 21, photoresist is positive photoresist.
Above-mentioned formation comprises that the figure of the pre-formed layer of described grid and described grid is for adopting composition technique to form, a kind of preferred mode is, after the pre-formed layer 3 of grid forms, adopting melting reperfusion mode to be formed in grid embedded groove 32 (is about to pour in corresponding groove after the melting of gate metal material), can corresponding omission step S15)-step S18), the grid 2 that adopts which to form, that thickness can be made is thinner, flatness is better.
Step S2): on grid 2, form the figure that comprises gate insulation layer 4.
In this step: at completing steps S1) substrate 1 on form gate insulation layer 4.Wherein, gate insulation layer 4 can strengthen chemical vapour deposition technique formation by using plasma.
Step S3): on gate insulation layer 4, form the figure that comprises active layer 5.
In this step: at completing steps S2) substrate 1 on form compound tunic, form composite film and can adopt the methods such as deposition, sputter or thermal evaporation, compound tunic includes source tunic and is arranged at the etching barrier layer film of active tunic top (depositing successively respectively in deposition process), can utilize normal masks plate on gate insulation layer 4, to form by a composition technique figure that comprises composite bed.
Or, at completing steps S2) substrate on form the figure comprise composite bed, composite bed comprises active layer and is arranged at the ohmic contact layer of active layer top (depositing successively respectively in forming process), utilizes normal masks plate on gate insulator 4, to form by a composition technique figure that comprises composite bed.
Step S4): on active layer 5, form the figure that comprises source electrode 7 and drain electrode 8.
In this step, specifically comprise following sub-step:
Step S41): first pre-formed tunic is leaked in formation source.
Step S42): above leaking pre-formed tunic in source, form the first photoresist layer.
Step S43): by exposure, developing process for the first time, in source, leak in pre-formed tunic to form and comprise that source leaks pre-formed layer and the source that is opened in and leak source electrode embedded groove in pre-formed layer and the figure of drain electrode embedded groove.
Step S44): remove the first photoresist layer.
Step S45): above leaking pre-formed layer and source electrode embedded groove and drain electrode embedded groove in source, metal tunic is leaked in formation source.
Step S46): above leaking metal tunic in source, form the second photoresist layer.
Step S47): by exposure, developing process for the second time, the part of corresponding source electrode embedded groove and drain electrode embedded groove in metal tunic is leaked in reservation source, removes other parts, thereby forms the figure that comprises source electrode and drain electrode.
Step S48): remove the second photoresist layer.
In this step, the diagram of each concrete sub-step can comprise the process cutaway view that the figure of grid forms with reference to figure 5A-5H, omits respective drawings here.
In this step: adopt the method formation source of deposition, sputter or thermal evaporation to leak pre-formed tunic or source leakage metal tunic.Wherein, source is leaked pre-formed tunic and is adopted inorganic material to form, and inorganic material comprises silicon nitride, silica or silicon oxynitride; The thickness that the thickness of source electrode 7 and drain electrode 8 leaks pre-formed layer 9 with source is identical; Equally, the preferred exposure incompatibility of photoresist in the exposure character of photoresist and the second photoresist layer in the first photoresist layer.
In like manner, source electrode 7 and drain electrode 8 adopt melting reperfusion mode to be formed in source electrode embedded groove and drain electrode embedded groove after can leaking pre-formed layer 9 and form in source, can corresponding omission step S45)-step S48), the source electrode 7 and the drain electrode 8 that adopt which to form, that thickness can be made is thinner, flatness is better.
So far, thin-film transistor has been prepared.
In Fig. 2 and Fig. 3, the preparation method of thin-film transistor can, with reference to the concrete steps (Fig. 5 A-Fig. 5 H) of the preparation method of thin-film transistor in above-mentioned Fig. 4, repeat no more here.
With grid in the present embodiment and grid in prior art, occur that depression defect compares, in the present embodiment, form grid on substrate before, first form the pre-formed layer of grid, and form and hold and the fixing needed grid embedded groove of grid by exposure, development and etching; The grid of the pre-formed layer of formation and grid same thickness, obtains being filled into completely the grid in grid embedded groove again.Like this, in the formation technique of gate patterns, even after etch step finishes, still may exist gate surface out-of-flatness or figure sudden change place to have the situation of defect, the formation of subsequent film can further not aggravate defect yet.For example: as shown in Figure 6, when while having served as the less or exposure of quarter amount, mask plate (mask) pattern coverage area is larger, Hui etching edge generates some projections (defect 15), this protruding height is much smaller than the thickness of grid, along with the formation of subsequent film in thin-film transistor, this projection slows down gradually, and, because this projection is not in the edge of other layers, so can therefore not produce the possibility of electric leakage; Again as shown in Figure 7, while having served as the large or exposure of quarter amount, mask plate pattern coverage area hour, Hui etching edge generates some depressions (defect 15), the degree of depth of this depression is much smaller than the thickness of grid, and along with the formation of subsequent film in thin-film transistor, this depression slows down gradually, and, because this depression is not in the edge of other layers, also can therefore not produce the possibility of electric leakage, can effectively solve in prior art and cause the problem of electric leakage because defect appears in figure sudden change place.Equally, in the present embodiment, source electrode is compared with drain electrode with source electrode in prior art with drain electrode, can effectively solve in prior art and cause the problem of electric leakage because defect appears in figure sudden change place
Simultaneously, because the pre-formed layer of grid and grid adopt, same mask plate forms such scheme, source is leaked pre-formed layer and adopted same mask plate to form with source/drain, can not increase on the basis of number of masks, only respectively increase respectively that single exposure, developing process form the pre-formed layer of corresponding grid or pre-formed layer is leaked in source, just can reach the effect that effectively prevents metal electrode connection in thin-film transistor.
Embodiment 2:
The difference of the present embodiment and embodiment 1 is, the present embodiment thin-film transistor is top gate type structure.
In the present embodiment, thin-film transistor is bottom gate type structure, i.e. source electrode and drain electrode is arranged on substrate, and grid is arranged on the top of source electrode and drain electrode, and concrete is on substrate, to be disposed with source electrode and drain electrode, active layer, gate insulation layer, grid.According to grid, specifically form the different of technique from source electrode and drain electrode, reference example 1, in the present embodiment, thin-film transistor specifically comprises following three kinds of structures.
As shown in Figure 8, a kind of structure of thin-film transistor is, source is leaked pre-formed layer 9 and is formed on substrate 1 with source electrode 7 and drain electrode 8, source is leaked pre-formed layer 9 and in correspondence, that the region that forms source electrode offers source electrode embedded groove, corresponding the region that forms drain electrode offers drain electrode embedded groove, source electrode 7 is arranged in source electrode embedded groove, and drain electrode 8 is arranged in drain electrode embedded groove.The top of source electrode 7 and drain electrode 8 is disposed with respectively active layer 5, gate insulation layer 4 and grid 2.
A kind of structure of thin-film transistor is, source electrode 7 and drain electrode 8 are formed on substrate 1, the top of source electrode 7 and drain electrode 8 is disposed with respectively active layer 5, gate insulation layer 4, and the region that the pre-formed layer 3 of grid formation grid in correspondence offers grid embedded groove, and grid 2 is arranged in grid embedded groove.
A kind of structure of thin-film transistor is, source is leaked pre-formed layer 9 and is formed on substrate 1 with source electrode 7 and drain electrode 8, source is leaked pre-formed layer 9 and in correspondence, that the region that forms source electrode offers source electrode embedded groove, corresponding the region that forms drain electrode offers drain electrode embedded groove, source electrode 7 is arranged in source electrode embedded groove, and drain electrode 8 is arranged in drain electrode embedded groove; The top of source electrode 7 and drain electrode 8 is disposed with respectively active layer 5, gate insulation layer 4, and the region that the pre-formed layer 3 of grid formation grid in correspondence offers grid embedded groove, and grid 2 is arranged in grid embedded groove.
In above-mentioned thin-film transistor structure, the pre-formed layer 3 of grid leaks pre-formed layer 9 with source and all adopts inorganic material to form, and inorganic material comprises silicon nitride, silica or silicon oxynitride.Preferably, the thickness of grid 2 is identical with the thickness of the pre-formed layer 3 of grid, and the thickness that the thickness of source electrode 7 and drain electrode 8 leaks pre-formed layer 9 with source is identical.
In the thin-film transistor of the present embodiment, the material of each rete is identical with embodiment 1, and concrete preparation method also can reference example 1, repeats no more here.
Embodiment 3:
The present embodiment provides a kind of array base palte, and this array base palte comprises the thin-film transistor in embodiment 1.
In the array base palte of the present embodiment, comprise grid line, data wire and be arranged on the thin-film transistor in the pixel region being intersected to form by grid line and data wire, thin-film transistor adopts the thin-film transistor of bottom gate type in embodiment 1.
In the present embodiment, the pre-formed layer of grid also extends to pixel region correspondence and thin-film transistor other regions in addition, and grid line and grid arrange and are electrically connected to grid with layer; Or source is leaked pre-formed layer and is also extended to pixel region correspondence and other regions beyond thin-film transistor, data wire with source electrode with layer setting and be electrically connected to source electrode.
Concrete, the thin-film transistor in corresponding embodiment 1, the pre-formed layer of grid in correspondence the region that forms grid line and is offered grid line embedded groove, and grid line is arranged in grid line embedded groove; Or the region that leakage pre-formed layer in source formation data wire in correspondence offers data wire embedded groove, data wire is arranged in data wire embedded groove.Wherein, the thickness of grid equates with the thickness of grid, and the thickness of data wire equates with the thickness of source electrode.
As shown in Figure 9, array base palte in the present embodiment comprises above-mentioned thin-film transistor, also comprise passivation layer 10 and pixel electrode 11, passivation layer 10 is arranged on the top of source electrode 7 and drain electrode 8, the region that passivation layer 10 correspondences drain electrode 8 offers via hole, and passivation layer 10 adopts Si oxide, silicon nitride, hafnium oxide or aluminum oxide to form.
Certainly, the above-mentioned array base palte that is provided with pixel electrode, can form TN(Twisted Nematic, twisted-nematic) liquid crystal indicator, the VA(Vertical Alignment of pattern, vertical orientated) liquid crystal indicator of pattern; Or, continue, on the basis of above-mentioned array base palte, public electrode to be set to form ADS(ADvanced Super Dimension Switch, a senior super dimension switch technology) and the liquid crystal indicator of pattern; Or, above-mentioned array base palte is formed to OLED(Organic Light-Emitting Diode for forming the region of pixel electrode, Organic Light Emitting Diode) metal anode, to form AMOLED(Active Matrix Organic Light Emission Display, active matrix drive type organic light-emitting display device).
Accordingly, the preparation method of above-mentioned array base palte, the preparation method who comprises thin-film transistor in embodiment 1, also comprises: the pre-formed layer of grid is extended to pixel region correspondence and thin-film transistor other regions in addition, make grid line and grid form and be electrically connected to grid with layer; Or, pre-formed layer is leaked in source and also extends to pixel region correspondence and other regions beyond thin-film transistor, make data wire with source electrode with layer formation and be electrically connected to source electrode.
In brief, the pre-formed layer of grid corresponding form grid line region form grid line embedded groove, grid line is formed in grid line embedded groove; Or, in source, leak pre-formed layer corresponding form data wire region form data wire embedded groove, data wire is formed in data wire embedded groove.Wherein, the thickness of grid equates with the thickness of grid, and the thickness of data wire equates with the thickness of source electrode.
Concrete, in embodiment 1, prepared thin-film transistor, and be pre-formed on the basis of controlling grid scan line and data wire, also further comprise:
Step S5): in source electrode 7, drain electrode 8, form the figure that comprises passivation layer 10 and via hole.
In this step: at completing steps S4) substrate 1 on form passivation tunic (PVXDeposition), can utilize normal masks plate to form and comprise the figure of passivation layer 10 in source electrode 7, drain electrode 8 by a composition technique, and adopt etching mode in passivation layer 10, to form the figure that comprises via hole.Wherein, adopt the method for deposition, sputter or thermal evaporation to form passivation tunic.
Step S6): above passivation layer 10, form the figure that comprises pixel electrode 11, drain electrode 8 is connected by via hole with pixel electrode 11.
In this step, at completing steps S5) substrate 1 on form nesa coating, can utilize normal masks plate above passivation layer 10, to form by a composition technique figure that comprises pixel electrode 11, drain electrode 8 is connected by via hole with pixel electrode 11; Wherein, adopt the method for deposition, sputter or thermal evaporation to form nesa coating.
The array base palte of the present embodiment, the formation simultaneously of grid line and grid, data wire and source/drain form simultaneously, and grid line embedded groove and grid embedded groove form simultaneously, and/or, data wire embedded groove and source electrode embedded groove and drain electrode embedded groove form simultaneously, do not increasing on the basis of number of masks, just can reach the effect that effectively prevents electric leakage.
Embodiment 4:
The present embodiment provides a kind of array base palte, and this array base palte comprises the thin-film transistor in embodiment 2.
In the array base palte of the present embodiment, comprise grid line, data wire and be arranged on the thin-film transistor in the pixel region being intersected to form by grid line and data wire, thin-film transistor adopts the thin-film transistor of top gate type in embodiment 2.
In the present embodiment, the pre-formed layer of grid also extends to pixel region correspondence and thin-film transistor other regions in addition, and grid line and grid arrange and are electrically connected to grid with layer; Or source is leaked pre-formed layer and is also extended to pixel region correspondence and other regions beyond thin-film transistor, data wire with source electrode with layer setting and be electrically connected to source electrode.
Concrete, the thin-film transistor in corresponding embodiment 2, the pre-formed layer of grid in correspondence the region that forms grid line and is offered grid line embedded groove, and grid line is arranged in grid line embedded groove; Or the region that leakage pre-formed layer in source formation data wire in correspondence offers data wire embedded groove, data wire is arranged in data wire embedded groove.Wherein, the thickness of grid equates with the thickness of grid, and the thickness of data wire equates with the thickness of source electrode.
Other structures of the array base palte of the present embodiment are identical with embodiment 3, and concrete preparation method also can reference example 3, repeats no more here.
Embodiment 5:
The present embodiment provides a kind of display unit, comprises the array base palte in embodiment 3,4.This display unit can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
In the present embodiment, because the array base palte wherein adopting has the effect of the electric leakage of effectively preventing, make this display unit there is good stability and display quality preferably.
The utility model, in the preparation process of thin-film transistor, is first formed on inorganic material on substrate, by exposure, development, etching, forms the groove identical with gate patterns; Then form grid, and make the thickness of grid and the degree of depth of groove in full accord, form and to be filled to the full graphics in groove with gate metal material; And then other retes of formation thin-film transistor; And/or, make source electrode and drain electrode there is similar layer structure, this structure can effectively slow down the counter productive that grid or source electrode and drain electrode bring because of the etching defect at slope place, while relating to gate metal tunic, source leakage metal tunic deposition and etching for solution, there is less desirable defect effective especially, can fundamentally stop the discontinuous possibility of subsequent film, improve the quality of display unit.
Accordingly, the utility model is in adopting the array base palte of above-mentioned thin-film transistor, the grid line being connected with grid, the data wire that is connected with source electrode are also formed in inorganic material layer, in the increase process of subsequent film, make each conductive film layer realize reducing of margin slope area, can effectively slow down the counter productive that grid line, data wire bring because of the defect at place, slope, under the overall background progressively becoming more meticulous in pixel, making display unit obtain perfect display screen becomes possibility.
Thin-film transistor structure provided by the utility model and corresponding preparation method, can extend to various compared with in the semiconductor device structure of multiple film layer and preparation method, its core is first to form with other materials the groove of semiconductor device graph to be formed, in groove, fill and form the corresponding material of semiconductor device graph again, this preparation method need not increase number of masks, but can reduce incomplete impact the in slope that subsequent film is subject to front and continued to exist rete to exist, can effectively avoid semiconductor device to occur the possibility of electric leakage.
Be understandable that, above execution mode is only used to principle of the present utility model is described and the illustrative embodiments that adopts, yet the utility model is not limited to this.For those skilled in the art, in the situation that not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection range of the present utility model.
Claims (11)
1. a thin-film transistor, comprise substrate and be arranged at grid on described substrate, the source electrode and the drain electrode that with layer, arrange and be arranged at described grid and described source electrode and described drain electrode between insulating barrier, it is characterized in that, with layer, be provided with the pre-formed layer of grid with described grid, described grid is formed in the pre-formed layer of described grid; And/or, with layer, the pre-formed layer of active leakage being set with described source electrode and described drain electrode, described source electrode and described drain electrode are formed on described source and leak in pre-formed layer.
2. thin-film transistor according to claim 1, it is characterized in that, described grid is arranged on described substrate, described source electrode and described drain electrode are arranged on the top of described grid, the region that the pre-formed layer of described grid formation grid in correspondence offers grid embedded groove, and described grid is arranged in described grid embedded groove; And/or, described source is leaked pre-formed layer and in correspondence, that the region that forms described source electrode offers source electrode embedded groove, corresponding the region that forms described drain electrode offers drain electrode embedded groove, described source electrode is arranged in described source electrode embedded groove, and described drain electrode is arranged in described drain electrode embedded groove.
3. thin-film transistor according to claim 1, it is characterized in that, described source electrode and described drain electrode are arranged on described substrate, described grid is arranged on the top of described source electrode and described drain electrode, described source is leaked pre-formed layer and in correspondence, that the region that forms described source electrode offers source electrode embedded groove, corresponding the region that forms described drain electrode offers drain electrode embedded groove, described source electrode is arranged in described source electrode embedded groove, and described drain electrode is arranged in described drain electrode embedded groove; And/or the region that the pre-formed layer of described grid the described grid of formation in correspondence offers grid embedded groove, described grid is arranged in described grid embedded groove.
4. according to the thin-film transistor described in claim 2 or 3, it is characterized in that, the pre-formed layer of described grid leaks pre-formed layer with described source and all adopts inorganic material to form, and described inorganic material comprises silicon nitride, silica or silicon oxynitride.
5. thin-film transistor according to claim 4, is characterized in that, the thickness of described grid is identical with the thickness of the pre-formed layer of described grid, and the thickness of described source electrode and described drain electrode is identical with the thickness that pre-formed layer is leaked in described source.
6. thin-film transistor according to claim 5, it is characterized in that, between described source electrode and described drain electrode, be also provided with active layer, and described active layer is overlapping at least partly in orthographic projection direction with described source electrode and described drain electrode respectively, described active layer adopts amorphous silicon material to form; Or described active layer adopts indium oxide gallium zinc, indium zinc oxide, tin indium oxide or indium oxide gallium tin to form.
7. an array base palte, comprises grid line, data wire and is arranged on the thin-film transistor in the pixel region being intersected to form by described grid line and described data wire, it is characterized in that, described thin-film transistor adopts the thin-film transistor described in claim 1-6 any one.
8. array base palte according to claim 7, is characterized in that, the pre-formed layer of described grid also extends to described pixel region correspondence and described thin-film transistor other regions in addition, and described grid line and described grid arrange and are electrically connected to described grid with layer; Or described source is leaked pre-formed layer and is also extended to described pixel region correspondence and other regions beyond described thin-film transistor, described data wire with described source electrode with layer setting and be electrically connected to described source electrode.
9. array base palte according to claim 8, is characterized in that, the region that the pre-formed layer of described grid formation grid line in correspondence offers grid line embedded groove, and described grid line is arranged in described grid line embedded groove; Or the region that leakage pre-formed layer in described source formation data wire in correspondence offers data wire embedded groove, described data wire is arranged in described data wire embedded groove.
10. array base palte according to claim 9, is characterized in that, the thickness of described grid equates with the thickness of described grid, and the thickness of described data wire equates with the thickness of described source electrode.
11. 1 kinds of display unit, is characterized in that, comprise the array base palte described in claim 7-10 any one.
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| CN201320613545.0U CN203521430U (en) | 2013-09-30 | 2013-09-30 | Thin film transistor, array substrate, and display device |
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| CN201320613545.0U CN203521430U (en) | 2013-09-30 | 2013-09-30 | Thin film transistor, array substrate, and display device |
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| CN203521430U true CN203521430U (en) | 2014-04-02 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103489922A (en) * | 2013-09-30 | 2014-01-01 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, array substrate and preparation method thereof and display device |
| CN105633102A (en) * | 2016-04-05 | 2016-06-01 | 京东方科技集团股份有限公司 | Array substrate, film transistor, manufacturing method of display device and display device |
| CN113721432A (en) * | 2021-09-16 | 2021-11-30 | 北京京东方技术开发有限公司 | Electric control drum, manufacturing method thereof and printer |
| CN115440789A (en) * | 2022-11-09 | 2022-12-06 | 北京京东方技术开发有限公司 | Display panel and display device |
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2013
- 2013-09-30 CN CN201320613545.0U patent/CN203521430U/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103489922A (en) * | 2013-09-30 | 2014-01-01 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, array substrate and preparation method thereof and display device |
| WO2015043302A1 (en) * | 2013-09-30 | 2015-04-02 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method therefor, array substrate and preparation method therefor and display device |
| CN103489922B (en) * | 2013-09-30 | 2017-01-18 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, array substrate and preparation method thereof and display device |
| CN105633102A (en) * | 2016-04-05 | 2016-06-01 | 京东方科技集团股份有限公司 | Array substrate, film transistor, manufacturing method of display device and display device |
| CN105633102B (en) * | 2016-04-05 | 2018-11-09 | 京东方科技集团股份有限公司 | Array substrate, thin film transistor (TFT), the production method of display device, display device |
| CN113721432A (en) * | 2021-09-16 | 2021-11-30 | 北京京东方技术开发有限公司 | Electric control drum, manufacturing method thereof and printer |
| CN115440789A (en) * | 2022-11-09 | 2022-12-06 | 北京京东方技术开发有限公司 | Display panel and display device |
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