CN203502754U - Load modeling apparatus based on real time disturbance data - Google Patents
Load modeling apparatus based on real time disturbance data Download PDFInfo
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- CN203502754U CN203502754U CN201320590659.8U CN201320590659U CN203502754U CN 203502754 U CN203502754 U CN 203502754U CN 201320590659 U CN201320590659 U CN 201320590659U CN 203502754 U CN203502754 U CN 203502754U
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Abstract
Provided is a load modeling apparatus based on real time disturbance data, comprising an analog quantity signal input plate, a switch signal input plate, a collection plate, a backboard data bus respectively in connection with the analog quantity signal input plate, the switch signal input plate and the collection plate, a GPS (Global Positioning System) time setting plate and a monitoring plate respectively in connection with the collection plate, and a supervisor unit in connection with the monitoring plate through the Ethernet. According to the utility model, real time disturbance data measured on site is employed to perform load modeling; parameter identification can be performed on a static load model, a dynamic load model, a comprehensive load model and a comprehensive load model considering distribution network to obtain an optimal load model in a load model scope; the data recorded by equipment can be directly used for load modeling to provide a reasonable and realistic load model for the power grid and perform real time on-line identification on the parameters of an electric power load model; in addition, the parameters of a load model can realize data interface with the common electric power system stable calculating analysis simulation software BPA of an electrical power system.
Description
Technical field
The utility model relates to Modeling for Electric Loads, particularly relates to a kind of Modeling for Electric Loads device based on real-time noisy data.
Background technology
Power system load model is that the power of reflection practical power systems load ports and electric current are with math equation and the corresponding parameter of its port voltage and frequency variation characteristics.Load modeling is not only set up model to various concrete consumer elements, the more important thing is the relation that the power of the overall load absorption on research load bus changes with load busbar voltage and frequency variation, and describe the form of the math equation of determining this relation and parameter wherein.The Digital Simulation of modern power systems design, planning, decision-making and operation, all needs the load model that degree of accuracy is higher.Because the result that the variation of load model is calculated system transient modelling, voltage stabilization and trend has impact in various degree, under critical condition, even there is the variation of matter.And load modeling not only will obtain by one group of data fitting the structure and parameter of model, also must be with the test of echoing of other data, to verify its robustness comprehensive and to noise.Load model by the measurement data identification under a certain change in voltage remains correct under larger or less change in voltage, be extrapolation and the interpolation of load model, there is the load model of the ability of good extrapolability, interpolation ability and comprehensive description different load composition, just with practical value.
Existing load model is from key concept mostly, and adopting Utopian model is that permanent power, constant-impedance, continuous current or three's combination is as integrated load model.This coarse load model is seriously inharmonious with accurate generating and distribution model, has obviously reduced degree of accuracy and the confidence level of emulation, under critical condition, even can draw diametrically opposite conclusion.So far there is not yet based on real-time noisy data and belong to the load modeling device that method is distinguished in total body examination, the load model that this device load modeling is set up, the integrated load model that comprises static load model, dynamic load model, integrated load model, consideration distribution, and can access the Optimal Load model within the scope of selected load model, can accurately reflect multiple part throttle characteristics, its accurately load model parameters can for power system operation mode selection, simulation calculation and systems organization provide basis, there is practical value.
Summary of the invention
Technical problem to be solved in the utility model is the defect that makes up above-mentioned prior art, and a kind of load modeling device based on real-time noisy data is provided.
The feature of this load modeling device based on real-time noisy data is:
Comprise analog signals tablet, switching signal tablet, collection plate, the backboard data bus being connected with described analog signals tablet, switching signal tablet, collection plate respectively, GPS (the Global Positioning System being connected with described collection plate respectively, initialism is GPS) to time plate and monitor board, and the supervisor unit being connected with described monitor board by Ethernet.
Described supervisor unit is embedded computer, comprise embedded microprocessor, peripheral hardware equipment, embedded OS, and the load modeling application program that is solidificated in memory chip or microprocessor itself, claim again backstage management procedure, the function of backstage management procedure comprises load modeling file management, load model parameters identification, modelling verification, modeling statistics, definite value configuration, Real-Time Monitoring, checks historical record, data are preserved, load modeling data show and print.
Described load model definite value configuration is undertaken by the definite value configuration menu item of backstage management procedure, and the definite value of described load model comprises transformer station's information, line information, channel information, switching information, load model identification initial parameter value, and sampling rate.
Described load model data are kept on the hard disc of computer of described supervisor unit, the data of described load model comprise the method for operation of load model parameters, modeling bus, modeling bus, the voltage disturbance value of the electric pressure of modeling bus, modeling bus, and load modeling valid data.
Described load model parameters demonstration is by backstage management procedure interface display on the computer display of supervisor unit, and described load model parameters demonstration comprises modeling bus, modeling pattern, load model parameters value, and voltage disturbance value.
The printer that described load model parameters is printed by supervisor unit carries out, and described load model parameters is printed and comprised modeling bus, modeling pattern, load model parameters value, and voltage disturbance value.
Described simulating signal tablet, comprise multi-analog detection module, analog/digital (the Analog/Digital being connected with described multi-analog detection module, initialism is A/D) sampling module, the field programmable gate array being connected with A/D sampling module with described multi-analog detection module respectively (Field Programmable Gate Array, initialism is FPGA)-1, be separately positioned on buffer memory/isolation module and power supply detection module between described A/D sampling module and described FPGA-1, described simulating signal tablet surpasses the three-phase voltage of setting value for receiving Sudden Changing Rate on load modeling bus, the front end main-transformer output three-phase current that load modeling bus is corresponding and the load current of load modeling bus outlet.
Described multi-analog detection module, the analog signal input circuit, the simulating signal sampling that comprise cascade keep module and simulating signal multichannel to select module, by access device on outside voltage transformer (VT) summation current transformer, from the real-time disturbance analog input signal of collection in worksite, enter described multi-analog detection module, isolate conversion, filtering, by sampling, keep the sampling switch of module to take current simulating signal, by simulating signal sampling, keep module to keep current simulating signal.
Described A/D sampling module, is converted to digital signal by the real-time disturbance simulating signal in each road, is uploaded to FGPA-1 processes after gathering by backboard data bus.
Described FPGA-1 controls described A/D sampling module each road simulating signal is converted to the digital signal of 16, and image data is gathered and is directly uploaded to described FPGA-1 and processes afterwards.
Described power supply detection module, comprises that input circuit, filtration module and the power supply duplex of cascade selected module, for power supply is provided.
Described switching signal tablet, comprise multi-path light electric isolator, the reactance voltage interfered circuit being connected with described multi-path light electric isolator, first order impact damper, CPLD (Complex Programmable Logic Device, initialism is CPLD), and second level impact damper, described first order impact damper is arranged between described reactance voltage interfered circuit and described CPLD, described second level impact damper is arranged between described CPLD and described backboard data bus, described switching signal tablet is for receiving the load outlet switch signal of load current outlet under load modeling bus, switching signal on bus connection switch signal and load modeling bus, described load outlet switch signal is from the auxiliary burden outlet switch contact signal of outside access, described bus connection switch signal is from the auxiliary bus connection switch contact signal of outside access, switching signal on described load modeling bus is from the auxiliary burden modeling bus-tie circuit breaker contact signal of outside access.
Described multi-path light electric isolator, the Transistor-Transistor Logic level that the isolation of external input voltage semaphore is converted to 5V enters system, with isolating exterior input signal, disturbs.
Described reactance voltage interfered circuit, is the reactance voltage interfered circuit that comprises transient voltage twin zener dioder (Transient Voltage Suppressor, initialism is TVS), and the switching value of the system of entering is completed to reactance voltage interference function by TVS.
Described first order impact damper is four universal buffer 74LS245,32 signals are divided into 4 Zu Ba road signals, bus select signal is chosen 2 groups of data bufferings wherein through described CPLD decoding, to meet the data bus form of 16,32 road signaling switch amount data can be by system acquisition, and through core bus, this signal is delivered to collection plate by 16 bit data bus.
Described second level impact damper is two universal buffer 74LS245, to other 2 groups of data bufferings of choosing without CPLD decoding.
Described collection plate, comprise with synchronous RAM (Synchronous Random Access Memory, initialism is SRAM), read-only memory device (Read-Only Memory, initialism is ROM) digital signal processing (Digital Signal Processing, initialism is DSP) module, the sampling FPGA and the communication FPGA that are connected with described DSP module respectively, and the CPU being connected with described communication FPGA, described CPU is with Synchronous Dynamic Random Access Memory (Synchronous Dynamic Random Access Memory, initialism is SDRAM) and network interface.
Described DSP module, from backboard data bus, read discrete voltage, current data, and according to gps time, each sampled point is stamped to absolute time mark, when sampled data often expires a cycle, the discrete voltage of collection, current data are passed through to mathematical computations, obtain the effective value of voltage, electric current, and result of calculation is kept in predefined type of data structure.
Described DSP module compares according to result of calculation and the definite value that is arranged and be issued to monitor board by daemon software definite value, judges whether to meet disturbance trigger condition.
Described sampling FPGA, from analog input, gather respectively the three-phase current that main-transformer corresponding to three-phase voltage, load modeling bus load modeling bus exported, and the three-phase current of the load current of load modeling bus outlet, also from switching value tablet, gather respectively auxiliary burden outlet switch contact signal, auxiliary bus connection switch contact signal, auxiliary burden modeling bus-tie circuit breaker contact signal, and be uploaded to described DSP module.
Described communication FPGA is data communication module, and for communicating by letter between described DSP module and described CPU, described DSP module is uploaded to described CPU correlation parameter result of calculation, passes definite value to described DSP module under described CPU.
Described CPU is when meeting disturbance trigger condition, generate load modeling data file, fill in identified event structure, and result of calculation, sampled data, log-on message structure, identified event structure, load modeling file are sent to monitor board by network interface, every cycle sends once.
Described load modeling data file is the load modeling file that meets disturbance trigger condition, claims again load modeling flag event file.
It is described that to meet disturbance trigger condition as follows:
1) phase voltage sudden change:
If the three-phase voltage Sudden Changing Rate on load modeling bus surpasses specified phase voltage value U
ndefault setting value 4%, working value error be no more than setting valve ± 30%, described specified phase voltage value U
ndefault setting value arranges by backstage management procedure interface, can manual modification;
2) phase voltage is out-of-limit:
Setting valve is at (90%～110%) U
nduring scope, working value error should be no more than setting valve ± 5%:
3) phase current sudden change:
Difference of phase currents setting valve is made as 10%I
n, working value error should be no more than setting valve ± 20%, I wherein
nfor phase current ratings;
4) phase current is out-of-limit:
Setting valve is 110%I
ntime, working value error should be no more than setting valve ± 5%.When meeting above-mentioned 4 disturbance discriminant approaches, load modeling device can start record ripple, and generates load modeling data file.
Described Payload modeling data file is the load modeling file that meets load modeling data validity judgment principle.
Described load modeling data validity judgment principle is as follows:
Three-phase voltage Sudden Changing Rate on load modeling bus surpasses specified phase voltage value U
ndefault setting value 4%, and the switch of load modeling bus and front end main-transformer thereof do not trip and load outlet switch also not tripping operation, only have the data that meet this distinguishing validity rule just to can be used for load modeling.
Described identified event structure, is the event information forming when meeting disturbance trigger condition, and the object of event structure body is carried out to assignment.
Described backboard data bus be analog signals tablet, switching signal tablet, collection plate, GPS to time plate, the monitor board data bus that forms by walking the mode of backboard, described backboard provides power supply, the corresponding control signal of each circuit board, the communication interface of each circuit board, makes each circuit board complete specific function.
Described GPS to time plate, comprise FPGA-4, to time CPU and constant-temperature crystal oscillator (Oven Controlled Crystal Oscillator, initialism is OCXO), it is the synchronous clock circuit of systematic unity, be used for receiving 1PPS, target range instrument group (Inter-Range Instrumentation Group, initialism is IRIG)-B, serial time message, utilize the taming local clock of signal input time, again by the logical operation of FPGA-4, generate high-precision 1PPS, IRIG-B, 10kHz reference clock signal, 1MHz reference clock signal, after satellite-signal disappears, can accurately keep time, after satellite-signal recovers, can automatically switch to GPS to time mode.
Described monitor board, comprise with flash memory (Compact Flash, initialism is CF) card and/or the storer of hard disk and the CPU processing module of two network interfaces, described CPU processing module also comprises CPLD code translator He Ba road relay, use Peripheral Component Interconnect standard (Peripheral Component Interconnect, initialism is PCI) interface is to asynchronous interface (Host Port Interface, initialism is HPI) special-purpose bridging chip complete HPI access, by industrial standard architecture bus (Industrial Standard Architecture, initialism is ISA) transmit, again by CPLD code translator, expand described No. eight relay outputs, described monitor board receives the load modeling data of described collection plate, and load modeling data are sent to data buffer by network interface, then judge whether to meet load modeling data validity judgment principle, as met, carry out load modeling Data Format Transform, load modeling data pre-service after Data Format Transform, load model parameters identification is analyzed, load modeling data are preserved and load model parameters is preserved, and externally provide effective load modeling data by two network interfaces of CPU processing module.
Described load modeling Data Format Transform comprises with reference to GB/T22386-2008 electrical power system transient data interchange general format standard the data of recorder data file is converted to ieee standard electrical power system transient data interchange general format COMTRADE, and respective data record mode is as follows:
The A1 period: the data before the large disturbance of system starts, output raw readings waveform, be 10 cycles writing time;
The B period: system disturbance starts to the data that finish whole dynamic process, output raw readings waveform, be 500 cycles writing time, sampling rate is a kind of in 1kHz, 2kHz, 5kHz and 10kHz.
Load modeling data pre-service after described Data Format Transform, comprises dq shaft voltage, electric current after load busbar voltage, Park Transformation, and instantaneous active power, reactive power calculate.
It is on the CF of described monitor board card and/or hard disk, to preserve the method for operation of load model parameters, modeling bus, modeling bus, the voltage disturbance value of the electric pressure of modeling bus, modeling bus that described load modeling data are preserved, and load modeling valid data.
Described load model parameters identification is analyzed, be by monitor board by levenberg-marquart algorithm to static load model, dynamic load model, integrated load model, the parameter of the integrated load model of consideration distribution is carried out identification analysis, obtain selecting the Optimal Load model within the scope of load model, the load model parameters of identification is more, can increase calculated amount on the one hand, also can affect identification precision on the other hand, because the space dimensionality of identified parameters is more, searching exact solution, to obtain probability just less, only important parameter is carried out to identification, and minor parameter is directly fixed with its representative value, to guarantee the identifiability of model, improve identification speed.
It is by described monitor board, the parameter of the integrated load model of static load model, equivalent dynamic load model, integrated load model, consideration distribution to be kept on the CF card and/or hard disk of monitor board that described load model parameters is preserved.
This load modeling device adopts total body examination to distinguish method, electric load group is done as a whole, by access device on outside voltage transformer (VT) summation current transformer, from collection in worksite, measure real-time noisy data, by to the collection of described real-time noisy data and analysis, determine and meet on-the-spot actual load model structure, and go out to meet on-the-spot actual load model parameters according to the data identification of collection in worksite, there are successively following steps:
1) reception and the processing of the switching value signal of analog input signal and outside input:
By access device on outside voltage transformer (VT) summation current transformer, from the real-time disturbance analog input signal of collection in worksite, entered the multi-analog detection module of simulating signal tablet, real-time disturbance analog input signal is isolated to conversion, filtering, A/D conversion, generate real-time noisy data, be sent to backboard data bus;
Switching value signal tablet receives the switching value signal of outside input, first the signal of outside input disturbs is isolated with reactance voltage interfered circuit and is processed by photoisolator, after processing, through first order impact damper, CPLD and second level impact damper, enter data bus, finally the switching value input signal of outside input is sent to backboard data bus;
2) beat markers:
The DSP module of collection plate reads discrete voltage, current data from backboard data bus, and according to gps time, each sampled point is stamped to absolute time mark;
3) data are calculated:
When sampled data often expires a cycle, by described DSP module, discrete voltage, current data are passed through to mathematical computations, obtain the effective value of voltage, electric current, and result of calculation is kept in predefined type of data structure;
4) load modeling event identifier generates:
The DSP module of collection plate compares according to result of calculation and the definite value that is arranged and be issued to monitor board by backstage management procedure definite value, judge whether to meet disturbance trigger condition, as met, the CPU of collection plate generates load modeling data file, and on CPU, fills in identified event structure;
5) data send:
The CPU of collection plate sends to monitor board by result of calculation, sampled data, log-on message structure, identified event structure, load modeling file by the network interface of CPU, and every cycle sends once;
6) monitor board is processed the data that receive:
Monitor board receives the load modeling data that described collection plate sends, and load modeling data are sent to data buffer by network interface, then judge whether to meet load modeling data validity judgment principle, as met, the pre-service of load modeling data, load model parameters identification analysis, the load modeling data of carrying out after load modeling Data Format Transform, Data Format Transform are preserved and load model parameters preservation, and externally provide effective load modeling data by two network interfaces of CPU processing module;
Described load modeling Data Format Transform comprises with reference to GB/T22386-2008 electrical power system transient data interchange general format standard the data of recorder data file is converted to ieee standard electrical power system transient data interchange general format COMTRA/DE, and respective data record mode is as follows:
The A1 period: the data before the large disturbance of system starts, output raw readings waveform, be 10 cycles writing time;
The B period: system disturbance starts to the data that finish whole dynamic process, output raw readings waveform, be 500 cycles writing time, sampling rate is a kind of in 1kHz, 2kHz, 5kHz and 10kHz.
Load modeling data pre-service after described Data Format Transform, comprises dq shaft voltage, electric current after load busbar voltage, Park Transformation, and instantaneous active power, reactive power calculate.
It is on the CF of described monitor board card and/or hard disk, to preserve the method for operation of load model parameters, modeling bus, modeling bus, the voltage disturbance value of the electric pressure of modeling bus, modeling bus that described load modeling data are preserved, and load modeling valid data.
Described load model parameters identification is analyzed, by levenberg-marquart algorithm, the parameter of the integrated load model of static load model, dynamic load model, integrated load model, consideration distribution to be carried out to identification analysis by monitor board, obtain selecting the Optimal Load model within the scope of load model, the load model parameters of identification is more, can increase calculated amount on the one hand, also can affect identification precision on the other hand, because the space dimensionality of identified parameters is more, searching exact solution, to obtain probability just less; Only important parameter is carried out to identification, and minor parameter is directly fixed with its representative value, to guarantee the identifiability of model, improve identification speed.
It is by described monitor board, the parameter of the integrated load model of static load model, equivalent dynamic load model, integrated load model, consideration distribution to be kept on the CF card and/or hard disk of monitor board that described load model parameters is preserved.
7) supervisor cell operation
By supervisor unit, complete management and the off-line analysis to the load modeling data file of every online load modeling device, comprise load modeling file management, load model parameters identification, modelling verification, modeling statistics, definite value configuration, data preservation, Real-Time Monitoring, check historical record, load modeling data show and print.
The utility model beneficial effect is compared with prior art:
The utility model device adopts the real-time noisy data of in-site measurement to carry out load modeling, and can be to static load model, dynamic load model, integrated load model, the integrated load model of considering distribution carries out parameter identification, obtain selecting the Optimal Load model within the scope of load model, what device recorded is all directly to carry out the data of load modeling, can provide reasonable and realistic load model for electrical network, can carry out real-time online identification to electric load model parameter, and, the load model parameters that is mainly used in Model for Stability Calculation of Power System that the utility model device obtains can be realized the data-interface of analyzing the BPA of simulation software with the conventional Model for Stability Calculation of Power System of electric system, facilitate electric system simulation computational analysis.The utility model device can be widely used in transformer station, large size industrial enterprise distribution substation, its accurately load model parameters can for power system operation mode selection, simulation calculation and systems organization provide basis, there is practical value.
Accompanying drawing explanation
Fig. 1 is the compositional block diagram of the utility model embodiment;
Fig. 2 is the compositional block diagram of the analog signals tablet in Fig. 1;
Fig. 3 is the compositional block diagram of the switching value signal tablet in Fig. 1;
Fig. 4 is the compositional block diagram of the collection plate in Fig. 1;
Fig. 5 is the compositional block diagram of the monitor board in Fig. 1.
Embodiment
Below in conjunction with embodiment and contrast accompanying drawing the utility model is described.
A kind of load modeling device based on real-time noisy data as shown in Fig. 1～5, the GPS that comprise analog signals tablet, switching signal tablet, collection plate, the backboard data bus being connected with analog signals tablet, switching signal tablet, collection plate respectively, is connected respectively with described collection plate to time plate and monitor board, and the supervisor unit being connected with monitor board by Ethernet.
Supervisor unit is embedded computer, comprise embedded microprocessor, peripheral hardware equipment, embedded OS, and the load modeling application program that is solidificated in memory chip or microprocessor itself, claim again backstage management procedure, the function of backstage management procedure comprises load modeling file management, load model parameters identification, modelling verification, modeling statistics, definite value configuration, Real-Time Monitoring, checks historical record, data are preserved, load modeling data show and print.
The configuration of load model definite value is undertaken by the definite value configuration menu item of backstage management procedure, and the definite value of load model comprises transformer station's information, line information, channel information, switching information, load model identification initial parameter value, and sampling rate.
Load model data are kept on the hard disc of computer of supervisor unit, the data of load model comprise the method for operation of load model parameters, modeling bus, modeling bus, the voltage disturbance value of the electric pressure of modeling bus, modeling bus, and load modeling valid data.
Load model parameters shows that by backstage management procedure interface display, on the computer display of supervisor unit, load model parameters demonstration comprises modeling bus, modeling pattern, load model parameters value, and voltage disturbance value.
The printer that load model parameters is printed by supervisor unit carries out, and load model parameters is printed and comprised modeling bus, modeling pattern, load model parameters value, and voltage disturbance value.
Simulating signal tablet, comprise multi-analog detection module, the A/D sampling module being connected with multi-analog detection module, the FPGA-1 being connected with multi-analog detection module and A/D sampling module respectively, be separately positioned on buffer memory/isolation module and power supply detection module between A/D sampling module and FPGA-1, simulating signal tablet is exported the load current of three-phase current and the outlet of load modeling bus for the Sudden Changing Rate front end main-transformer corresponding over three-phase voltage, the load modeling bus of setting value receiving on load modeling bus.
Multi-analog detection module, the analog signal input circuit, the simulating signal sampling that comprise cascade keep module and simulating signal multichannel to select module, by access device on outside voltage transformer (VT) summation current transformer, from the real-time disturbance analog input signal of collection in worksite, enter described multi-analog detection module, isolate conversion, filtering, by sampling, keep the sampling switch of module to take current simulating signal, by simulating signal sampling, keep module to keep current simulating signal.
The chip model of A/D sampling module is AD7607, and the real-time disturbance simulating signal in each road is converted to digital signal, is uploaded to FGPA-1 processes after gathering by backboard data bus.
FPGA-1 is that model is the FPGA of EP3C5E144, and it is controlled A/D sampling module each road simulating signal is converted to the digital signal of 16, and image data is gathered and is directly uploaded to described FPGA-1 and processes afterwards.
Power supply detection module, comprises that input circuit, filtration module and the power supply duplex of cascade selected module, for power supply is provided.
Switching signal tablet, comprise multi-path light electric isolator, the reactance voltage interfered circuit being connected with multi-path light electric isolator, first order impact damper, CPLD, and second level impact damper, first order impact damper is arranged between reactance voltage interfered circuit and CPLD, second level impact damper is arranged between CPLD and backboard data bus, switching signal tablet is for receiving the load outlet switch signal of load current outlet under load modeling bus, switching signal on bus connection switch signal and load modeling bus, load outlet switch signal is from the auxiliary burden outlet switch contact signal of outside access, bus connection switch signal is from the auxiliary bus connection switch contact signal of outside access, switching signal on load modeling bus is from the auxiliary burden modeling bus-tie circuit breaker contact signal of outside access.
Multi-path light electric isolator is TLP121 device, and the Transistor-Transistor Logic level that the isolation of external input voltage semaphore is converted to 5V enters system, with isolating exterior input signal, disturbs.
Reactance voltage interfered circuit is to comprise that model is the reactance voltage interfered circuit of the TVS of P6SMB43CA, completes reactance voltage interference function to the switching value of the system of entering by TVS.
First order impact damper is eight universal buffer 74LS245,32 signals are divided into 4 Zu Ba road signals, 2 groups of data bufferings are wherein chosen in the CPLD decoding that bus select signal is EPM3032ATC44 through chip model, to meet the data bus form of 16,32 road signaling switch amount data can be by system acquisition, and through core bus, this signal is delivered to collection plate by 16 bit data bus.
Second level impact damper is two universal buffer 74LS245, to other 2 groups of data bufferings of choosing without CPLD decoding.
Collection plate, comprises the DSP module with SRAM, ROM, sampling FPGA and the communication FPGA being connected with described DSP module respectively, and the CPU being connected with communication FPGA, and CPU is with SDRAM and network interface.
The chip model of DSP module is TMS320C6713BZDP-300, it reads discrete voltage, current data from backboard data bus, and according to gps time, each sampled point is stamped to absolute time mark, when sampled data often expires a cycle, the discrete voltage of collection, current data are passed through to mathematical computations, obtain the effective value of voltage, electric current, and result of calculation is kept in predefined type of data structure.DSP module compares according to result of calculation and the definite value that is arranged and be issued to monitor board by daemon software definite value, judges whether to meet disturbance trigger condition.
Sampling FPGA is that model is the FPGA of EP3C10F25617N, it gathers respectively from analog input the three-phase current that main-transformer corresponding to three-phase voltage, load modeling bus load modeling bus exported, and the three-phase current of the load current of load modeling bus outlet, also from switching value tablet, gather respectively auxiliary burden outlet switch contact signal, auxiliary bus connection switch contact signal, auxiliary burden modeling bus-tie circuit breaker contact signal, and be uploaded to DSP module.
Communication FPGA is that model is the data communication module of EP2C8, and for communicating by letter between DSP module and CPU, DSP module is uploaded to CPU correlation parameter result of calculation, passes definite value to DSP module under CPU.
The chip model of CPU is X86, it is when meeting disturbance trigger condition, generate load modeling data file, fill in identified event structure, and result of calculation, sampled data, log-on message structure, identified event structure, load modeling file are sent to monitor board by network interface, every cycle sends once.
Load modeling data file is the load modeling file that meets disturbance trigger condition, claims again load modeling flag event file, meets disturbance trigger condition as follows:
1) phase voltage sudden change:
If the three-phase voltage Sudden Changing Rate on load modeling bus surpasses specified phase voltage value U
ndefault setting value 4%, working value error be no more than setting valve ± 30%, specified phase voltage value U
ndefault setting value arranges by backstage management procedure interface, can manual modification;
2) phase voltage is out-of-limit:
Setting valve is at (90%～110%) U
nduring scope, working value error should be no more than setting valve ± 5%:
3) phase current sudden change:
Difference of phase currents setting valve is made as 10%I
n, working value error should be no more than setting valve ± 20%, I wherein
nfor phase current ratings;
4) phase current is out-of-limit:
Setting valve is 110%I
ntime, working value error should be no more than setting valve ± 5%.When meeting above-mentioned 4 disturbance discriminant approaches, load modeling device can start record ripple, and generates load modeling data file.
Payload modeling data file is the load modeling file that meets load modeling data validity judgment principle, and load modeling data validity judgment principle is as follows:
Three-phase voltage Sudden Changing Rate on load modeling bus surpasses specified phase voltage value U
ndefault setting value 4%, and the switch of load modeling bus and front end main-transformer thereof do not trip and load outlet switch also not tripping operation, only have the data that meet this distinguishing validity rule just to can be used for load modeling.
Identified event structure is the event information forming when meeting disturbance trigger condition, and the object of event structure body is carried out to assignment.
Backboard data bus be analog signals tablet, switching signal tablet, collection plate, GPS to time plate, the monitor board data bus that forms by walking the mode of backboard, backboard provides power supply, the corresponding control signal of each circuit board, the communication interface of each circuit board, makes each circuit board complete specific function.
GPS to time plate, comprise chip model be FPGA-4, the chip model of EP2C8 be W77E58A40PL to time CPU and OCXO, it is the synchronous clock circuit of systematic unity, be used for receiving 1PPS, IRIG-B, serial time message, utilize the taming local clock of signal input time, again by the logical operation of FPGA-4, generate high-precision 1PPS, IRIG-B, 10kHz reference clock signal, 1MHz reference clock signal, after satellite-signal disappears, can accurately keep time, after satellite-signal recovers, can automatically switch to GPS to time mode.
Monitor board, comprise the CPU processing module that the chip model with the storer of CF card and/or hard disk and two network interfaces is EmETX-i2900, CPU processing module also comprises CPLD code translator He Ba road relay, use pci interface to complete HPI access to the special-purpose bridging chip PCI9054 of HPI, by ISA, transmit, again by CPLD code translator, expand No. eight relay outputs, monitor board receives the load modeling data of collection plate, and load modeling data are sent to data buffer by network interface, then judge whether to meet load modeling data validity judgment principle, as met, carry out load modeling Data Format Transform, load modeling data pre-service after Data Format Transform, load model parameters identification is analyzed, load modeling data are preserved and load model parameters is preserved, and externally provide effective load modeling data by two network interfaces of CPU processing module.
This embodiment adopts total body examination to distinguish method, electric load group is done as a whole, by access device on outside voltage transformer (VT) summation current transformer, from collection in worksite, measure real-time noisy data, by to the collection of described real-time noisy data and analysis, determine and meet on-the-spot actual load model structure, and go out to meet on-the-spot actual load model parameters according to the data identification of collection in worksite, there are successively following steps:
1) reception and the processing of the switching value signal of analog input signal and outside input:
By access device on outside voltage transformer (VT) summation current transformer, from the real-time disturbance analog input signal of collection in worksite, entered the multi-analog detection module of simulating signal tablet, real-time disturbance analog input signal is isolated to conversion, filtering, A/D conversion, generate real-time noisy data, be sent to backboard data bus;
Switching value signal tablet receives the switching value signal of outside input, first the signal of outside input disturbs is isolated with reactance voltage interfered circuit and is processed by photoisolator, after processing, through first order impact damper, CPLD and second level impact damper, enter data bus, finally the switching value input signal of outside input is sent to backboard data bus;
2) beat markers:
The DSP module of collection plate reads discrete voltage, current data from backboard data bus, and according to gps time, each sampled point is stamped to absolute time mark;
3) data are calculated:
When sampled data often expires a cycle, by DSP module, discrete voltage, current data are passed through to mathematical computations, obtain the effective value of voltage, electric current, and result of calculation is kept in predefined type of data structure;
4) load modeling event identifier generates:
The DSP module of collection plate compares according to result of calculation and the definite value that is arranged and be issued to monitor board by backstage management procedure definite value, judge whether to meet disturbance trigger condition, as met, the CPU of collection plate generates load modeling data file, and on CPU, fills in identified event structure;
5) data send:
The CPU of collection plate sends to monitor board by result of calculation, sampled data, log-on message structure, identified event structure, load modeling file by the network interface of CPU, and every cycle sends once;
6) monitor board is processed the data that receive:
Monitor board receives the load modeling data that collection plate sends, and load modeling data are sent to data buffer by network interface, then judge whether to meet load modeling data validity judgment principle, as met, the pre-service of load modeling data, load model parameters identification analysis, the load modeling data of carrying out after load modeling Data Format Transform, Data Format Transform are preserved and load model parameters preservation, and externally provide effective load modeling data by two network interfaces of CPU processing module;
Load modeling Data Format Transform comprises with reference to GB/T22386-2008 electrical power system transient data interchange general format standard the data of recorder data file is converted to ieee standard electrical power system transient data interchange general format COMTRADE, and respective data record mode is as follows:
The A1 period: the data before the large disturbance of system starts, output raw readings waveform, be 10 cycles writing time;
The B period: system disturbance starts to the data that finish whole dynamic process, output raw readings waveform, be 500 cycles writing time, sampling rate is a kind of in 1kHz, 2kHz, 5kHz and 10kHz.
Load modeling data pre-service after Data Format Transform, comprises dq shaft voltage, electric current after load busbar voltage, Park Transformation, and instantaneous active power, reactive power calculate.
It is on the CF of monitor board card and/or hard disk, to preserve the method for operation of load model parameters, modeling bus, modeling bus, the voltage disturbance value of the electric pressure of modeling bus, modeling bus that load modeling data are preserved, and load modeling valid data.
Load model parameters identification is analyzed, be by monitor board by levenberg-marquart algorithm to static load model, dynamic load model, integrated load model, the parameter of the integrated load model of consideration distribution is carried out identification analysis, obtain selecting the Optimal Load model within the scope of load model, the load model parameters of identification is more, can increase calculated amount on the one hand, also can affect identification precision on the other hand, because the space dimensionality of identified parameters is more, searching exact solution, to obtain probability just less, only important parameter is carried out to identification, and minor parameter is directly fixed with its representative value, to guarantee the identifiability of model, improve identification speed.
The important parameter of static load model is as follows:
A
p: constant-impedance accounts for the number percent of active power;
B
p: continuous current accounts for the number percent of active power;
A
q: constant-impedance accounts for the number percent of reactive power;
B
q: continuous current accounts for the number percent of reactive power.
The minor parameter of static load model is as follows:
C
p: permanent power accounts for the number percent of active power;
C
q: permanent power accounts for the number percent of reactive power.
The important parameter of equivalent dynamic load model is as follows:
X
s: stator reactance;
S
0: initial slippage;
H: inertia time constant.
The minor parameter of equivalent dynamic load model is as follows:
R
s: fixed value resistance;
X
r: rotor reactance;
R
r: rotor resistance;
X
m: excitatory reactance;
A: torque equation constant;
B: torque equation constant.
The important parameter of integrated load model is as follows:
K
pm: sound scale-up factor;
X
s: stator reactance;
S
0: initial slippage;
H: inertia time constant.
The minor parameter of integrated load model is as follows:
R
s: fixed value resistance;
X
r: rotor reactance;
R
r: rotor resistance;
X
m: excitatory reactance;
A: torque equation constant;
B: torque equation constant;
A
p: constant-impedance accounts for the number percent of active power;
B
p: continuous current accounts for the number percent of active power;
A
q: constant-impedance accounts for the number percent of reactive power;
B
q: continuous current accounts for the number percent of reactive power;
C
p: permanent power accounts for the number percent of active power;
C
q: permanent power accounts for the number percent of reactive power.
The important parameter of the integrated load model of consideration distribution is as follows:
K
pm: sound scale-up factor;
X
s: stator reactance;
S
0: initial slippage;
H: inertia time constant;
X
d: the reactance of power distribution network branch road.
The minor parameter of the integrated load model of consideration distribution is as follows:
R
d: power distribution network branch road resistance;
R
s: fixed value resistance;
X
r: rotor reactance;
R
r: rotor resistance;
X
m: excitatory reactance;
A: torque equation constant;
B: torque equation constant;
A
p: constant-impedance accounts for the number percent of active power;
B
p: continuous current accounts for the number percent of active power;
A
q: constant-impedance accounts for the number percent of reactive power;
B
q: continuous current accounts for the number percent of reactive power;
C
p: permanent power accounts for the number percent of active power;
C
q: permanent power accounts for the number percent of reactive power.
It is by monitor board, the parameter of the integrated load model of static load model, equivalent dynamic load model, integrated load model, consideration distribution to be kept on the CF card and/or hard disk of monitor board that load model parameters is preserved.
7) supervisor cell operation
By supervisor unit, complete management and the off-line analysis to the load modeling data file of every online load modeling device, comprise load modeling file management, load model parameters identification, modelling verification, modeling statistics, definite value configuration, data preservation, Real-Time Monitoring, check historical record, load modeling data show and print.
The configuration of load model definite value is undertaken by the definite value configuration menu item of backstage management procedure, and the definite value of load model comprises transformer station's information, line information, channel information, switching information, load model identification initial parameter value, and sampling rate.
Load model data are kept on the hard disc of computer of supervisor unit, the data of load model comprise the method for operation of load model parameters, modeling bus, modeling bus, the voltage disturbance value of the electric pressure of modeling bus, modeling bus, and load modeling valid data.
Load model parameters shows that by backstage management procedure interface display, on the computer display of supervisor unit, load model parameters demonstration comprises modeling bus, modeling pattern, load model parameters value, and voltage disturbance value.
The printer that load model parameters is printed by supervisor unit carries out, and load model parameters is printed and comprised modeling bus, modeling pattern, load model parameters value, and voltage disturbance value.
Above content is in conjunction with concrete preferred implementation further detailed description of the utility model, can not assert that concrete enforcement of the present utility model is confined to these explanations.For the utility model person of an ordinary skill in the technical field; make without departing from the concept of the premise utility some alternative or obvious modification that are equal to; and performance or purposes identical, all should be considered as belonging to the utility model by the definite scope of patent protection of submitted to claims.
Claims (10)
1. the load modeling device based on real-time noisy data, is characterized in that:
Comprise analog signals tablet, switching signal tablet, collection plate, respectively with described analog signals tablet, switching signal tablet, the backboard data bus that collection plate connects, the global position system GPS being connected with described collection plate respectively to time plate and monitor board, and the supervisor unit being connected with described monitor board by Ethernet, described supervisor unit is embedded computer, comprise embedded microprocessor, peripheral hardware equipment, embedded OS, and the load modeling application program that is solidificated in memory chip or microprocessor itself, claim again backstage management procedure,
Described simulating signal tablet, comprises multi-analog detection module, the analog/digital A/D sampling module being connected with described multi-analog detection module, on-site programmable gate array FPGA-1 being connected with described multi-analog detection module and A/D sampling module respectively, is separately positioned on buffer memory/isolation module and power supply detection module between described A/D sampling module and described FPGA-1;
Described switching signal tablet, comprise multi-path light electric isolator, the reactance voltage interfered circuit, first order impact damper, the complex programmable logic device (CPLD) that are connected with described multi-path light electric isolator, and second level impact damper, described first order impact damper is arranged between described reactance voltage interfered circuit and described CPLD, and described second level impact damper is arranged between described CPLD and described backboard data bus;
Described collection plate, comprise with the digital signal processing DSP module of synchronous RAM SRAM, read-only memory device ROM, the sampling FPGA and the communication FPGA that are connected with described DSP module respectively, and the CPU being connected with described communication FPGA, described CPU is with Synchronous Dynamic Random Access Memory SDRAM and network interface;
Described backboard data bus be analog signals tablet, switching signal tablet, collection plate, GPS to time plate, the monitor board data bus that forms by walking the mode of backboard;
Described GPS to time plate, comprise FPGA-4, to time CPU and constant-temperature crystal oscillator OCXO, be the synchronous clock circuit of systematic unity;
Described monitor board, comprises that described CPU processing module also comprises CPLD code translator He Ba road relay with the CPU processing module of storer and two network interfaces of flash memory CF card and/or hard disk.
2. the load modeling device based on real-time noisy data as claimed in claim 1, is characterized in that:
Described multi-analog detection module, comprises that analog signal input circuit, the simulating signal sampling of cascade keeps module and simulating signal multichannel to select module.
3. the load modeling device based on real-time noisy data as claimed in claim 1 or 2, is characterized in that:
The chip model of described A/D sampling module is AD7607.
4. the load modeling device based on real-time noisy data as claimed in claim 3, is characterized in that:
Described FPGA-1 is that model is the FPGA of EP3C5E144.
5. the load modeling device based on real-time noisy data as claimed in claim 4, is characterized in that:
Described power supply detection module, comprises that input circuit, filtration module and the power supply duplex of cascade selected module.
6. the load modeling device based on real-time noisy data as claimed in claim 5, is characterized in that:
Described multi-path light electric isolator is TLP121 device;
Described reactance voltage interfered circuit is the reactance voltage interfered circuit that comprises transient voltage twin zener dioder TVS.
7. the load modeling device based on real-time noisy data as claimed in claim 6, is characterized in that:
Described first order impact damper is four universal buffer 74LS245;
Described second level impact damper is two universal buffer 74LS245.
8. the load modeling device based on real-time noisy data as claimed in claim 7, is characterized in that:
The chip model of described DSP module is TMS320C6713BZDP-300.
9. the load modeling device based on real-time noisy data as claimed in claim 8, is characterized in that:
Described sampling FPGA is that model is the FPGA of EP3C10F25617N;
Described communication FPGA is that model is the data communication module of EP2C8.
10. the load modeling device based on real-time noisy data as claimed in claim 9, is characterized in that:
The chip model of described CPU is X86.
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| CN115902387A (en) * | 2023-02-15 | 2023-04-04 | 北京志翔科技股份有限公司 | Test tool and test method for load identification module |
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| CN115902387A (en) * | 2023-02-15 | 2023-04-04 | 北京志翔科技股份有限公司 | Test tool and test method for load identification module |
| CN115902387B (en) * | 2023-02-15 | 2023-06-06 | 北京志翔科技股份有限公司 | Test fixture and test method of load identification module |
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