CN203466168U - Bearing platform for compatibility test of semiconductor wafer - Google Patents
Bearing platform for compatibility test of semiconductor wafer Download PDFInfo
- Publication number
- CN203466168U CN203466168U CN201320603338.7U CN201320603338U CN203466168U CN 203466168 U CN203466168 U CN 203466168U CN 201320603338 U CN201320603338 U CN 201320603338U CN 203466168 U CN203466168 U CN 203466168U
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- CN
- China
- Prior art keywords
- microscope carrier
- semiconductor wafer
- bearing platform
- compatibility test
- annular
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
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Abstract
The utility model provides a bearing platform for a compatibility test of a semiconductor wafer and helps to solve the problems that at present, when tests are performed on semiconductor wafers with different sizes in the same machine, corresponding bearing platforms need to be replaced based on the sizes of the semiconductor wafers, so that the changing process is time-consuming and labor-consuming, and the production efficiency is influenced, and the edges of the semiconductor wafers are contaminated easily when the semiconductor wafers are being fixed and the like. According to the bearing platform for the compatibility test of the semiconductor wafer, the bearing platform is in a circle shape, and the center of circle is provided with an axle hole; the back surface of the bearing platform is a plane, and the front surface of the bearing platform is formed by annular steps with the axle hole being as the center of the circle; the annular steps comprise multiple stages of steps, wherein the steps comprise annular planes and annular vertical surfaces; and the number of the steps increases progressively from the circumference of the axle hole to the circumference of the bearing platform.
Description
Technical field
The utility model relates to a kind of microscope carrier, particularly a kind of semiconductor wafer compatibility test microscope carrier.
Background technology
Semiconductor wafer generally dimensions has 3 inches, 4 inches and 6 inches etc., at present, when same board is tested the semiconductor wafer of different size, need to change corresponding microscope carrier according to the size of semiconductor wafer, changing a microscope carrier generally needs 5～10 minutes, wastes time and energy; When the semiconductor wafer of producing especially at the same time different size need to be tested, the number of times of changing microscope carrier is more frequent, has a strong impact on production efficiency.
Test microscope carrier is originally in order to prevent semiconductor wafer landing, adopted the design of three Bolt to positions, during use, silicon carbide wafer has been put into microscope carrier, rotated three bolts semiconductor wafer is clamped, such design easily causes the contamination of edge of semiconductor wafer, affects the yields of product; For this deficiency, designed a kind of microscope carrier with vacuum cup, but this microscope carrier need to install the relevant auxiliary facility of vacuum additional, cost is higher.
Utility model content
The utility model proposes a kind of semiconductor wafer compatibility test microscope carrier, when having solved current same board the semiconductor wafer of different size tested, need to change corresponding microscope carrier according to the size of semiconductor wafer, waste time and energy, affect production efficiency, and fixedly easily cause the problems such as edge of semiconductor wafer contamination during semiconductor wafer.
The technical solution of the utility model is achieved in that
A semiconductor wafer compatibility test microscope carrier, described microscope carrier is rounded, and circle centre position offers an axis hole;
The back side of described microscope carrier is plane, positive by take the ring-shaped step that described axis hole is the center of circle, forms; Described ring-shaped step comprises multistage ladder, and described ladder comprises planar annular and annular vertical plane;
The quantity of described ladder increases progressively along the circumference of the circumferential described microscope carrier of described axis hole.
Further, described microscope carrier front offers a groove along radial direction.
Further, the width of described groove and the diameter length of described axis hole are consistent.
Further, described ring-shaped step comprises level Four ladder.
From above-mentioned, to description of the present utility model, compared to the prior art, the utlity model has following advantage:
One, the utility model is when testing the semiconductor wafer of different size, do not need to change the microscope carrier of corresponding size, only need directly semiconductor wafer to be placed in the groove of corresponding ring-shaped step formation the time of having saved original replacing microscope carrier, the operating efficiency of raising equipment.
Two, original microscope carrier, in order to prevent semiconductor wafer landing, has adopted the design of three Bolt to positions, and the shortcoming of this design is exactly the contamination that easily causes edge of semiconductor wafer; The utility model adopts ring-shaped step design, both can guarantee that semiconductor wafer can landing when microscope carrier moves, and has avoided again the contamination of edge of semiconductor wafer, has improved the quality of semiconductor wafer, has improved the yields of product.
Three, the utility model adopts the material of the lightweights such as aluminum or aluminum alloy, hard to make conventionally, and moulding is simply easy to process, with low cost.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the utility model Facad structure schematic diagram;
Fig. 2 is the utility model cross-sectional view.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
See figures.1.and.2, a kind of semiconductor wafer compatibility test microscope carrier, described microscope carrier 1 is rounded, and circle centre position offers an axis hole 2, and in the convenient test of described axis hole 2, microscope carrier 1 takes; The back side of described microscope carrier 1 is plane, positive by take the ring-shaped step 3 that described axis hole is the center of circle, forms; Described ring-shaped step 3 comprises multistage ladder, and described ladder comprises planar annular 30 and annular vertical plane 31; The quantity of described ladder increases progressively along the circumference of the circumferential described microscope carrier 1 of described axis hole 2.
Described microscope carrier front offers a groove 4 along radial direction, and the width of described groove 4 is consistent with the diameter length of described axis hole.Before test, first semiconductor wafer is picked up from the back side with inhaling pen, semiconductor wafer is faced up and is positioned on microscope carrier 1, now inhale pen and rest in groove 4, along groove 4 directions, extract out and inhale pen; After test, along groove 4, suction pen is stretched into semiconductor wafer bottom and picked up; Completed thus picking and placeing of semiconductor wafer.
In the present embodiment, described ring-shaped step 3 comprises level Four ladder, level Four ladder comprises four annular terraces 30 and four annular vertical planes 31 altogether, and the diameter of described microscope carrier three annular terraces is from inside to outside that the semiconductor chip of 3 inches, 4 inches and 6 inches is suitable with diameter respectively; In test process, no longer need to change microscope carrier, only tested semiconductor wafer need be placed on corresponding annular terrace.Certainly, those skilled in the art can select annular terrace quantity to be arranged to four as required, and the diameter of four annular terraces is from inside to outside suitable with the diameter of required four semiconductor chips respectively; In like manner, those skilled in the art can be arranged to the quantity of annular terrace five, six or more according to actual needs; Only need reach the semiconductor chip that same test microscope carrier can be tested a plurality of different sizes.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all within spirit of the present utility model and principle, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection range of the present utility model.
Claims (4)
1. a semiconductor wafer compatibility test microscope carrier, it is characterized in that: described microscope carrier is rounded, and circle centre position offers an axis hole;
The back side of described microscope carrier is plane, positive by take the ring-shaped step that described axis hole is the center of circle, forms; Described ring-shaped step comprises multistage ladder, and described ladder comprises planar annular and annular vertical plane;
The quantity of described ladder increases progressively along the circumference of the circumferential described microscope carrier of described axis hole.
2. a kind of semiconductor wafer compatibility test microscope carrier as claimed in claim 1, is characterized in that: described microscope carrier front offers a groove along radial direction.
3. a kind of semiconductor wafer compatibility test microscope carrier as claimed in claim 2, is characterized in that: the width of described groove is consistent with the diameter length of described axis hole.
4. a kind of semiconductor wafer compatibility test microscope carrier as claimed in claim 1, is characterized in that: described ring-shaped step comprises level Four ladder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320603338.7U CN203466168U (en) | 2013-09-22 | 2013-09-22 | Bearing platform for compatibility test of semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320603338.7U CN203466168U (en) | 2013-09-22 | 2013-09-22 | Bearing platform for compatibility test of semiconductor wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203466168U true CN203466168U (en) | 2014-03-05 |
Family
ID=50178514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320603338.7U Withdrawn - After Issue CN203466168U (en) | 2013-09-22 | 2013-09-22 | Bearing platform for compatibility test of semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203466168U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103474371A (en) * | 2013-09-22 | 2013-12-25 | 瀚天天成电子科技（厦门）有限公司 | Semi-conductor chip compatibility test carrying platform and using method thereof |
-
2013
- 2013-09-22 CN CN201320603338.7U patent/CN203466168U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103474371A (en) * | 2013-09-22 | 2013-12-25 | 瀚天天成电子科技（厦门）有限公司 | Semi-conductor chip compatibility test carrying platform and using method thereof |
| CN103474371B (en) * | 2013-09-22 | 2016-06-29 | 瀚天天成电子科技（厦门）有限公司 | A kind of semiconductor wafer compatibility test microscope carrier and using method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20140305 Effective date of abandoning: 20160629 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20140305 Effective date of abandoning: 20160629 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |