CN203455884U - Access redundancy control system - Google Patents

Access redundancy control system Download PDF

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Publication number
CN203455884U
CN203455884U CN201320546884.1U CN201320546884U CN203455884U CN 203455884 U CN203455884 U CN 203455884U CN 201320546884 U CN201320546884 U CN 201320546884U CN 203455884 U CN203455884 U CN 203455884U
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China
Prior art keywords
control system
main frame
standby host
redundancy control
gate inhibition
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Expired - Fee Related
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CN201320546884.1U
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Chinese (zh)
Inventor
庄虹
张振亮
张君华
陈良
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Suzhou Sigma Technology Co ltd
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SUZHOU YUANCHENG INTELLIGENCE TECHNOLOGY Co Ltd
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Abstract

The utility model discloses an access redundancy control system. The access redundancy control system comprises a host computer, a standby computer and a universal asynchronous transceiving transmitter, wherein the host computer with the same structure as the standby computer comprises a power supply, and a processor, a clock chip, two CAN (Controller Area Network) transceiver interface chips which are electrically connected with the power supply; the output voltage of the power supply is 3.3V; the host computer and the standby computer are connected with a local controller through a CAN bus, and are connected with each other through the universal asynchronous transceiving transmitter; one heartbeat cable led out from the host computer through an IO (Input/output) port is connected to the standby computer, and another heartbeat cable led out from the standby computer through an IO (Input/output) port is connected to the host computer; the processor is electrically connected with a Flash chip. When a main controller malfunctions, a redundancy backup controller in the access redundancy control system can immediately take over control, thereby ensuring the continuous correct running of an access control system.

Description

A kind of gate inhibition's redundancy control system
Technical field
The utility model relates to a kind of access control system of track traffic.
Background technology
At present, due to the high request of track traffic to gate control system, requirement when general gate inhibition's design proposal is difficult to meet gate inhibition and breaks down in safety and reliability, therefore, market is huge to the solution demand when track traffic gate inhibition is broken down.
Summary of the invention
For the problems referred to above, the purpose of this utility model is to provide a kind of when track traffic gate inhibition is broken down, and can guarantee the normal access control system using of gate inhibition.
For achieving the above object, the utility model adopts following technical scheme:
Gate inhibition's redundancy control system, comprises main frame, standby host and universal asynchronous receiving-transmitting transmitter, and described main frame is identical with standby host structure, comprises power supply, and 2 of the processors being electrically connected to power supply, clock chip, CAN transceiver interface chip,
Described electric power output voltage is 3.3V,
Described main frame is connected with Local Controller by CAN bus with standby host,
Between described main frame and standby host, by universal asynchronous receiving-transmitting transmitter, be connected,
Described main frame and standby host are drawn respectively by general purpose I/O port the wire jumper of uniting as one and are connected to the other side above, and described processor is electrically connected with Flash chip.
As the further optimization of such scheme, described CAN bus medium is twisted-pair feeder or concentric cable or light transmitting fiber.
As the further optimization of such scheme, described CAN bus and Local Controller adopt winding connection method to be connected, and interface is CAN transceiver interface, so that main frame sends instruction to Local Controller, obtain the communications status with Local Controller simultaneously.
As the further optimization of such scheme, described Flash chip-stored space is 12~20M,
Described Flash chip-stored space is 2~4, in order to ensure enough large storage space.
The time of main frame of described clock chip periodic calibration and standby host, as the time every main frame of calibration in 1 hour and standby host.
The beneficial effects of the utility model main manifestations is: gate inhibition's redundant manipulator of the specific (special) requirements design based on track traffic gate inhibition, when master controller breaks down, the backup controller of redundancy can be taken over control immediately, guarantees the lasting true(-)running of gate control system.
Accompanying drawing explanation
Fig. 1 is that the utility model structure forms schematic diagram.
Fig. 2 is the utility model process flow diagram that main frame/standby host identity is switched when gate inhibition is abnormal.
Internal work flow process figure when Fig. 3 is the utility model operation.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment, the utility model will be further described.
With reference to Fig. 1, shown in 2 and 3, a kind of gate inhibition's redundancy control system of the utility model, comprise main frame, standby host and universal asynchronous receiving-transmitting transmitter, described main frame is identical with standby host structure, comprise power supply, and the processor being electrically connected to power supply, clock chip, 2 of CAN transceiver interface chips, described electric power output voltage is 3.3V, described main frame is connected with Local Controller by CAN bus with standby host, between described main frame and standby host, by universal asynchronous receiving-transmitting transmitter, be connected, described main frame and standby host are drawn respectively by general purpose I/O port the wire jumper of uniting as one and are connected on the other side, described processor is electrically connected with Flash chip.
Described CAN bus medium is twisted-pair feeder or concentric cable or light transmitting fiber.
Described CAN bus adopts winding connection method to be connected with Local Controller.
Described Flash chip-stored space is 16M, and described Flash chip is 2.
Described clock chip is every the time of main frame of calibration in 1 hour and standby host.
Main frame of the present utility model and standby host, by ICP/IP protocol and server communication, are communicated by letter with Local Controller by CAN bus.Access control system adopts Redundancy Design, and when chance failure appears in main frame, what standby host was can be immediately seamless connects, and guarantees the normal of front end door access control function.Can send alarm, prompting message processing to background computer simultaneously.In places such as nuclear power station, power plant, if control system paralysis will cause significant impact, can this difficult problem of fine solution but have the access control system of redundancy feature.
For Rail Door access control system, reliabilty and availability is two very important indexs.In order to meet these index requests, improving on the basis of gate control system absolute reliability, in system or structure, taking some Redundancy Design is also the important measures that improve entire system reliabilty and availability.As shown in Figure 1, mutually redundant main frame and standby host adopt identical structure to the utility model, are connected, by network and server communication by CAN bus with Local Controller.During normal operation, active and standby machine receives data CAN bus simultaneously, but only has main frame can pass through CAN bus to external transport instruction and control data.
Between active and standby machine, by asynchronous receiving-transmitting transmitter (UART), be connected, realize between two-shipper data monitoring and the function such as synchronous.General purpose I/O port (GPIO mouth) at main frame and standby host is drawn respectively " heartbeat " line, and main frame regularly sends pulse signal, and standby host is used for checking whether judgement possesses basic service ability to method, apparatus.When two-shipper switches, by arbitraling logic circuit, change the power on duty of dual systems, the blocked operation of completion system.
During native system operation, state is divided into three kinds:
1. when system starts, main frame and standby host authority are processed
First initialization system, waiting for server distributing IP then, the controller that first obtains IP is main frame, and to notify another controller switching be standby host.
2. master-slave swap while extremely occurring, as shown in Figure 2
Once main frame sends IO(I/O port) heartbeat signal is abnormal, and standby host is read main frame running status and error message and is switched to main frame by UART, informs that original host switches to standby host, then announcement server.If UART occur communication abnormality standby host directly switch to main frame announcement server, server switches to standby host by control original host.
3. system normal operating condition.
System is without extremely, and main frame completes and communicates by letter and control with server and Local Controller with standby host.
The function that in native system, kernel program is realized is as follows:
1. controller (main frame and standby host) program is identical, and main frame and standby host are realized monitoring and synchronous by IO heartbeat and UART at ordinary times, and main frame and slave be access switch all, but only has main frame to communicate by letter with host computer, and standby host is only intercepted and responded.
2. when flat, only main frame receives CAN data, and slave (standby host) does not receive CAN data.
3. can distinguish main frame, standby host or unit work, and preserve abnormal front data
4. data have synchronously mainly adopted two kinds of mechanism: static synchronous and dynamic synchronization mechanism.
<1> static synchronous mechanism.The sector state of each flash chip represents with the zone bit of a byte.In mainframe program, the synchronous Detection task of data constantly detects main frame flash chip zone bit, if sector has data sector data to be synchronized to standby host.And by the sector label position 1 of synchronously crossing.If synchronously completing, all sectors stop this task, unless that standby host is replaced by is new, and this task again.
<2> dynamic synchronization mechanism.When the data of a certain sector change, record the numbering of this sector, add synchronous task queue to wait for synchronous, when task reaches 7 in queue, synchronize the data of these sectors with standby host.
Wherein dynamic synchronization mechanism can real main frame and the real-time synchronization of the existing data of standby host, and static synchronous mechanism can guarantee when standby host is changed or other are abnormal to guarantee that standby host is consistent with host data.
5. the operational scheme after native system energising is shown in Fig. 3, first system and hardware device-controller are carried out to initialization, then from Flash, read configuration information data, the active and standby machine right assignment of IP " identity " acquisition of information of sending according to server, sets up " heartbeat " signal simultaneously.During normal operation, main frame is communicating by letter of charge server and Local Controller on the one hand, and main frame and standby host communicate on the other hand, synchronous operation state.When main frame occurs that when abnormal, standby host is obtained main frame abnormal information and taken over control by communication and becomes main frame, original host switches to standby host; What then announcement server occurred is abnormal, and equipment continues operation and processes related service.
When system is normally moved, a controller is as main frame, and another is as standby host, and two controllers carry out sending and receiving " heartbeat " synchronous operation state by UART and IO mouth.Main frame is communicated by letter with Local Controller by CAN bus, and but standby host is intercepted CAN bus do not processed.Once operation troubles appears in main frame, standby host immediately seamless switching is taken over all data and configuration consistency when authority also guarantees and main frame moves, and guarantees that gate control system continues, safe operation.
When gate control system controller normally moves, the information that the master controller of gate control system and Local Controller are sent by CAN bus communication processing server, system is normally moved.Between master controller and redundant manipulator, by GPIO, carry out " heartbeat " transmission of signal, by UART, communicate simultaneously.When gate inhibition's master controller is abnormal; comprise Flash read-write error; heartbeat signal is abnormal; when communication occurs that the situations such as gross error occur; heartbeat signal that standby host is received is abnormal or while receiving the identity handoff request of main frame; standby host will be taken over immediately control and play the part of host role and notify original host to switch to standby host, the abnormal conditions that then announcement server occurs, assurance system continuous service.
Processor in the present embodiment (CPU), adopt the LM3S9B92 chip of TI company, ARM Cortex-M3 processor cores, 80MHz dominant frequency, 100DMIPS performance, ARM Cortex system timer, nested vectorial interruptable controller, 256KB monocycle Flash, 96KB monocycle SRAM, Advanced Encryption Standard (AES) key form, cyclic redundancy check (CRC) (CRC) error detection function; Power acquisition LM2575 chip, input voltage range 4.74~40V; CAN communication adopts TJA1050 to communicate as transceiver and Local Controller; Real-time clock adopts DS1302 for system provides clock, periodically from server, obtains correct time and calibrates simultaneously; Flash chip adopts two MX25L6405D 16M bytes of storage space altogether, guarantees a large amount of storages of data; The PHY that network using LM3S9B92 carries and MAC realize; The inner LWIP of employing agreement realizes communicates by letter with the TCP of server.
CAN(Controller Area Network) being controller local area network, is to be applied in scene, between computerized measurement equipment, to realize bidirectional linked list multinode digital communication system, is the bottom control network of a kind of open, digitizing, multi-point.CAN agreement is based upon on ISO/OSI model, and its model structure has three layers.Agreement is divided into Can2.0A, CAN2.0B, and CANopen is several.
CAN-BUS is CAN bussing technique, and full name is " Controller Area Network BUS technology (Controller Area Network-BUS) ".Communication distance is relevant with ripple holdup, and maximum communication distance can reach 10km, and maximum communication ripple holdup can reach 1Mdps.CAN bus arbitration adopts 11 bit-identifies and non-destructive arbitration bus structure mechanism, and priority that can specified data piece guarantees that highest priority node does not need conflict to wait for when network node conflicts.CAN bus has adopted how main competitive mode bus structure, has the operation of many main websites and disperses the universal serial bus of arbitration and the feature of broadcast communication.In CAN bus, arbitrary node can be at any time sends information and regardless of primary and secondary, therefore can between each node, realize free communication to other node on network on one's own initiative.
Redundancy, increases standby equipment exactly, with assurance system more reliably, work safely.The sorting technique of redundancy is varied, and according to residing position in system, redundancy can be divided into component-level, component-level and system-level; According to the degree of redundancy, can be divided into 1:1 redundancy, 1:2 redundancy, 1:n redundancy etc. multiple.
Redundancy can improve the mission reliability of system or equipment, but can reduce the basic reliability of system or equipment.Redundancy is divided into active redundancy and inoperative redundancy (standby redundancy) two classes.
Two-node cluster hot backup, says to overview, with network, two-server is coupled together exactly, and backup mutually, carries out same service jointly at ordinary times.When a station server is shut down, can automatically the service take-over of server will be shut down by another station server in two-shipper, thereby in the situation that not needing manual intervention, assurance system can continue to provide service.
Dual-machine hot backup system adopts " heartbeat " method to guarantee contacting of main system and back-up system.So-called " heartbeat ", refers between master slave system and mutually according to certain time interval, sends communication signal, shows the current running status of system separately.Once " heartbeat " signal stops showing that host computer system breaks down, or back-up system cannot be received host computer system " heartbeat " signal, the high availability management software of system thinks that host computer system breaks down, main frame quits work, and system resource is transferred in back-up system, back-up system will substitute main frame and play a role, uninterrupted to guarantee network service operation.
By reference to the accompanying drawings the utility model preferred implementation is explained in detail above, but the utility model is not limited to above-mentioned embodiment, in the ken possessing those of ordinary skills, can also under the prerequisite that does not depart from the utility model aim, make a variety of changes.
Do not depart from design of the present utility model and scope and can make many other changes and remodeling.Should be appreciated that the utility model is not limited to specific embodiment, scope of the present utility model is defined by the following claims.

Claims (7)

1. gate inhibition's redundancy control system, comprises main frame, standby host and universal asynchronous receiving-transmitting transmitter, and described main frame is identical with standby host structure, comprises power supply, and 2 of the processors being electrically connected to power supply, clock chip, CAN transceiver interface chip,
Described electric power output voltage is 3.3V,
Described main frame is connected with Local Controller by CAN bus with standby host,
Between described main frame and standby host, by universal asynchronous receiving-transmitting transmitter, be connected,
Described main frame and standby host are drawn respectively by general purpose I/O port the wire jumper of uniting as one and are connected to the other side above, and described processor is electrically connected with Flash chip.
2. a kind of gate inhibition's redundancy control system according to claim 1, is characterized in that, described CAN bus medium is twisted-pair feeder or concentric cable or light transmitting fiber.
3. a kind of gate inhibition's redundancy control system according to claim 1, is characterized in that, described CAN bus adopts winding connection method to be connected with Local Controller.
4. a kind of gate inhibition's redundancy control system according to claim 1, is characterized in that, described Flash chip-stored space is 12~20M.
5. a kind of gate inhibition's redundancy control system according to claim 4, is characterized in that, described Flash chip is 2~4.
6. a kind of gate inhibition's redundancy control system according to claim 1, is characterized in that, the time of main frame of described clock chip periodic calibration and standby host.
7. a kind of gate inhibition's redundancy control system according to claim 6, is characterized in that, described clock chip is every the time of main frame of calibration in 1 hour and standby host.
CN201320546884.1U 2013-09-04 2013-09-04 Access redundancy control system Expired - Fee Related CN203455884U (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104299301A (en) * 2014-09-22 2015-01-21 哈尔滨工业大学 Nonporous electronic control security door fault-tolerant control system
CN104424680A (en) * 2013-09-04 2015-03-18 苏州元澄智能科技有限公司 Entrance guard redundancy control system
CN104700909A (en) * 2014-12-31 2015-06-10 大亚湾核电运营管理有限责任公司 Nuclear power plant group pile safety system
CN109147130A (en) * 2018-08-28 2019-01-04 昆明理工大学 A kind of electronic lock and its reading/writing method with dual-memory
CN110992550A (en) * 2020-01-02 2020-04-10 高新兴科技集团股份有限公司 Access control method, device, equipment and system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104424680A (en) * 2013-09-04 2015-03-18 苏州元澄智能科技有限公司 Entrance guard redundancy control system
CN104299301A (en) * 2014-09-22 2015-01-21 哈尔滨工业大学 Nonporous electronic control security door fault-tolerant control system
CN104700909A (en) * 2014-12-31 2015-06-10 大亚湾核电运营管理有限责任公司 Nuclear power plant group pile safety system
CN109147130A (en) * 2018-08-28 2019-01-04 昆明理工大学 A kind of electronic lock and its reading/writing method with dual-memory
CN110992550A (en) * 2020-01-02 2020-04-10 高新兴科技集团股份有限公司 Access control method, device, equipment and system

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C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20170414

Address after: Room 9, building 10, Lane No. 215000, Suzhou, Jiangsu, China

Patentee after: SUZHOU SIGMA TECHNOLOGY Co.,Ltd.

Address before: 215021, international science and Technology Park, Jinji Lake Avenue, Suzhou, Jiangsu, China 141D

Patentee before: SUZHOU YUANCHENG INTELLIGENCE TECHNOLOGY Co.,Ltd.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140226

Termination date: 20210904