CN203444102U

CN203444102U - Marine radar signal processor based on FPGA and Ethernet

Info

Publication number: CN203444102U
Application number: CN201320565178.1U
Authority: CN
Inventors: 李鹏; 马志强; 葛俊祥; 鲁建斌; 潘安
Original assignee: Nanjing University of Information Science and Technology
Current assignee: Nanjing University of Information Science and Technology
Priority date: 2013-09-11
Filing date: 2013-09-11
Publication date: 2014-02-19
Anticipated expiration: 2023-09-11

Abstract

The utility model discloses a marine radar signal processor based on an FPGA and the Ethernet. The structure of a signal processing system is greatly simplified, the transmission rate is improved, the bit error rate of signal transmission is lowered, and real-time and efficient data transmission is realized. The marine radar signal processor based on the FPGA and the Ethernet, provided by the utility model, comprises an information processing mechanism and a communication mechanism; the information processing mechanism comprises an antenna, a radar receiver, an intermediate-frequency amplification circuit, an A/D conversion circuit and an FPGA chip which are connected in sequence; the communication mechanism includes an Ethernet controller and a PC, wherein the Ethernet controller is connected with the PC through the Ethernet; and the FPGA chip is connected with the Ethernet controller. As the marine radar signal processor adopts the FPGA instead of a traditional signal processing method, the signal processing part is greatly simplified, the marine radar signal processor has the advantages of high reliability, good portability, good real-time performance, flexibility and the like, and the design of a whole radar system is made more compact and efficient.

Description

A kind of marine radar signal processor based on FPGA and Ethernet

Technical field

The utility model belongs to Radar Signal Processing and shows control field, especially relates to a kind of marine radar signal processor based on FPGA and Ethernet.

Background technology

Marine radar signal processing consists of many electronic circuits both at home and abroad at present, mainly comprises that CPU control section, vision signal amplifier section, signal processing and control section, figure show and control section.Its signal processing circuit design comparison is complicated, mainly single-chip microcomputer and related peripheral circuit, consists of, and this has affected to a certain extent the processing speed of whole signal processing module and has controlled precision.The today of processing special chip, universal cpu and microprocessor high speed development at signal, traditional radar signal processor part is not obviously optimal selection, and its processing speed and control precision all can not reach optimization.

In recent years, FPGA is more and more extensive in the application of radar signal processing field.FPGA(Field-Programmable Gate Array), i.e. field programmable gate array, it is the product further developing on the basis of the programming devices such as PAL, GAL, CPLD.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, has overcome again the limited shortcoming of original programming device gate circuit number.It is fast that FPGA has travelling speed, easily realizes large scale system, internal processes parallel running, and interface is controlled the advantages such as flexible.FPGA is as radar signal processor core, echoed signal after processing must be sent to display terminal shows, this just needs to have between display terminal and FPGA its communication ability of high speed, and requirement can be passed through FPGA control radar signal processor by PC.

But at present traditional PC and FPGA communication mode mostly is serial communication and usb communication, and serial communication has the shortcoming that transmission data rate is low, usb communication when long-distance transmissions the bit error rate higher.Because radar return data generally have longer distance to display terminal, and echo signal data amount is larger, and when this makes serial communication and usb communication as the communication interface of radar signal processor and display module, effect is poor, can not meet real-time Transmission demand.

Summary of the invention

For addressing the above problem, the utility model discloses a kind of marine radar signal processor based on FPGA and Ethernet, greatly simplified the structure of signal processing system, improved transfer rate, reduce the transmission error rates of signal, realized real-time, the high efficiency of transmission of data.

In order to reach above object, the utility model provides following technical scheme:

A marine radar signal processor for FPGA and Ethernet, comprises information processing mechanism and communication agency, and described information processing mechanism comprises antenna, radar receiver, intermediate level circuit, A/D change-over circuit and the fpga chip connecting successively; Described communication agency comprises ethernet controller and PC, and ethernet controller is connected with PC by Ethernet; Described fpga chip is connected with ethernet controller; Antenna reception to echoed signal after radar receiver, intermediate level circuit and A/D change-over circuit, enter into fpga chip, after fpga chip is processed radar echo signal, the data after processing are transferred to PC through ethernet controller, Ethernet and show.

As a kind of preferred version of the present utility model, described fpga chip model is EP4CE15F17C8.This chip processing speed is high, with low cost, and I/O rich interface can effectively improve Assessment of Radar Signal Processor Performance, debugs also very convenient.

As a kind of preferred version of the present utility model, described ethernet controller model is ENC28J60.This chip interface is simple, and number of pin is few, stable performance, and transmission speed is high, is enough to meet marine radar signal processor data transmission demand.

Compared with prior art, the utlity model has following advantage and beneficial effect:

1. adopt FPGA to replace classical signal processing mode, signal processing is simplified greatly, there is the advantages such as high, portable good, the real-time of reliability and dirigibility, using FPGA as the main control chip of whole radar system also make the design of whole radar system compacter, efficient.

2. adopt ethernet communication to replace traditional serial ports or usb communication pattern, transfer rate is fast, time delay is little, the long Distance Transmission bit error rate is low, networking flexibility and the easy advantage such as expansion, can overcome the shortcoming existing in serial communication and usb communication, system control flexibly simple, visual strong, cost of development is low.

Accompanying drawing explanation

Fig. 1 is the structural principle schematic diagram of the marine radar signal processor based on FPGA and Ethernet;

Fig. 2 is the connection diagram of fpga chip and ethernet controller.

Embodiment

Below in conjunction with the drawings and specific embodiments, further illustrate the utility model, should understand following embodiment and only for the utility model is described, be not used in restriction scope of the present utility model.

The marine radar signal processor based on FPGA and Ethernet as shown in Figure 1, comprises information processing mechanism and communication agency, and described information processing mechanism comprises antenna, radar receiver, intermediate level circuit, A/D change-over circuit and fpga chip; Described communication agency comprises ethernet controller and PC, thereby ethernet controller has Ethernet interface, by Ethernet, is connected with PC; Fpga chip is connected with ethernet controller.Radar echo signal enters radar receiver by antenna reception, and radar receiver carries out a series of processing such as frequency conversion, filtering, amplification and demodulation to echoed signal; During intermediate-freuqncy signal after radar receiver is processed enters, put plate, in put plate and realize processing such as the envelope detection of signal and amplifications; A/D plate is realized the signal digitalized processing after detection, is convenient to post-processed, and the echoed signal after sampling enters FPGA; FPGA mainly realizes the processing of echoed signal and storage, the driving of the required control signal of system and ethernet communication is provided.FPGA drive ethernet controller by Ethernet by the data transmission after processing to PC, PC receives Ethernet and transmits the data of returning and show.In addition, also can further by the display on PC, see the duty of FPGA and be controlled, thereby can control whole radar system.

As shown in Figure 2, fpga chip model preferably adopts EP4CE15F17C8, and this chip has the features such as processing speed is high, cost is low, and I/O mouth is abundant, can effectively improve Assessment of Radar Signal Processor Performance, and conveniently debug.Ethernet controller model preferably adopts ENC28J60, it is simple that this chip has interface, by SPI, communicates by letter with CPU, reduced to a great extent the quantity of pin, be convenient to control and communicate by letter by FPGA, and the transmission speed of 10Mb/s is enough to meet marine radar signal processor data transmission demand.EP4CE15F17C8 type FPGA is by the control of I/O mouth own being reached to the object of controlling ENC28J60 type ethernet controller, thereby completes the driving work of FPGA to ethernet communication, and wherein PIN_** corresponds respectively to FPGA pin,

iNT interrupt output pin,

be that LAN interrupts waking output pin up, SO is SPI interface data output pin, and SI is SPI interface data input pin, and SCK is the clock input pin of SPI interface,

the sheet that is SPI interface selects input pin,

it is Low level effective device reset input.The PIN_E15 of fpga chip, PIN_E16, PIN_J12, PIN_J14, PIN_K10, PIN_L10, PIN_M1 pin are respectively successively with ethernet controller

pin,

pin, SO pin, SI pin, SCK pin, pin,

pin connects.

The disclosed technological means of the utility model scheme is not limited only to the disclosed technological means of above-mentioned embodiment, also comprises the technical scheme being comprised of above technical characterictic combination in any.It should be pointed out that for those skilled in the art, not departing under the prerequisite of the utility model principle, can also make some improvements and modifications, these improvements and modifications are also considered as protection domain of the present utility model.

Claims

1. the marine radar signal processor based on FPGA and Ethernet, it is characterized in that: comprise information processing mechanism and communication agency, described information processing mechanism comprises antenna, radar receiver, intermediate level circuit, A/D change-over circuit and the fpga chip connecting successively; Described communication agency comprises ethernet controller and PC, and ethernet controller is connected with PC by Ethernet; Described fpga chip is connected with ethernet controller; Antenna reception to echoed signal after radar receiver, intermediate level circuit and A/D change-over circuit, enter into fpga chip, after fpga chip is processed radar echo signal, the data after processing are transferred to PC through ethernet controller, Ethernet and show.

2. the marine radar signal processor based on FPGA and Ethernet according to claim 1, is characterized in that: described fpga chip model is EP4CE15F17C8.

3. the marine radar signal processor based on FPGA and Ethernet according to claim 1 and 2, is characterized in that: described ethernet controller model is ENC28J60.