CN203423676U - Signal conditioning circuit - Google Patents
Signal conditioning circuit Download PDFInfo
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- CN203423676U CN203423676U CN201320564922.6U CN201320564922U CN203423676U CN 203423676 U CN203423676 U CN 203423676U CN 201320564922 U CN201320564922 U CN 201320564922U CN 203423676 U CN203423676 U CN 203423676U
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Abstract
The utility model provides a signal conditioning circuit, which comprises a signal input circuit and a signal output circuit, wherein the signal input circuit comprises a positive signal input unit, a negative signal input unit and a first intermediate resistor R-1; and the signal output circuit comprises a positive signal output unit, a negative signal output unit and a second intermediate resistor R-2. The signal conditioning circuit adopts the circuit structure of an instrumentation amplifier, and has the advantages that input impedance and common mode rejection ratio are high; the circuit structure is symmetrical; elimination of common mode noise and temperature drift is facilitated; and therefore low noise and low temperature drift are achieved.
Description
Technical field
The utility model relates to a kind of circuit, relates in particular to a kind of signal conditioning circuit.
Background technology
At present, generally, AD acquisition chip all can have high frequency sampling noiset, and this noise can affect preamplifying circuit, can make precision amplify, and system linear degree and noise variation are generally being placed electric capacity near AD, can average current pulse, and reflection and vibration; And general high precision operating amplifier can only drive the electric capacity of hundreds of pF; Therefore conventional modulate circuit cannot meet requirements of one's work, greatly reduces the efficiency of work.
Summary of the invention
In order to solve existing technical problem in above-mentioned background technology, the utility model provides a kind of signal conditioning circuit.
Technical solution of the present utility model is:
The utility model provides a kind of signal conditioning circuit, and its special character is: comprise signal input circuit and signal output apparatus; Described signal input circuit comprises positive signal input unit, negative signal input unit and the first interlaminated resistance R-1; Described positive signal input unit comprises positive signal amplifier U1, positive signal diverter switch SW-1 and positive signal resistance unit; Described negative signal input unit comprises negative signal amplifier U2, negative signal diverter switch SW-2 and negative signal resistance unit; Described positive signal resistance unit comprises the positive signal resistance R J-1 of N series connection; Described positive signal diverter switch SW-1 comprises N+1 input and an output; Described negative signal resistance unit comprises the negative signal resistance R J-2 of N series connection; Described negative signal diverter switch SW-2 comprises N+1 input and an output; N is more than or equal to 1 integer; The output of one termination positive signal amplifier U1 of described positive signal resistance unit; The output of one termination negative signal amplifier U2 of described negative signal resistance unit; The other end of described positive signal resistance unit is connected with the other end of negative signal resistance unit by the first interlaminated resistance R-1; Described N positive signal resistance R J-1 is serially connected in respectively between N+1 the input of positive signal diverter switch SW-1; Described N negative signal resistance R J-2 is serially connected in respectively between N+1 the input of negative signal diverter switch SW-2; The negative input of the output termination positive signal amplifier U1 of described positive signal diverter switch SW-1; The negative input of the output termination negative signal amplifier U2 of described negative signal diverter switch SW-2; Described positive signal input unit and negative signal input unit symmetrical configuration, parameter is consistent;
Above-mentioned signal output apparatus comprises positive signal output unit, negative signal output unit, the second interlaminated resistance R-2; Described positive signal output unit comprises positive signal amplifier U3, positive signal output resistance unit and output capacitance C1; Described negative signal output unit comprises negative signal amplifier U4, negative signal output resistance unit and output capacitance C2; Described positive signal output resistance unit comprises the positive anode signal output resistance RJ-3 of M series connection and the positive cathode signal output resistance RJ-4 of M series connection; Described negative signal output resistance unit comprises the negative anode signal output resistance RJ-5 of M series connection and the negative cathode signal output resistance RJ-6 of M series connection; M is more than or equal to 1 integer; The negative input of a termination positive signal amplifier U3 of described output capacitance C1; The output of another termination positive signal amplifier U3 of described output capacitance C1; The positive cathode signal output resistance RJ-4 of described M series connection is in parallel with output capacitance C1; The negative input of a termination negative signal amplifier U4 of described output capacitance C2; Another termination of described output capacitance C2 connects the output of negative signal amplifier U4; The negative cathode signal output resistance RJ-6 of described M series connection is in parallel with output capacitance C2; The electrode input end of a termination positive signal amplifier U3 of the positive anode signal output resistance RJ-3 of described M series connection; Another termination positive signal input unit of the positive anode signal output resistance RJ-3 of described M series connection; The electrode input end of a termination negative signal amplifier U4 of the negative anode signal output resistance RJ-5 of described M series connection; Another termination Vcm of the negative anode signal output resistance RJ-5 of described M series connection; A termination negative signal input unit of the positive cathode signal output resistance RJ-4 of described M series connection; The negative cathode signal output resistance RJ-6 of M the series connection of another termination of the positive cathode signal output resistance RJ-4 of described M series connection; The positive anode signal output resistance RJ-3 of described M series connection is connected with the negative cathode signal output resistance RJ-6 of M series connection by the second interlaminated resistance R-2; Described positive signal output unit is all consistent with negative signal output unit structure and parameter;
Above-mentioned positive signal diverter switch SW-1 and negative signal diverter switch SW-2 are mechanical switch, analog switch, wire jumper or relay;
Resistance in above-mentioned positive signal resistance unit, negative signal resistance unit and the first interlaminated resistance R-1 is conventional, electric-resistance, precision resistance, discrete resistor, network resistor.；
Resistance in above-mentioned positive signal output resistance unit, negative signal output resistance unit and the second interlaminated resistance R-2 is conventional, electric-resistance, precision resistance, discrete resistor, network resistor.
Advantage of the present utility model:
1, modulate circuit of the present utility model is instrument amplifier circuit structure, has the feature of high input impedance and high cmrr, and circuit structure symmetry, is conducive to eliminate common-mode noise and temperature is floated, thereby reaches low noise and Low Drift Temperature.
2, the circuit structure of modulate circuit of the present utility model, is conducive to drive large electric capacity, can drive the large electric capacity of uF level, thereby reduces the sampling noiset of AD.
3, in circuit of the present utility model, adopt the method (be diverter switch with resistance coordinate) of adjustable control gain, thereby according to different demand regulation and control, the requirement of satisfied use different conditions, has improved the efficiency of work.
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams of modulate circuit of the present utility model;
Fig. 2 is the circuit diagram of modulate circuit of the present utility model;
Fig. 3 is the another kind of circuit diagram of the signal input circuit in the utility model modulate circuit.
Embodiment
Referring to Fig. 1, the utility model provides a kind of signal conditioning circuit, comprises signal input circuit and signal output apparatus; Signal input circuit comprises positive signal input unit, negative signal input unit and the first interlaminated resistance R-1; Positive signal input unit comprises positive signal amplifier U1, positive signal diverter switch SW-1 and positive signal resistance unit; Negative signal input unit comprises negative signal amplifier U2, negative signal diverter switch SW-2 and negative signal resistance unit; Positive signal resistance unit comprises the positive signal resistance R J-1 of N series connection; Positive signal diverter switch SW-1 comprises N+1 input and an output; Negative signal resistance unit comprises the negative signal resistance R J-2 of N series connection; Negative signal diverter switch SW-2 comprises N+1 input and an output; N is more than or equal to 1 integer; The output of one termination positive signal amplifier U1 of positive signal resistance unit; The output of one termination negative signal amplifier U2 of negative signal resistance unit; The other end of positive signal resistance unit is connected with the other end of negative signal resistance unit by the first interlaminated resistance R-1; N positive signal resistance R J-1 is serially connected in respectively between N+1 the input of positive signal diverter switch SW-1; N negative signal resistance R J-2 is serially connected in respectively between N+1 the input of negative signal diverter switch SW-2; The negative input of the output termination positive signal amplifier U1 of positive signal diverter switch SW-1; The negative input of the output termination negative signal amplifier U2 of negative signal diverter switch SW-2; Positive signal input unit and negative signal input unit symmetrical configuration, parameter is consistent.
Signal output apparatus comprises positive signal output unit, negative signal output unit, the second interlaminated resistance R-2; Positive signal output unit comprises positive signal amplifier U3, positive signal output resistance unit and output capacitance C1; Negative signal output unit comprises negative signal amplifier U4, negative signal output resistance unit and output capacitance C2; Positive signal output resistance unit comprises the positive anode signal output resistance RJ-3 of M series connection and the positive cathode signal output resistance RJ-4 of M series connection; Negative signal output resistance unit comprises the negative anode signal output resistance RJ-5 of M series connection and the negative cathode signal output resistance RJ-6 of M series connection; M is more than or equal to 1 integer; The negative input of a termination positive signal amplifier U3 of output capacitance C1; The output of another termination positive signal amplifier U3 of output capacitance C1; The positive cathode signal output resistance RJ-4 of M series connection is in parallel with output capacitance C1; The negative input of a termination negative signal amplifier U4 of output capacitance C2; Another termination of output capacitance C2 connects the output of negative signal amplifier U4; The negative cathode signal output resistance RJ-6 of M series connection is in parallel with output capacitance C2; The electrode input end of a termination positive signal amplifier U3 of the positive anode signal output resistance RJ-3 of M series connection; Another termination positive signal input unit of the positive anode signal output resistance RJ-3 of M series connection; The electrode input end of a termination negative signal amplifier U4 of the negative anode signal output resistance RJ-5 of M series connection; Another termination Vcm of the negative anode signal output resistance RJ-5 of M series connection; A termination negative signal input unit of the positive cathode signal output resistance RJ-4 of M series connection; The negative cathode signal output resistance RJ-6 of M the series connection of another termination of the positive cathode signal output resistance RJ-4 of M series connection; The positive anode signal output resistance RJ-3 of M series connection is connected with the negative cathode signal output resistance RJ-6 of M series connection by the second interlaminated resistance R-2; Positive signal output unit is all consistent with negative signal output unit structure and parameter.
Positive signal diverter switch SW-1 and negative signal diverter switch SW-2 are mechanical switch, analog switch, wire jumper or relay.
Resistance in positive signal resistance unit, negative signal resistance unit and the first interlaminated resistance R-1 is conventional, electric-resistance, precision resistance, discrete resistor, network resistor.
Resistance in positive signal output resistance unit, negative signal output resistance unit and the second interlaminated resistance R-2 is conventional, electric-resistance, precision resistance, discrete resistor, network resistor.
Positive signal diverter switch and negative signal diverter switch can be Split type structures, and optimum is integrative-structure, two switches move simultaneously and switching result consistent.
Referring to Fig. 2-Fig. 3, be modulate circuit theory diagram, this modulate circuit is instrument amplifier circuit structure, has the feature of high input impedance and high cmrr, circuit structure symmetry, is conducive to eliminate common-mode noise and temperature is floated, thereby reaches low noise and Low Drift Temperature.
Generally, AD acquisition chip all can have high frequency sampling noiset, and this noise can affect preamplifying circuit, can make precision amplify, system linear degree and noise variation.Near AD, place electric capacity, can average current pulse, reflection and vibration.And general high precision operating amplifier can only drive the electric capacity of hundreds of pF, the circuit structure of this modulate circuit, is conducive to drive large electric capacity, can drive the large electric capacity of uF level, thereby reduces the sampling noiset of AD.
Number in the figure is the resistance of RJ, and R is precision resistance, is not limited to discrete resistor, and also network resistor etc., decisive action to the gain of circuit and warm levitating.A, B, C, D is four operational amplifiers.Circuit is divided into two-stage, and function at different levels is as follows:
A) first order
The first order is the input stage of modulate circuit, and the circuit structure of the first order is symmetrical, for typical instrument amplifier structure, can pass through diverter switch SW, realizes the switching of gain.First order circuit structure can not introduced gain by the error of switch internal resistance, because switch is connected with the negative terminal of operational amplifier A and B, can thinks and not have electric current to flow through.
SW is the switch of broad sense, can be mechanical switch, analog switch, wire jumper, the components and parts that relay etc. can switching signal.In Fig. 2, take difference analogue switch as example, and there are A and B double switch in its inside.Switch A comprises DA, S1A, S2A, the several pins of S3A; Switch B comprises DB, S1B, S2B, S3B pin.Have three kinds of states, state 1:DA is communicated with S1A, and DB is communicated with S1B simultaneously; State 2:DA is communicated with S2A, and DB is communicated with S2B simultaneously; State 3:DA is communicated with S3A, and DB is communicated with S3B simultaneously.
Referring to Fig. 2,5 resistance of take in figure are example, can realize 3 kinds of gains, resistance R J2=RJ4 wherein, and RJ3=RJ5, is a kind of circuit structure of symmetry.Also can change the number of resistance, change the number of gain, if Fig. 3 is the situation of two kinds of gains, Fig. 2 compares with Fig. 3, has removed resistance R J3 and RJ5, the corresponding number of states that reduces simulation.Identical reason, the number of increase resistance, also can realize the increase of gain quantity, and reason is equivalent to change into three kinds of gains Fig. 3 from two kinds of gains of Fig. 2.
In Fig. 2, when SW is operated in " state 1 ", SW is switched to a1 and b1, and gaining is:
while being operated in " state 2 ", SW is switched to a2 and b2, and gaining is:
while being operated in " state 3 ", SW is switched to a3 and b3, and gaining is:
For example: realize 1,10,100 3 kinds of gains, resistance R J1 selects 400 Ω; RJ2, RJ4 selects 1.8k Ω; RJ3, RJ5 selects 18k Ω.By formula above, can be calculated three gains as follows:
The first order both can realize differential signal input, also can realize single-ended signal input, in Fig. 3, with differential signal, was input as example, i.e. Vi+ in figure and Vi-, when input signal is while being single-ended, receive Vi-with reference on the ground.If the gain of the first order switches to G, the first order is output as G * (V so
i+-V
i-), during single-ended input, think that Vi-is 0.Signal is amplified into the second level through the first order.
B) second level
The output signal that the second level receives the first order, realizes the decay of signal, common-mode voltage stack, difference output.The second level is by resistance R J6, RJ7, and RJ8, RJ9, RJ10, RJ11, R1, R2, capacitor C 1, C2 and operational amplifier C and D form.
R1 in this grade of circuit, R2, C1, the circuit structure of C2 is beneficial to and drives large electric capacity, thereby reduces the sampling noiset of AD.R1, R2, C1, C2 is on not impact of attenuation multiple.Capacitor C 1, the selection of C2 will meet the bandwidth requirement of whole circuit, and C1 and RJ9 form RC low pass filter, and C2 and RJ10 form RC low pass filter, and the upper cut-off frequency of these two low pass filters all will adapt with the bandwidth of whole amplifying circuit.Resistance R 1, R2 plays the effect of isolation resistance, general resistance is less than 100 Ω, in most cases 10 Ω can meet the demands, concrete numerical value when reality is debugged, according to the capacitance size of whole drives, the parameter of operational amplifier C and D and determining.
Attenuation multiple is by precision resistance RJ6, RJ7, and RJ8, RJ9 determines, must meet RJ6=RJ8, RJ7=RJ9, attenuation multiple is
for example: if 0.2 times of error is wanted in the second level, the optional 1k Ω of RJ6 and RJ8 so, the optional 5k Ω of RJ7 and RJ9.
RJ10, RJ11 and operational amplifier D realize the stack of common-mode voltage, must meet RJ10=RJ11.Wherein Vcm is common-mode voltage, and resistance R 3 is optional resistance.
The second level is output as differential signal Vo+ and Vo-, and common-mode voltage is Vcm.Can directly connect rear class AD acquisition chip.
Remove RJ10, RJ11, R2, R3, C2, operational amplifier D and common-mode voltage Vcm, and Vo-is received with reference on the ground, can realize Single-end output.
The gain of whole modulate circuit is determined jointly by the first order and second level circuit.For example the gain of the first order is 1,10,100, the second level decay to 0.2, the gain of so whole modulate circuit is 0.2,2,20.
Claims (5)
1. a signal conditioning circuit, is characterized in that: comprise signal input circuit and signal output apparatus; Described signal input circuit comprises positive signal input unit, negative signal input unit and the first interlaminated resistance R-1; Described positive signal input unit comprises positive signal amplifier U1, positive signal diverter switch SW-1 and positive signal resistance unit; Described negative signal input unit comprises negative signal amplifier U2, negative signal diverter switch SW-2 and negative signal resistance unit; Described positive signal resistance unit comprises the positive signal resistance R J-1 of N series connection; Described positive signal diverter switch SW-1 comprises N+1 input and an output; Described negative signal resistance unit comprises the negative signal resistance R J-2 of N series connection; Described negative signal diverter switch SW-2 comprises N+1 input and an output; N is more than or equal to 1 integer; The output of one termination positive signal amplifier U1 of described positive signal resistance unit; The output of one termination negative signal amplifier U2 of described negative signal resistance unit; The other end of described positive signal resistance unit is connected with the other end of negative signal resistance unit by the first interlaminated resistance R-1; Described N positive signal resistance R J-1 is serially connected in respectively between N+1 the input of positive signal diverter switch SW-1; Described N negative signal resistance R J-2 is serially connected in respectively between N+1 the input of negative signal diverter switch SW-2; The negative input of the output termination positive signal amplifier U1 of described positive signal diverter switch SW-1; The negative input of the output termination negative signal amplifier U2 of described negative signal diverter switch SW-2; Described positive signal input unit and negative signal input unit symmetrical configuration, parameter is consistent.
2. signal conditioning circuit according to claim 1, is characterized in that: described signal output apparatus comprises positive signal output unit, negative signal output unit, the second interlaminated resistance R-2; Described positive signal output unit comprises positive signal amplifier U3, positive signal output resistance unit and output capacitance C1; Described negative signal output unit comprises negative signal amplifier U4, negative signal output resistance unit and output capacitance C2; Described positive signal output resistance unit comprises the positive anode signal output resistance RJ-3 of M series connection and the positive cathode signal output resistance RJ-4 of M series connection; Described negative signal output resistance unit comprises the negative anode signal output resistance RJ-5 of M series connection and the negative cathode signal output resistance RJ-6 of M series connection; M is more than or equal to 1 integer; The negative input of a termination positive signal amplifier U3 of described output capacitance C1; The output of another termination positive signal amplifier U3 of described output capacitance C1; The positive cathode signal output resistance RJ-4 of described M series connection is in parallel with output capacitance C1; The negative input of a termination negative signal amplifier U4 of described output capacitance C2; Another termination of described output capacitance C2 connects the output of negative signal amplifier U4; The negative cathode signal output resistance RJ-6 of described M series connection is in parallel with output capacitance C2; The electrode input end of a termination positive signal amplifier U3 of the positive anode signal output resistance RJ-3 of described M series connection; Another termination positive signal input unit of the positive anode signal output resistance RJ-3 of described M series connection; The electrode input end of a termination negative signal amplifier U4 of the negative anode signal output resistance RJ-5 of described M series connection; Another termination Vcm of the negative anode signal output resistance RJ-5 of described M series connection; A termination negative signal input unit of the positive cathode signal output resistance RJ-4 of described M series connection; The negative cathode signal output resistance RJ-6 of M the series connection of another termination of the positive cathode signal output resistance RJ-4 of described M series connection; The positive anode signal output resistance RJ-3 of described M series connection is connected with the negative cathode signal output resistance RJ-6 of M series connection by the second interlaminated resistance R-2; Described positive signal output unit is all consistent with negative signal output unit structure and parameter.
3. signal conditioning circuit according to claim 1, is characterized in that: described positive signal diverter switch SW-1 and negative signal diverter switch SW-2 are mechanical switch, analog switch, wire jumper or relay.
4. signal conditioning circuit according to claim 1, is characterized in that: the resistance in described positive signal resistance unit, negative signal resistance unit and the first interlaminated resistance R-1 is conventional, electric-resistance, precision resistance, discrete resistor, network resistor.
5. signal conditioning circuit according to claim 2, is characterized in that: the resistance in described positive signal output resistance unit, negative signal output resistance unit and the second interlaminated resistance R-2 is conventional, electric-resistance, precision resistance, discrete resistor, network resistor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320564922.6U CN203423676U (en) | 2013-07-03 | 2013-09-11 | Signal conditioning circuit |
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| CN201320393754 | 2013-07-03 | ||
| CN201320393754.9 | 2013-07-03 | ||
| CN201320564922.6U CN203423676U (en) | 2013-07-03 | 2013-09-11 | Signal conditioning circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103457607A (en) * | 2013-07-03 | 2013-12-18 | 陕西海泰电子有限责任公司 | Signal conditioning circuit |
| CN105406870A (en) * | 2015-12-27 | 2016-03-16 | 哈尔滨米米米业科技有限公司 | High-speed accelerometer data acquisition system |
| CN114553157A (en) * | 2022-02-28 | 2022-05-27 | 山东大学 | Differential amplification circuit, control method and signal amplification equipment |
-
2013
- 2013-09-11 CN CN201320564922.6U patent/CN203423676U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103457607A (en) * | 2013-07-03 | 2013-12-18 | 陕西海泰电子有限责任公司 | Signal conditioning circuit |
| CN103457607B (en) * | 2013-07-03 | 2017-02-22 | 陕西海泰电子有限责任公司 | Signal conditioning circuit |
| CN105406870A (en) * | 2015-12-27 | 2016-03-16 | 哈尔滨米米米业科技有限公司 | High-speed accelerometer data acquisition system |
| CN114553157A (en) * | 2022-02-28 | 2022-05-27 | 山东大学 | Differential amplification circuit, control method and signal amplification equipment |
| CN114553157B (en) * | 2022-02-28 | 2024-04-05 | 山东大学 | Differential amplifying circuit, control method and signal amplifying equipment |
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