CN203414503U - Self-checking adapter of automatic detection system based on PXI bus - Google Patents
Self-checking adapter of automatic detection system based on PXI bus Download PDFInfo
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- CN203414503U CN203414503U CN201320483324.6U CN201320483324U CN203414503U CN 203414503 U CN203414503 U CN 203414503U CN 201320483324 U CN201320483324 U CN 201320483324U CN 203414503 U CN203414503 U CN 203414503U
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Abstract
The utility model relates to a self-checking adapter of an automatic detection system based on a PXI bus, applies to interconnection of an incentive instrument, switch resource, and measuring instrument of the automatic detection system, and realizes the state detection of the automatic detection system resource. The self-checking adapter of the automatic detection system based on the PXI bus comprises a standard current source, a standard resistor R, a reference source circuit, a square wave generator, a signal router N1-N3, a first copper foil short-circuit wire, a second copper foil short-circuit wire, a third copper foil short-circuit wire, a fourth copper foil short-circuit wire, and a fifth copper foil short-circuit wire. The beneficial effects of the utility model are that: the detection, and fault diagnosis, and fault location of the measured object are more accurate and reliable; the self-checking function is realized with slight addition of the adjunct circuit (the self-checking adapter); the simple structure and the high reliability are realized; the detection and the fault isolation of the automatic detection system are realized; and the detection accuracy is guaranteed.
Description
Technical field
The utility model relates to a kind of self-test adapter of the automatic checkout system based on PXI bus, is applicable to excitation instrument, the Switch Resource of automatic checkout system, the interconnection of surveying instrument, realizes the state-detection to the automatic checkout system resource based on PXI bus.
Background technology
For the automatic checkout system of complex electronic equipment or circuit board, conventionally adopt the method for embedded built-in test (BIT) to guarantee himself reliability and security.The BIT method for designing of taking for different circuit modules is also not quite similar, and main method has remaining BIT technology and around BIT technology etc.Remaining BIT technology improves fault detect and isolating power by increasing remaining unit, but price comparison is expensive, and general for to the very high expensive system of reliability requirement or key position; Around BIT technology, make full use of equipment own resource and build closed-loop system, be applicable to circuit board, module or subsystem level, can be without external circuit or completion system self check only need a small amount of peripheral support circuit in the situation that.Native system is based on around BIT technology, and the PXI test module by self-test adapter and automatic checkout system forms loop, under the selftest module of system software is controlled, and the self-checking function of completion system.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of self-test adapter of the automatic checkout system based on PXI bus.
The utility model adopts following technical scheme:
A self-test adapter for the automatic checkout system of PXI bus, comprises normalized current source, measuring resistance R, reference source circuit, square-wave generator, signal router N1-N3 and the first to the 5th Copper Foil short-circuit line;
The output terminal COM in described normalized current source connects VPC connector the 1st groove respective input of described automatic checkout system; The input end I1 of the D1 termination signal router N1 of described measuring resistance R, the output terminal O4 of the D2 termination signal router N2 of described measuring resistance R; The output terminal REF of described reference source circuit meets the input end I5 of signal router N2; The input end I2 of described signal router N1 meets the input end I4 of signal router N2, connects the simulating signal generation module output terminal of described automatic checkout system through the VPC of described automatic checkout system connector the 2nd groove simultaneously; The output terminal O1 of described signal router N1 connects VPC connector the 1st groove respective input of described automatic checkout system; The output terminal O2 of described signal router N1 meets the input end I3 of described signal router N2; The output terminal O3 of described signal router N2 connects the multi-functional DAQ module of described automatic checkout system through the VPC of described automatic checkout system connector the 3rd groove; VPC connector the 1st groove output terminal of described automatic checkout system connects respectively the respective input of the high voltage multiplexer module of described automatic checkout system; The input end of the output termination digital multimeter module of the high voltage multiplexer module of described automatic checkout system;
The output terminal W0 of described square-wave generator meets the input end I6 of signal router N3; The output terminal W1 of described square-wave generator connects the first dynamic signal acquisition module input through the VPC of described automatic checkout system connector the 8th groove, the first universal switch module successively; The output terminal W2 of described square-wave generator connects the second dynamic signal acquisition module input through the VPC of described automatic checkout system connector the 9th groove, the second universal switch module successively;
The input end I7 of described signal router N3 divides two branch roads, wherein a branch road connects the output terminal of the first virtual arbitrary waveform generator module successively through the VPC of described automatic checkout system connector the 6th groove, the 3rd intermediate frequency switch module, and another branch road connects the output terminal of the second virtual arbitrary waveform generator module successively through the VPC of described automatic checkout system connector the 7th groove, the 4th intermediate frequency switch module; The output terminal O5 of described signal router N3 divides two branch roads, wherein a branch road connects the input end of the first Digital Oscillograph Module successively through the VPC of described automatic checkout system connector the 4th groove, the first intermediate frequency switch module, and another branch road connects the input end of the second Digital Oscillograph Module successively through the VPC of described automatic checkout system connector the 5th groove, the second intermediate frequency switch module;
The first end of described the first Copper Foil short-circuit line is two-way connection of digital I/O module corresponding end with described automatic checkout system through the VPC of described automatic checkout system connector the 10th groove, and the second end of described the first Copper Foil short-circuit line is two-way connection of digital I/O module corresponding end with described automatic checkout system through the VPC of described automatic checkout system connector the 10th groove; Described the second Copper Foil short-circuit line first end is optics isolation digital input module two-way connection of corresponding end with described automatic checkout system through the VPC of described automatic checkout system connector the 10th groove, and described second Copper Foil short-circuit line the second end is optics isolation digital input module two-way connection of corresponding end with described automatic checkout system through the VPC of described automatic checkout system connector the 10th groove;
The first end of described the 3rd Copper Foil short-circuit line is held two-way connection through the VPC of described automatic checkout system connector the 11st groove with the H of the CAN1 of the CAN interface module of described automatic checkout system; The second end of described the 3rd Copper Foil short-circuit line is held two-way connection through the VPC of described automatic checkout system connector the 11st groove with the H of the CAN2 of the CAN interface module of described automatic checkout system; The first end of described the 4th Copper Foil short-circuit line is held two-way connection through the VPC of described automatic checkout system connector the 11st groove with the L of the CAN1 of the CAN interface module of described automatic checkout system; The second end of described the 4th Copper Foil short-circuit line is held two-way connection through the VPC of described automatic checkout system connector the 11st groove with the L of the CAN2 of the CAN interface module of described automatic checkout system;
The first end of described the 5th Copper Foil short-circuit line meets the RS232 serial interface module transmitting terminal TX of described automatic checkout system through the VPC of described automatic checkout system connector the 11st groove, the second end of described the 5th Copper Foil short-circuit line meets the receiving end RX of the RS232 serial interface module of described automatic checkout system through the VPC of described automatic checkout system connector the 11st groove;
The control end of the high voltage multiplexer module of described automatic checkout system, the control end of digital multimeter module, the control end of simulating signal generation module, the control end of multi-functional DAQ module, the control end of the first to second virtual arbitrary waveform generator module, the control end of the first to second Digital Oscillograph Module, the control end of first to fourth intermediate frequency switch module, the control end of first to fourth universal switch module, the control end of the first to second dynamic signal acquisition module, the control of numeral I/O module, the control end of optics isolation digital input module, the control end of the control end of CAN interface module and RS232 serial interface module respectively with two-way connection of controller corresponding port of described automatic checkout system.
Described reference source circuit comprises reference source chip U1, amplifier U2, resistance R 1 and capacitor C 1-C2;
Described capacitor C 1 is connected between input end 2 pin and ground of reference source chip U1; Described capacitor C 2 is connected between output terminal 6 pin and ground of reference source chip U1; The 4 pin ground connection of described reference source chip U1; Connect+12V of the power end 8 pin direct supply of described amplifier U2; Connect-12V of the power end 4 pin direct supply of described amplifier U2.
Described square-wave generator comprises integrated package U3, crystal oscillator Y1, resistance R 2-R6 and capacitor C 3-C4; 11 pin of described integrated package U3 connect 8 pin of integrated package U3 successively through crystal oscillator Y1, capacitor C 4; Described resistance R 2 is in parallel with crystal oscillator Y1; Described capacitor C 3 is connected between 11 pin and 8 pin of integrated package U3; Described resistance R 3 is connected between the node of crystal oscillator Y1 and capacitor C 2 and 10 pin of integrated package U3; Connect+12V of the 16 pin direct supply of described integrated package U3; 12 pin of described integrated package U3 and the equal ground connection of 8 pin; 4 pin of described integrated package U3 meet the output terminal W0 of square-wave generator through resistance R 4; 5 pin of described integrated package U3 meet the output terminal W1 of square-wave generator through resistance R 5; 6 pin of described integrated package U3 meet the output terminal W2 of square-wave generator through resistance R 6.
Described normalized current source comprises amplifier U4, resistance R 9-R14; Described amplifier U4 comprises U4A unit and U4B unit;
In-phase input end 3 pin of described U4A unit divide two branch roads, and wherein a branch road is through connect+5V of resistance R 13 direct supply, and another branch road connects output terminal 7 pin of U4B unit through resistance R 12; Inverting input 2 pin of described U4A unit divide two branch roads, and wherein a branch road connects output terminal 1 pin of U4A unit through resistance R 10, and another branch road is through resistance R 9 ground connection; Output terminal 1 pin of described U4A unit meets the output terminal COM in described normalized current source successively through resistance R 11, R14;
In-phase input end 5 pin of described U4B unit connect the node of described resistance R 11 and R14; Inverting input 6 pin of described U4B unit connect output terminal 7 pin of U4B unit; Connect+12V of the 8 pin direct supply of described amplifier U4B; Connect-12V of the 4 pin direct supply of described amplifier U4B.
Described signal route N1 comprises U5A unit, capacitor C 5, resistance R 15-R18 and the relay J 1 of amplifier U5; Described resistance R 15 connect with resistance R 17 after between be connected on+24V direct supply and ground; In-phase input end 3 pin of the U5A unit of described amplifier U5 connect the node of described resistance R 15 and resistance R 17; Described resistance R 16 is connected on after connecting with resistance R 18 between the input end I2 and ground of described signal route N1; Inverting input 2 pin of the U5A unit of described amplifier U5 connect the node of described resistance R 16 and resistance R 18; U5A unit connect+24V of the 8 pin direct supply of described amplifier U5; Between described capacitor C 5 be connected on+24V direct supply and ground; 4 pin ground connection of the U5A unit of described amplifier U5;
Between U5A unit output terminal 1 pin of the coil of described relay J 1 be connected on+24V direct supply and described amplifier U5; Swing arm 1 pin of described relay J 1 meets the output terminal O1 of described signal route N1; Swing arm 2 pin of described relay J 1 meet the output terminal O2 of described signal route N1; Stationary contact 3 pin of described relay J 1 meet described signal route N1 input end I2; Moving contact 4 pin of described relay J 1 are unsettled; Stationary contact 5 pin of described electrical equipment J1 meet the input end I1 of described signal route N1; Moving contact 6 pin of described relay J 1 meet the input end I2 of described signal route N1;
Described signal route N2 comprises U5B unit, resistance R 19-R22 and the relay J 2 of amplifier U5; Described resistance R 19 connect with resistance R 21 after between be connected on+24V direct supply and ground; In-phase input end 5 pin of the U5B unit of described amplifier U5 connect the node of described resistance R 19 and resistance R 21; Described resistance R 20 is connected on after connecting with resistance R 22 between the input end I4 and ground of described signal route N2; Inverting input 6 pin of the U5B unit of described amplifier U5 connect the node of described resistance R 20 and resistance R 22;
Between U5B unit output terminal 7 pin of the coil of described relay J 2 be connected on+24V direct supply and described amplifier U5; Swing arm 1 pin of described relay J 2 meets the output terminal O3 of described signal route N2; Swing arm 2 pin of described relay J 2 meet the output terminal O4 of described signal route N2; Stationary contact 3 pin of described relay J 2 are unsettled; The moving contact 4 pin ground connection of described relay J 2; Stationary contact 5 pin of described relay J 2 meet the input end I5 of described signal route N2; Moving contact 6 pin of described relay J 2 meet the input end I6 of described signal route N2.
Described signal route N3 comprises amplifier U6B, resistance R 23-R26, capacitor C 6 and relay J 3; Described resistance R 23 connect with resistance R 25 after between be connected on+24V direct supply and ground; In-phase input end 5 pin of described amplifier U6B connect the node of described resistance R 23 and resistance R 25; Described resistance R 24 is connected on after connecting with resistance R 26 between the input end I7 and ground of described signal route N3; Inverting input 6 pin of described amplifier U6B connect the node of described resistance R 24 and resistance R 26; Connect+24V of the 8 pin direct supply of described amplifier U6B; Between described capacitor C 7 be connected on+24V direct supply and ground; The power end 4 pin ground connection of described amplifier U6B;
Between output terminal 7 pin of the coil of described relay J 3 be connected on+24V direct supply and described amplifier U6B; Swing arm 1 pin of described relay J 3 meets the output terminal O5 of described signal route N3; Swing arm 2 pin of described relay J 3 are unsettled; Stationary contact 3 pin of described relay J 3 are unsettled; Moving contact 4 pin of described relay J 3 meet the input end I6 of described signal route N3; Stationary contact 5 pin of described relay J 3 are unsettled; Moving contact 6 pin of described relay J 3 meet the input end I7 of described signal route N3.
The model of described reference source chip U1 is ADR425AR; The model of described amplifier U2 is AD8512AR; The model of described integrated package U3 is CD4060BCM; The model of described amplifier U4 is AD8512AR; The model of described amplifier U5 is LM293; The model of described amplifier U6B is LM293; The model of described relay J 1-J3 is HF4/5-G6K-2P.
Good effect of the present utility model is as follows:
Self-checking function is extremely important in the design of whole automatic checkout system, only possesses the automatic checkout system of self-checking function, just more true and reliable to the test of measurand and fault diagnosis, localization of fault.The utility model makes full use of the hardware resource of automatic checkout system itself, in the situation that only increasing a small amount of adjunct circuit (self-test adapter), complete its self-checking function, simple in structure, reliability is high, realized the detection of this automatic checkout system and fault isolation, ensured the accuracy of test.
Accompanying drawing explanation
Fig. 1 is theory diagram of the present utility model;
Fig. 2 is reference source circuit schematic diagram of the present utility model;
Fig. 3 is square-wave generator circuit schematic diagram of the present utility model;
Fig. 4 is normalized current source circuit schematic diagram of the present utility model;
Fig. 5 is signal router N1-N2 circuit theory diagrams of the present utility model;
Fig. 6 is signal router N3 circuit theory diagrams of the present utility model.
Embodiment
Automatic checkout system based on PXI bus comprises PXI module, VPC connector, self-test adapter, the controller that automatic checkout system software is installed and the keyboard being connected with controller, display, described PXI module comprises digital I/O module (model is NI PXI-6509), multi-functional DAQ module (model is NI PXI-6259), simulating signal generation module (model is NI PXI-6723), high voltage multiplexer module (model is NI PXI-2527), the first to second universal switch module (model is NI PXI-2576), first to fourth intermediate frequency switch module (model is NI PXI-2593), the first to second Digital Oscillograph Module (model is NI PXI-5152), the first virtual arbitrary waveform generator module (model is NI PXI-5412), the second virtual arbitrary waveform generator module (model is NI PXI-5441), digital multimeter module (model is NI PXI-4070), the first to second dynamic signal acquisition module (model is NI PXI-4461), RS232 serial interface module (model is NI PXI-8430), CAN interface module (model is NI PXI-8511) and optics isolation digital input module (model is NI SCXI-1162).
From the embodiment shown in Fig. 1-6, the present embodiment comprises normalized current source, measuring resistance R, reference source circuit, square-wave generator, signal router N1-N3 and the first to the 5th Copper Foil short-circuit line;
The output terminal COM in described normalized current source connects VPC connector the 1st groove respective input of described automatic checkout system; The input end I1 of the D1 termination signal router N1 of described measuring resistance R, the output terminal O4 of the D2 termination signal router N2 of described measuring resistance R; The output terminal REF of described reference source circuit meets the input end I5 of signal router N2; The input end I2 of described signal router N1 meets the input end I4 of signal router N2, connects the simulating signal generation module output terminal of described automatic checkout system through the VPC of described automatic checkout system connector the 2nd groove simultaneously; The output terminal O1 of described signal router N1 connects VPC connector the 1st groove respective input of described automatic checkout system; The output terminal O2 of described signal router N1 meets the input end I3 of described signal router N2; The output terminal O3 of described signal router N2 connects the multi-functional DAQ module of described automatic checkout system through the VPC of described automatic checkout system connector the 3rd groove; VPC connector the 1st groove output terminal of described automatic checkout system connects respectively the respective input of the high voltage multiplexer module of described automatic checkout system; The input end of the output termination digital multimeter module of the high voltage multiplexer module of described automatic checkout system;
The output terminal W0 of described square-wave generator meets the input end I6 of signal router N3; The output terminal W1 of described square-wave generator connects the first dynamic signal acquisition module input through the VPC of described automatic checkout system connector the 8th groove, the first universal switch module successively; The output terminal W2 of described square-wave generator connects the second dynamic signal acquisition module input through the VPC of described automatic checkout system connector the 9th groove, the second universal switch module successively;
The input end I7 of described signal router N3 divides two branch roads, wherein a branch road connects the output terminal of the first virtual arbitrary waveform generator module successively through the VPC of described automatic checkout system connector the 6th groove, the 3rd intermediate frequency switch module, and another branch road connects the output terminal of the second virtual arbitrary waveform generator module successively through the VPC of described automatic checkout system connector the 7th groove, the 4th intermediate frequency switch module; The output terminal O5 of described signal router N3 divides two branch roads, wherein a branch road connects the input end of the first Digital Oscillograph Module successively through the VPC of described automatic checkout system connector the 4th groove, the first intermediate frequency switch module, and another branch road connects the input end of the second Digital Oscillograph Module successively through the VPC of described automatic checkout system connector the 5th groove, the second intermediate frequency switch module;
The first end of described the first Copper Foil short-circuit line is two-way connection of digital I/O module corresponding end with described automatic checkout system through the VPC of described automatic checkout system connector the 10th groove, and the second end of described the first Copper Foil short-circuit line is two-way connection of digital I/O module corresponding end with described automatic checkout system through the VPC of described automatic checkout system connector the 10th groove; Described the second Copper Foil short-circuit line first end is optics isolation digital input module two-way connection of corresponding end with described automatic checkout system through the VPC of described automatic checkout system connector the 10th groove, and described second Copper Foil short-circuit line the second end is optics isolation digital input module two-way connection of corresponding end with described automatic checkout system through the VPC of described automatic checkout system connector the 10th groove;
The first end of described the 3rd Copper Foil short-circuit line is held two-way connection through the VPC of described automatic checkout system connector the 11st groove with the H of the CAN1 of the CAN interface module of described automatic checkout system; The second end of described the 3rd Copper Foil short-circuit line is held two-way connection through the VPC of described automatic checkout system connector the 11st groove with the H of the CAN2 of the CAN interface module of described automatic checkout system; The first end of described the 4th Copper Foil short-circuit line is held two-way connection through the VPC of described automatic checkout system connector the 11st groove with the L of the CAN1 of the CAN interface module of described automatic checkout system; The second end of described the 4th Copper Foil short-circuit line is held two-way connection through the VPC of described automatic checkout system connector the 11st groove with the L of the CAN2 of the CAN interface module of described automatic checkout system;
The first end of described the 5th Copper Foil short-circuit line meets the RS232 serial interface module transmitting terminal TX of described automatic checkout system through the VPC of described automatic checkout system connector the 11st groove, the second end of described the 5th Copper Foil short-circuit line meets the receiving end RX of the RS232 serial interface module of described automatic checkout system through the VPC of described automatic checkout system connector the 11st groove;
The control end of the high voltage multiplexer module of described automatic checkout system, the control end of digital multimeter module, the control end of simulating signal generation module, the control end of multi-functional DAQ module, the control end of the first to second virtual arbitrary waveform generator module, the control end of the first to second Digital Oscillograph Module, the control end of first to fourth intermediate frequency switch module, the control end of first to fourth universal switch module, the control end of the first to second dynamic signal acquisition module, the control of numeral I/O module, the control end of optics isolation digital input module, the control end of the control end of CAN interface module and RS232 serial interface module respectively with two-way connection of controller corresponding port of described automatic checkout system.
Described reference source circuit comprises reference source chip U1, amplifier U2, resistance R 1 and capacitor C 1-C2;
Described capacitor C 1 is connected between input end 2 pin and ground of reference source chip U1; Described capacitor C 2 is connected between output terminal 6 pin and ground of reference source chip U1; The 4 pin ground connection of described reference source chip U1; Connect+12V of the power end 8 pin direct supply of described amplifier U2; Connect-12V of the power end 4 pin direct supply of described amplifier U2.
Described square-wave generator comprises integrated package U3, crystal oscillator Y1, resistance R 2-R6 and capacitor C 3-C4; 11 pin of described integrated package U3 connect 8 pin of integrated package U3 successively through crystal oscillator Y1, capacitor C 4; Described resistance R 2 is in parallel with crystal oscillator Y1; Described capacitor C 3 is connected between 11 pin and 8 pin of integrated package U3; Described resistance R 3 is connected between the node of crystal oscillator Y1 and capacitor C 2 and 10 pin of integrated package U3; Connect+12V of the 16 pin direct supply of described integrated package U3; 12 pin of described integrated package U3 and the equal ground connection of 8 pin; 4 pin of described integrated package U3 meet the output terminal W0 of square-wave generator through resistance R 4; 5 pin of described integrated package U3 meet the output terminal W1 of square-wave generator through resistance R 5; 6 pin of described integrated package U3 meet the output terminal W2 of square-wave generator through resistance R 6.
Described normalized current source comprises amplifier U4, resistance R 9-R14; Described amplifier U4 comprises U4A unit and U4B unit;
In-phase input end 3 pin of described U4A unit divide two branch roads, and wherein a branch road is through connect+5V of resistance R 13 direct supply, and another branch road connects output terminal 7 pin of U4B unit through resistance R 12; Inverting input 2 pin of described U4A unit divide two branch roads, and wherein a branch road connects output terminal 1 pin of U4A unit through resistance R 10, and another branch road is through resistance R 9 ground connection; Output terminal 1 pin of described U4A unit meets the output terminal COM in described normalized current source successively through resistance R 11, R14;
In-phase input end 5 pin of described U4B unit connect the node of described resistance R 11 and R14; Inverting input 6 pin of described U4B unit connect output terminal 7 pin of U4B unit; Connect+12V of the 8 pin direct supply of described amplifier U4B; Connect-12V of the 4 pin direct supply of described amplifier U4B.
Described signal route N1 comprises U5A unit, capacitor C 5, resistance R 15-R18 and the relay J 1 of amplifier U5; Described resistance R 15 connect with resistance R 17 after between be connected on+24V direct supply and ground; In-phase input end 3 pin of the U5A unit of described amplifier U5 connect the node of described resistance R 15 and resistance R 17; Described resistance R 16 is connected on after connecting with resistance R 18 between the input end I2 and ground of described signal route N1; Inverting input 2 pin of the U5A unit of described amplifier U5 connect the node of described resistance R 16 and resistance R 18; U5A unit connect+24V of the 8 pin direct supply of described amplifier U5; Between described capacitor C 5 be connected on+24V direct supply and ground; 4 pin ground connection of the U5A unit of described amplifier U5;
Between U5A unit output terminal 1 pin of the coil of described relay J 1 be connected on+24V direct supply and described amplifier U5; Swing arm 1 pin of described relay J 1 meets the output terminal O1 of described signal route N1; Swing arm 2 pin of described relay J 1 meet the output terminal O2 of described signal route N1; Stationary contact 3 pin of described relay J 1 meet described signal route N1 input end I2; Moving contact 4 pin of described relay J 1 are unsettled; Stationary contact 5 pin of described electrical equipment J1 meet the input end I1 of described signal route N1; Moving contact 6 pin of described relay J 1 meet the input end I2 of described signal route N1;
Described signal route N2 comprises U5B unit, resistance R 19-R22 and the relay J 2 of amplifier U5; Described resistance R 19 connect with resistance R 21 after between be connected on+24V direct supply and ground; In-phase input end 5 pin of the U5B unit of described amplifier U5 connect the node of described resistance R 19 and resistance R 21; Described resistance R 20 is connected on after connecting with resistance R 22 between the input end I4 and ground of described signal route N2; Inverting input 6 pin of the U5B unit of described amplifier U5 connect the node of described resistance R 20 and resistance R 22;
Between U5B unit output terminal 7 pin of the coil of described relay J 2 be connected on+24V direct supply and described amplifier U5; Swing arm 1 pin of described relay J 2 meets the output terminal O3 of described signal route N2; Swing arm 2 pin of described relay J 2 meet the output terminal O4 of described signal route N2; Stationary contact 3 pin of described relay J 2 are unsettled; The moving contact 4 pin ground connection of described relay J 2; Stationary contact 5 pin of described relay J 2 meet the input end I5 of described signal route N2; Moving contact 6 pin of described relay J 2 meet the input end I6 of described signal route N2.
Described signal route N3 comprises amplifier U6B, resistance R 23-R26, capacitor C 6 and relay J 3; Described resistance R 23 connect with resistance R 25 after between be connected on+24V direct supply and ground; In-phase input end 5 pin of described amplifier U6B connect the node of described resistance R 23 and resistance R 25; Described resistance R 24 is connected on after connecting with resistance R 26 between the input end I7 and ground of described signal route N3; Inverting input 6 pin of described amplifier U6B connect the node of described resistance R 24 and resistance R 26; Connect+24V of the 8 pin direct supply of described amplifier U6B; Between described capacitor C 7 be connected on+24V direct supply and ground; The power end 4 pin ground connection of described amplifier U6B;
Between output terminal 7 pin of the coil of described relay J 3 be connected on+24V direct supply and described amplifier U6B; Swing arm 1 pin of described relay J 3 meets the output terminal O5 of described signal route N3; Swing arm 2 pin of described relay J 3 are unsettled; Stationary contact 3 pin of described relay J 3 are unsettled; Moving contact 4 pin of described relay J 3 meet the input end I6 of described signal route N3; Stationary contact 5 pin of described relay J 3 are unsettled; Moving contact 6 pin of described relay J 3 meet the input end I7 of described signal route N3.
The model of described reference source chip U1 is ADR425AR; The model of described amplifier U2 is AD8512AR; The model of described integrated package U3 is CD4060BCM; The model of described amplifier U4 is AD8512AR; The model of described amplifier U5 is LM293; The model of described amplifier U6B is LM293; The model of described relay J 1-J3 is HF4/5-G6K-2P.
The electric current of described normalized current source output is 5mA.
Described measuring resistance R resistance is 10k Ω.
Described square-wave generator principle of work:
That described integrated package U3 selects is 14 binary divider CD4060BCM.Pinout is as follows:
1 pin: 12 frequency division outputs; 2 pin: 13 frequency division outputs; 3 pin: 14 frequency division outputs;
4 pin: 6 frequency division outputs; 5 pin: 5 frequency division outputs; 6 pin: 7 frequency division outputs;
7 pin: 4 frequency division outputs; 8 pin: ground; 9 pin: signal forward output;
10 pin: signals reverse output; 11 pin: signal input; 12 pin: reset signal input;
13 pin: 9 frequency division outputs; 14 pin: 8 frequency division outputs; 15 pin: 10 frequency division outputs;
16 pin: power supply+12V;
By crystal oscillator, produce pulse, through shaping frequency division, obtain the waveform needing.What in this circuit, use is the crystal oscillator of 32kHz.The W0 signal of the 4 pin outputs of described integrated package U3 is square waves of 32kHz/6=5.33kHz, and the W1 signal of 5 pin outputs is square waves of 32kHz5=6.4kHz, and the W2 signal of 6 pin outputs is square waves of 32kHz/7=4.57kHz.
Described reference source circuit principle of work:
Described reference source chip U1 selects the reference source chip ADR425 of U.S. Analog Device company.This chip is easy to use, and input voltage range is wide, and output+5V voltage accuracy is high, and initial precision can reach 0.4%, and environmental suitability is strong, and working temperature can reach-40 ~ 125 ℃.In this circuit, input voltage use is+12V voltage, and capacitor C 1 is for the filtering of input power, and C2 is for the filtering of out-put supply, and reference source ADR425 output pin 6 pin output+5V reference sources are by outputing in circuit after ratio discharge circuit in the same way.
The specific works process of the present embodiment is as follows:
Described digital multimeter module gathers the output signal in normalized current source, and whether checking digital multimeter module is measured function of current normal.If the current value of the numerical value that the display being connected with controller shows and the output of normalized current source circuit is consistent, digital multimeter module measurement function of current is normal; Otherwise there is fault in described digital multimeter module measuring resistance function.
Signal router N1-N2 principle of work: what described amplifier U5 selected is voltage comparator, model is LM293, it is doubleway output comparer.When 2 pin input voltages are greater than 3 pin input voltage, 1 pin is output low level, otherwise exports high level; When should 6 pin input voltages being greater than 5 pin input voltage, 7 pin are output low level, otherwise export high level.When described simulating signal generation module is not exported, whether standard signal+5V that described multi-functional DAQ module gathers reference source circuit output is normal to verify multi-functional DAQ functions of modules; When simulating signal generation module output voltage is greater than A and is less than B, whether the voltage that multi-functional DAQ module gathers the output of simulating signal generation module works with checking simulating signal generation module, and whether the measuring resistance of digital multimeter module collection simultaneously R is normal with checking digital multimeter module measuring resistance function; When simulating signal generation module output voltage is greater than B, whether the voltage signal of now digital multimeter module collection simulating signal generation module output is normal with checking digital multimeter module measuring voltage function.The A here and B can carry out size adjustment by resistance R 20 and R16.Specific algorithm is as follows:
(24V*R19)/(R19+R21)?=?(A*R20)/(R20+R22)，
(24V*R15)/(R15+R17)?=?(B*R16)/(R16+R18)。
Described signal router N3 principle of work: described amplifier U6B is voltage comparator, model is LM293, it is doubleway output comparer.When 2 pin input voltages are greater than 3 pin input voltage, 1 pin is output low level, otherwise exports high level; When should 6 pin input voltages being greater than 5 pin input voltage, 7 pin are output low level, otherwise export high level.The signal of described the first virtual arbitrary waveform generator module and the second virtual arbitrary waveform generator module is the input end I7 of input signal router N3 successively chronologically, and described the first Digital Oscillograph Module and the second Digital Oscillograph Module receive the output signal of the output terminal O5 of signal router N3 chronologically successively.When the input voltage (described the first virtual arbitrary waveform generator module gathering the successively chronologically or output signal of the second virtual arbitrary waveform generator module) of input end I7 is less than or equal to A1, whether described the first Digital Oscillograph Module and the second Digital Oscillograph Module gather the signal W0 of square wave output chronologically successively, normal to verify the first Digital Oscillograph Module and the second Digital Oscillograph Module function; Otherwise, whether described the first Digital Oscillograph Module and the second Digital Oscillograph Module gather the signal of described the first virtual arbitrary waveform generator module (or second virtual arbitrary waveform generator module) chronologically successively, normal to verify the function of described the first virtual arbitrary waveform generator module (or second virtual arbitrary waveform generator module).The A1 here can carry out size adjustment by R24, and specific algorithm is as follows:
(24V*R23)/(R23+R25)?=?(A1*R24)/(R24+R26)。
Described the first dynamic signal acquisition module gathers the output signal W1 of described square-wave generator, verifies that whether the first dynamic signal acquisition functions of modules is normal.If the waveform of the waveform that the display being connected with controller shows and the output signal W1 of described square-wave generator is consistent, the first dynamic signal acquisition functions of modules is normal; Otherwise there is fault in display report dynamic signal acquisition module.
Described the second dynamic signal acquisition module gathers the output signal W2 of described square-wave generator, verifies that whether the function of the second dynamic signal acquisition module is normal.If the waveform of the waveform that the display being connected with controller shows and the output signal W2 of described square-wave generator is consistent, the function of the second dynamic signal acquisition module is normal; Otherwise there is fault in display report the second dynamic signal acquisition module.
One of them passage of digital I/O module is made as to output, output high level or low level, another passage is made as input, gathers the high or low level signal of output channel output, and compares with it.If consistent, illustrate that its function is normal; Otherwise, illustrate that it exists fault.If normal, change the passage that is made as output into input, change the passage that is made as input into output, again gather relatively, if consistent, illustrate that its function is normal; Otherwise, illustrate that it exists fault.
One of them passage of optics being isolated to digital input module is made as output, output high level or low level, and another passage is made as input, gathers the high or low level signal of output channel output, and compares with it.If consistent, illustrate that its function is normal; Otherwise, illustrate that it exists fault.If normal, change the passage that is made as output into input, change the passage that is made as input into output, again gather relatively, if consistent, illustrate that its function is normal; Otherwise, illustrate that it exists fault.
By the Copper Foil short-circuit line short circuit for H end of the H end of CAN interface module CAN1 and CAN2, by the Copper Foil short-circuit line short circuit for L end of the L end of CAN interface module CAN1 and CAN2, by CAN1, send a string data, CAN2 receives data, and it is consistent whether the data that observation CAN2 receives send with CAN1.If it is qualified to be unanimously, otherwise it is fault.
By the transmitting terminal TX of RS232 serial interface module and receiving end RX Copper Foil short-circuit line short circuit, internal loopback.Transmitting terminal TX sends a string data, then observes the data consistent whether data that receiving end RX receives send with transmitting terminal TX.If it is qualified that the data consistent that the data that receiving end RX receives and transmitting terminal TX send is, otherwise be fault.
Claims (7)
1. a self-test adapter for the bus automatic checkout system based on PXI, is characterized in that: comprise normalized current source, measuring resistance R, reference source circuit, square-wave generator, signal router N1-N3 and the first to the 5th Copper Foil short-circuit line;
The output terminal COM in described normalized current source connects VPC connector the 1st groove respective input of described automatic checkout system; The input end I1 of the D1 termination signal router N1 of described measuring resistance R, the output terminal O4 of the D2 termination signal router N2 of described measuring resistance R; The output terminal REF of described reference source circuit meets the input end I5 of signal router N2; The input end I2 of described signal router N1 meets the input end I4 of signal router N2, connects the simulating signal generation module output terminal of described automatic checkout system through the VPC of described automatic checkout system connector the 2nd groove simultaneously; The output terminal O1 of described signal router N1 connects VPC connector the 1st groove respective input of described automatic checkout system; The output terminal O2 of described signal router N1 meets the input end I3 of described signal router N2; The output terminal O3 of described signal router N2 connects the multi-functional DAQ module of described automatic checkout system through the VPC of described automatic checkout system connector the 3rd groove; VPC connector the 1st groove output terminal of described automatic checkout system connects respectively the respective input of the high voltage multiplexer module of described automatic checkout system; The input end of the output termination digital multimeter module of the high voltage multiplexer module of described automatic checkout system;
The output terminal W0 of described square-wave generator meets the input end I6 of signal router N3; The output terminal W1 of described square-wave generator connects the first dynamic signal acquisition module input through the VPC of described automatic checkout system connector the 8th groove, the first universal switch module successively; The output terminal W2 of described square-wave generator connects the second dynamic signal acquisition module input through the VPC of described automatic checkout system connector the 9th groove, the second universal switch module successively;
The input end I7 of described signal router N3 divides two branch roads, wherein a branch road connects the output terminal of the first virtual arbitrary waveform generator module successively through the VPC of described automatic checkout system connector the 6th groove, the 3rd intermediate frequency switch module, and another branch road connects the output terminal of the second virtual arbitrary waveform generator module successively through the VPC of described automatic checkout system connector the 7th groove, the 4th intermediate frequency switch module; The output terminal O5 of described signal router N3 divides two branch roads, wherein a branch road connects the input end of the first Digital Oscillograph Module successively through the VPC of described automatic checkout system connector the 4th groove, the first intermediate frequency switch module, and another branch road connects the input end of the second Digital Oscillograph Module successively through the VPC of described automatic checkout system connector the 5th groove, the second intermediate frequency switch module;
The first end of described the first Copper Foil short-circuit line is two-way connection of digital I/O module corresponding end with described automatic checkout system through the VPC of described automatic checkout system connector the 10th groove, and the second end of described the first Copper Foil short-circuit line is two-way connection of digital I/O module corresponding end with described automatic checkout system through the VPC of described automatic checkout system connector the 10th groove; Described the second Copper Foil short-circuit line first end is optics isolation digital input module two-way connection of corresponding end with described automatic checkout system through the VPC of described automatic checkout system connector the 10th groove, and described second Copper Foil short-circuit line the second end is optics isolation digital input module two-way connection of corresponding end with described automatic checkout system through the VPC of described automatic checkout system connector the 10th groove;
The first end of described the 3rd Copper Foil short-circuit line is held two-way connection through the VPC of described automatic checkout system connector the 11st groove with the H of the CAN1 of the CAN interface module of described automatic checkout system; The second end of described the 3rd Copper Foil short-circuit line is held two-way connection through the VPC of described automatic checkout system connector the 11st groove with the H of the CAN2 of the CAN interface module of described automatic checkout system; The first end of described the 4th Copper Foil short-circuit line is held two-way connection through the VPC of described automatic checkout system connector the 11st groove with the L of the CAN1 of the CAN interface module of described automatic checkout system; The second end of described the 4th Copper Foil short-circuit line is held two-way connection through the VPC of described automatic checkout system connector the 11st groove with the L of the CAN2 of the CAN interface module of described automatic checkout system;
The first end of described the 5th Copper Foil short-circuit line meets the RS232 serial interface module transmitting terminal TX of described automatic checkout system through the VPC of described automatic checkout system connector the 11st groove, the second end of described the 5th Copper Foil short-circuit line meets the receiving end RX of the RS232 serial interface module of described automatic checkout system through the VPC of described automatic checkout system connector the 11st groove;
The control end of the high voltage multiplexer module of described automatic checkout system, the control end of digital multimeter module, the control end of simulating signal generation module, the control end of multi-functional DAQ module, the control end of the first to second virtual arbitrary waveform generator module, the control end of the first to second Digital Oscillograph Module, the control end of first to fourth intermediate frequency switch module, the control end of first to fourth universal switch module, the control end of the first to second dynamic signal acquisition module, the control of numeral I/O module, the control end of optics isolation digital input module, the control end of the control end of CAN interface module and RS232 serial interface module respectively with two-way connection of controller corresponding port of described automatic checkout system.
2. the self-test adapter of a kind of automatic checkout system based on PXI bus according to claim 1, is characterized in that: described reference source circuit comprises reference source chip U1, amplifier U2, resistance R 1 and capacitor C 1-C2;
Input end 2 pin of described reference source chip U1 are through connect+12V of resistance R 1 direct supply; Output terminal 6 pin of described reference source chip U1 connect in-phase input end 3 pin of amplifier U2; Inverting input 2 pin of described amplifier U2 connect output terminal 1 pin of amplifier U2, the output terminal REF that output terminal 1 pin of described amplifier U2 is reference source circuit;
Described capacitor C 1 is connected between input end 2 pin and ground of reference source chip U1; Described capacitor C 2 is connected between output terminal 6 pin and ground of reference source chip U1; The 4 pin ground connection of described reference source chip U1; Connect+12V of the power end 8 pin direct supply of described amplifier U2; Connect-12V of the power end 4 pin direct supply of described amplifier U2.
3. the self-test adapter of a kind of automatic checkout system based on PXI bus according to claim 2, is characterized in that: described square-wave generator comprises integrated package U3, crystal oscillator Y1, resistance R 2-R6 and capacitor C 3-C4; 11 pin of described integrated package U3 connect 8 pin of integrated package U3 successively through crystal oscillator Y1, capacitor C 4; Described resistance R 2 is in parallel with crystal oscillator Y1; Described capacitor C 3 is connected between 11 pin and 8 pin of integrated package U3; Described resistance R 3 is connected between the node of crystal oscillator Y1 and capacitor C 2 and 10 pin of integrated package U3; Connect+12V of the 16 pin direct supply of described integrated package U3; 12 pin of described integrated package U3 and the equal ground connection of 8 pin; 4 pin of described integrated package U3 meet the output terminal W0 of square-wave generator through resistance R 4; 5 pin of described integrated package U3 meet the output terminal W1 of square-wave generator through resistance R 5; 6 pin of described integrated package U3 meet the output terminal W2 of square-wave generator through resistance R 6.
4. the self-test adapter of a kind of automatic checkout system based on PXI bus according to claim 3, is characterized in that: described normalized current source comprises amplifier U4, resistance R 9-R14; Described amplifier U4 comprises U4A unit and U4B unit;
In-phase input end 3 pin of described U4A unit divide two branch roads, and wherein a branch road is through connect+5V of resistance R 13 direct supply, and another branch road connects output terminal 7 pin of U4B unit through resistance R 12; Inverting input 2 pin of described U4A unit divide two branch roads, and wherein a branch road connects output terminal 1 pin of U4A unit through resistance R 10, and another branch road is through resistance R 9 ground connection; Output terminal 1 pin of described U4A unit meets the output terminal COM in described normalized current source successively through resistance R 11, R14;
In-phase input end 5 pin of described U4B unit connect the node of described resistance R 11 and R14; Inverting input 6 pin of described U4B unit connect output terminal 7 pin of U4B unit; Connect+12V of the 8 pin direct supply of described amplifier U4B; Connect-12V of the 4 pin direct supply of described amplifier U4B.
5. the self-test adapter of a kind of automatic checkout system based on PXI bus according to claim 4, is characterized in that: described signal route N1 comprises U5A unit, capacitor C 5, resistance R 15-R18 and the relay J 1 of amplifier U5; Described resistance R 15 connect with resistance R 17 after between be connected on+24V direct supply and ground; In-phase input end 3 pin of the U5A unit of described amplifier U5 connect the node of described resistance R 15 and resistance R 17; Described resistance R 16 is connected on after connecting with resistance R 18 between the input end I2 and ground of described signal route N1; Inverting input 2 pin of the U5A unit of described amplifier U5 connect the node of described resistance R 16 and resistance R 18; U5A unit connect+24V of the 8 pin direct supply of described amplifier U5; Between described capacitor C 5 be connected on+24V direct supply and ground; 4 pin ground connection of the U5A unit of described amplifier U5;
Between U5A unit output terminal 1 pin of the coil of described relay J 1 be connected on+24V direct supply and described amplifier U5; Swing arm 1 pin of described relay J 1 meets the output terminal O1 of described signal route N1; Swing arm 2 pin of described relay J 1 meet the output terminal O2 of described signal route N1; Stationary contact 3 pin of described relay J 1 meet described signal route N1 input end I2; Moving contact 4 pin of described relay J 1 are unsettled; Stationary contact 5 pin of described electrical equipment J1 meet the input end I1 of described signal route N1; Moving contact 6 pin of described relay J 1 meet the input end I2 of described signal route N1;
Described signal route N2 comprises U5B unit, resistance R 19-R22 and the relay J 2 of amplifier U5; Described resistance R 19 connect with resistance R 21 after between be connected on+24V direct supply and ground; In-phase input end 5 pin of the U5B unit of described amplifier U5 connect the node of described resistance R 19 and resistance R 21; Described resistance R 20 is connected on after connecting with resistance R 22 between the input end I4 and ground of described signal route N2; Inverting input 6 pin of the U5B unit of described amplifier U5 connect the node of described resistance R 20 and resistance R 22;
Between U5B unit output terminal 7 pin of the coil of described relay J 2 be connected on+24V direct supply and described amplifier U5; Swing arm 1 pin of described relay J 2 meets the output terminal O3 of described signal route N2; Swing arm 2 pin of described relay J 2 meet the output terminal O4 of described signal route N2; Stationary contact 3 pin of described relay J 2 are unsettled; The moving contact 4 pin ground connection of described relay J 2; Stationary contact 5 pin of described relay J 2 meet the input end I5 of described signal route N2; Moving contact 6 pin of described relay J 2 meet the input end I6 of described signal route N2.
6. the self-test adapter of a kind of automatic checkout system based on PXI bus according to claim 5, is characterized in that: described signal route N3 comprises amplifier U6B, resistance R 23-R26, capacitor C 6 and relay J 3; Described resistance R 23 connect with resistance R 25 after between be connected on+24V direct supply and ground; In-phase input end 5 pin of described amplifier U6B connect the node of described resistance R 23 and resistance R 25; Described resistance R 24 is connected on after connecting with resistance R 26 between the input end I7 and ground of described signal route N3; Inverting input 6 pin of described amplifier U6B connect the node of described resistance R 24 and resistance R 26; Connect+24V of the 8 pin direct supply of described amplifier U6B; Between described capacitor C 7 be connected on+24V direct supply and ground; The power end 4 pin ground connection of described amplifier U6B;
Between output terminal 7 pin of the coil of described relay J 3 be connected on+24V direct supply and described amplifier U6B; Swing arm 1 pin of described relay J 3 meets the output terminal O5 of described signal route N3; Swing arm 2 pin of described relay J 3 are unsettled; Stationary contact 3 pin of described relay J 3 are unsettled; Moving contact 4 pin of described relay J 3 meet the input end I6 of described signal route N3; Stationary contact 5 pin of described relay J 3 are unsettled; Moving contact 6 pin of described relay J 3 meet the input end I7 of described signal route N3.
7. the self-test adapter of a kind of automatic checkout system based on PXI bus according to claim 6, is characterized in that: the model of described reference source chip U1 is ADR425AR; The model of described amplifier U2 is AD8512AR; The model of described integrated package U3 is CD4060BCM; The model of described amplifier U4 is AD8512AR; The model of described amplifier U5 is LM293; The model of described amplifier U6B is LM293; The model of described relay J 1-J3 is HF4/5-G6K-2P.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106154202A (en) * | 2016-07-26 | 2016-11-23 | 东莞市广安电气检测中心有限公司 | A kind of calibration steps of electrical short-circuit testing & measuring system |
| CN112073710A (en) * | 2020-08-14 | 2020-12-11 | 中国人民解放军32181部队 | Comprehensive device for detecting reconnaissance system |
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2013
- 2013-08-08 CN CN201320483324.6U patent/CN203414503U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106154202A (en) * | 2016-07-26 | 2016-11-23 | 东莞市广安电气检测中心有限公司 | A kind of calibration steps of electrical short-circuit testing & measuring system |
| CN112073710A (en) * | 2020-08-14 | 2020-12-11 | 中国人民解放军32181部队 | Comprehensive device for detecting reconnaissance system |
| CN112073710B (en) * | 2020-08-14 | 2024-03-26 | 中国人民解放军32181部队 | Comprehensive device for detecting reconnaissance system |
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