CN203399122U

CN203399122U - Optical transmitter and receiver of gigabit Network

Info

Publication number: CN203399122U
Application number: CN201320404085.0U
Authority: CN
Inventors: 赵富荣; 赵小明
Original assignee: Xi'an Qingsong Tech Co Ltd
Current assignee: Qstech Co Ltd
Priority date: 2013-07-09
Filing date: 2013-07-09
Publication date: 2014-01-15
Anticipated expiration: 2023-07-09

Abstract

The utility model relates to an optical transmitter and receiver of a gigabit Network. In the screen data transmission technology, a common unshielded twisted pair is sufficient for Gbps level communication speed. As the communication bandwidth increases greatly, the communication distance is limited, and the communication quality and electromagnetic radiation interference are worsened and line laying cost are increased. The optical transmitter and receiver comprises a PHY chip which is respectively connected with a main chip work module selecting circuit, a laser module, a state indicating lamp circuit, a chip resetting circuit, a chip clock circuit and an RJ45 interface, and the laser module is connected with an LC interface. The optical transmitter and receiver realizes long-distance and great bandwidth communication, and supports communication protocol of a gigabit network. Long-distance communication can be realized by installing two transceivers of the optical transmitter and receiver without modifying the structure of an original communication system, and single-fiber bidirectional communication also can be realized.

Description

A kind of kilomega network optical transmitter and receiver

One, technical field:

The utility model belongs to and relates to a kind of kilomega network optical transmitter and receiver.

Two, background technology:

In on-screen data transmission technology, conventional unshielded twisted pair technology can realize the communication speed of Gbps level, but along with increasing considerably of communication bandwidth, communication distance is subject to great restriction, communication quality, electromagnetic interference, track laying cost are in continuous increase.

Three, utility model content:

The utility model is in order to solve the weak point in above-mentioned background technology, a kind of kilomega network optical transmitter and receiver is provided, it is under the prerequisite of gigabit communication bandwidth, significantly extended communication distance, and support kilomega network communication protocol, strengthen the flexibility that screen is installed, reduced the cost of transmission laying-out, guaranteed the stability of communication.

For achieving the above object, the technical solution adopted in the utility model is: a kind of kilomega network optical transmitter and receiver, it is characterized in that: comprise PHY chip, on described PHY chip, be connected with respectively master chip mode of operation and select circuit, laser module, status indicator lamp circuit, chip reset circuit, chip clock circuit and RJ45 interface, on described laser module, be connected with LC interface.

The model of described PHY chip is the BCM54616S of Botong.

Compared with prior art, advantage and the effect that the utlity model has are as follows: the utility model can be realized at a distance, high-bandwidth communication, support kilomega network communication protocol, two transceivers in the situation that not changing former communication system architecture, optical transmitter and receiver being directly installed just can be realized telecommunication, and realize single fiber two-way communication.

Four, accompanying drawing explanation:

Fig. 1 is system architecture diagram of the present utility model;

Fig. 2 is the utility model chip clocking scheme;

Fig. 3 is the utility model laser module circuit diagram;

Fig. 4 is the utility model status indicator lamp circuit diagram;

Fig. 5 is the utility model PHY chip periphery configuration circuit figure;

Reference numeral: 1-PHY chip, 2-master chip mode of operation is selected circuit, 3-laser module, 4-status indicator lamp circuit, 5-chip reset circuit, 6-chip clock circuit, 7-RJ45 interface, 8-LC interface.

Five, embodiment:

Below in conjunction with the drawings and specific embodiments, the utility model is elaborated:

Referring to Fig. 1: a kind of kilomega network optical transmitter and receiver, comprise PHY chip 1, the model of described PHY chip 1 is the BCM54616S of Botong, on described PHY chip 1, be connected with respectively master chip mode of operation and select circuit 2, laser module 3, status indicator lamp circuit 4, chip reset circuit 5, chip clock circuit 6 and RJ45 interface 7, on described laser module 3, be connected with LC interface 8.

Referring to Fig. 2: the clock circuit of kilomega network optical transmitter and receiver, comprise that filter capacitor C16, magnetic bead and decoupling capacitor C17, C18 are connected between the VDD-to-VSS of crystal oscillator, filter capacitor C16 filtering in power supply 3V3 with medium and low frequency disturbance, magnetic bead, decoupling capacitor C17, C18 have eliminated the high-frequency noise in power supply, for crystal oscillator provides pure stable power environment.After crystal oscillator normal operation, just can from clock output pin 3, to master chip, input stable 25MHz clock.

Referring to Fig. 3: the SFP optical module peripheral circuit of kilomega network optical transmitter and receiver, module is universal accessories, buys LC interface optical module and can use.

VCCR and VCCT are receiver and the transmitter power pins of optical module, and by 3.3V power supply, through capacitor C 7 filtering, after magnetic bead FB1, FB2 and decoupling capacitor C5, C6 eliminate power noise, supplying module is used.

VeeR, VeeT are respectively the receiver of optical module and the ground level of transmitter.

MOD_DEF[2:0] be the status pin of optical module, external circuit must be by these 3 pins with moving VCCR or VCCT on the resistance of 4.7 ~ 10K Europe.MOD_DEF[0] pin is used to refer to optical module and whether is inserted into mainboard, and peripheral controller or MAC chip can just judge by the level that reads this.MOD_DEF[1:2] be the serial communication interface pin of optical module, by this interface, can read the string number of optical module.

RD+/-, TD+/-be that the SerDes interface of optical module is used for and outside controller or PHY chip communication.

TXDisable pin, is the transmitter enable pin of optical module, and in normal operation, this pin must pulled down to ground level.On draw or unsettled pin all can be forbidden the transmitter work of optical module.

TXFault and LOS pin are garble status pin, in the design, can ignore.RateSelect is the interface of international standard SFP definition, but does not use in this application.

Referring to Fig. 4: the status indicator lamp of kilomega network optical transmitter and receiver

In figure, LED1, LED2, LED3, LED4 are connected with power supply by 510 Europe resistance, and the other end is connected to the LED[4:1 of master chip] on four pins, before master chip electrification reset, this indicator light circuit plays initialization master chip and configures.After reset finishes, these four led indicator lights are used to refer to the operating state of master chip.

LED[2:1] indicate real-time connection status, Quan Liang to represent the success of 1000BASE-T link connection.

LED[3] indicate real-time data activity state, if having data to send or receive LED[3] will take 167 milliseconds as cycle flicker.

LED[4] indicate real-time interrupt status, if master chip generation internal interrupt signal, LED[4] when will light and wait until interrupt release always (interrupt register is read) just extinguish.

Referring to Fig. 5: the periphery configure circuit of kilomega network optical transmitter and receiver master chip,

REFCLK_SEL[1:0] pin is that master chip BCM53616S(is hereinafter to be referred as master chip) external clock reference select pin, by connecting 3.3V power supply or ground GND forms different level logics and inputs on this pin, master chip can be operated in different clock circuits, comprise that 1. active crystal oscillators 2. are without source crystal 3. low voltage difference clocks, used herein is the configuration mode of 1. active crystal oscillators.

CLKSEL_125 pin is that the 125MHz clock output (not belonging to periphery configure circuit) of master chip offers outside MAC chip use, does not use MAC chip here, so directly by 4.7K Europe grounding through resistance.

RDAC pin is for controlling signal amplitude on kilomega network Difference signal pair, and master chip is adjusted the amplitude of kilomega network differential signal by detecting RDAC pin to the electric current on ground level.Here used the limiting resistance in the 1.24K Europe (precision 1%) of Botong's recommendation.In design, can adjust by adjusting the resistance of this resistance the signal amplitude of kilomega network differential signal, with this, adjust the matching state of communicating by letter of master chip and transformer or MAC chip chamber.

TRST pin, be the reset pin of the jtag interface of master chip, in the debug process of master chip, be used to provide the reset signal of chip debugging interface, adopted generic configuration pattern here, by 1K Europe grounding through resistance, make master chip be operated in normal mode TRST pin.

LOWPWR pin is to control master chip to enter the control pin of " super low-power consumption " pattern, because master chip just starts normal operation until power-off when powering on.So here " super low-power consumption " pattern is forbidden, by LOWPWR pin ground connection.

LED[4:1] pin, be the light pin of master chip, be also the configuration pin of chip initiation state simultaneously.LED[1] be the control pin of " auto negotiation " function, when chip power resets, LED[1] by led and current-limiting resistance by move 3.3V to, indicate master chip power on after network " auto negotiation " function open.LED[2] be the control pin of " full duplex " function, in electrification reset, pin level is locked into control register, LED[2] by led and current-limiting resistance by move 3.3V to, indicate that master chip " full duplex " function of chip after powering on is opened.LED[3:4] cooperated with LED [1] controls the operating rate of master chip, here LED[1], LED[4], LED[3] after powering on, be locked in 111 states, indicate under the 1000BASE-T pattern that master chip works on power in gigabit speed.

RESET pin, is the reset pin of master chip, and right-hand member connects chip reset circuit.

INTERF_SEL[1:0] pin, be that the interface modes of master chip is selected pin, by moving 3.3V on two pins to, form logical one 1 here, chip selection SerDes interface modes is communicated by letter with laser module SFP.

PHYA[4:0] pin, it is the PHY address definition pin of master chip, now according to being defined as 00001 on schematic diagram, PHY address for master chip, when so externally controller need to be accessed a plurality of master chip, a plurality of systems can be articulated in a bus and conduct interviews, and carry out unique difference by PHY address.

MDC, MDIO pin, serial management interface, is the administration configuration interface pin of master chip, is used for reading and controlling the characteristic of PHY chip.Wherein MDC is clock pin, and MDIO is data pin.On to draw the resistance in 1.5K Europe be for the acquiescence level of pin being set, preventing misoperation, be also in order to improve the stability of communication simultaneously.

Application of the present utility model: display converts packet to and transmits at twisted-pair feeder from DVI signal source after kilomega network controller is processed, send on optical transmitter and receiver transmitter, by optical transmitter and receiver, being automatically converted to laser signal sends on receiver through optical fiber, by optical transmitter and receiver receiver, be automatically converted to corresponding packet, send display screen to.Meanwhile, the module control system on display screen also can be encoded signal to send on receiver, by receiver, returns to transmitter, and by kilomega network controller receiving feedback information.

Claims

1. a kilomega network optical transmitter and receiver, it is characterized in that: comprise PHY chip (1), on described PHY chip (1), be connected with respectively master chip mode of operation and select circuit (2), laser module (3), status indicator lamp circuit (4), chip reset circuit (5), chip clock circuit (6) and RJ45 interface (7), on described laser module (3), be connected with LC interface (8).

2. a kind of kilomega network optical transmitter and receiver according to claim 1, is characterized in that: the model of described PHY chip (1) is the BCM54616S of Botong.