CN203399089U - Bi-AD sampling loop for merging unit - Google Patents
Bi-AD sampling loop for merging unit Download PDFInfo
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- CN203399089U CN203399089U CN201320407509.9U CN201320407509U CN203399089U CN 203399089 U CN203399089 U CN 203399089U CN 201320407509 U CN201320407509 U CN 201320407509U CN 203399089 U CN203399089 U CN 203399089U
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Abstract
The utility model discloses a bi-AD sampling loop for a merging unit. The bi-AD sampling loop comprises a CT wire loop with a primary coil, and is characterized in that the secondary of the CT coil comprises a first coil connected with a first sampling resistor which is connected with a first low-pass filter circuit connected with a first A/D sampling circuit and a second coil connected with a second sampling resistor which is connected with a second low-pass filter circuit connected with a second A/D sampling circuit. The bi-AD sampling loop solves the problem of error operation of a digital protective relaying device in a common loop between two AD sampling loops in a conventional bi-AD sampling loop of a merging unit, thereby satisfying the sampling safety and reliability requirements on a merging unit by a digital protective relaying device of an intelligent transformer station and digital transformer station.
Description
Technical field
The utility model relates to the two AD sampling circuits of a kind of merge cells, be specifically related to completely independently two AD sampling circuits of a kind of intelligent substation and digital transformer substation analog input merge cells, the utility model belongs to intelligent substation of electric power system and digital transformer substation equipment development field.
Background technology
Digital transformer substation adopts at present in a large number increases the sampling (be AD sampling) of the application scheme of merge cells realization from analog quantity to digital quantity on traditional instrument transformer basis.At present, the application scheme that domestic traditional instrument transformer adds merge cells has entered the engineering application stage on a large scale.Due to the specification requirement of domestic traditional relay protection for two AD, so must adopt two AD Sampling techniques to meet the requirement of traditional relay protection as its preposition merge cells of sampling.The relaying protection producer that auspicious relay protection at present, state's electricity south are representative from, cubic relay protection samples at merge cells internal configurations two AD that completely independently two cover AD sampling circuits are realized merge cells; so really do not realize completely independently sampling system in device inside but the resistance of its built-in little CT is common return; once also just mean that the resistance of the inside of device damages or the virtual connection of little CT coil all likely can cause the judgement of two AD to be lost efficacy, thereby cause the malfunction of protective relaying device.And merge cells has been not only single relay protection device as its relay protection device affecting of public sample devices; and be directly connected to the overall operation safety of digital transformer substation, so its importance has surpassed the security requirement of traditional relay protection device.If adopt completely independently little CT, volume is excessive and cannot install.
Digital transformer substation application is also fewer in the world, and protective relaying device also seldom has the specification requirement of two AD, so at technical research or the blank out in this field.
Summary of the invention
For solving the deficiencies in the prior art, the purpose of this utility model is to provide a kind of merge cells two AD sampling circuits.
In order to realize above-mentioned target, the utility model adopts following technical scheme:
The two AD sampling circuits of merge cells, comprise CT coil, described CT coil there is a primary coil, it is characterized in that, the secondary of described CT coil comprises the first coil and the second coil; The first coil connects the first sample resistance, and the first sample resistance connects the first low-pass filter circuit, and the first low-pass filter circuit connects an A/D sample circuit; The second coil connects the second sample resistance, and the second sample resistance connects the second low-pass filter circuit, and the second low-pass filter circuit connects the 2nd A/D sample circuit.
The two AD sampling circuits of aforesaid merge cells, is characterized in that, the no-load voltage ratio of described primary coil and the first coil is 5A/0.001A or 1A/0.001A; The no-load voltage ratio of described primary coil and the second coil is 5A/0.001A or 1A/0.001A.
The two AD sampling circuits of aforesaid merge cells, is characterized in that, described the first sample resistance and the second sample resistance are 85 Europe.
The two AD sampling circuits of aforesaid merge cells, is characterized in that, described the first low-pass filter circuit and the second low-pass filter circuit are second-order low-pass filter loop, and the cut-off frequency of described the first low-pass filter circuit and the second low-pass filter circuit is 2000HZ.
The two AD sampling circuits of aforesaid merge cells, is characterized in that, a described A/D sample circuit and the 2nd A/D sample circuit are the AD7656 chip of 16.
The two AD sampling circuits of aforesaid merge cells, is characterized in that, a described A/D sample circuit, the 2nd A/D sample circuit connect respectively main CPU system.
The two AD sampling circuits of aforesaid merge cells, is characterized in that, described main CPU system sampling fpga chip.
Usefulness of the present utility model is: the two AD sampling circuits of merge cells of the present utility model have been eliminated in the two AD sampling circuits of existing merge cells and overlapped between AD sampling circuits and exist common return to cause the hidden danger of digital relay protection device malfunction because of two, therefore can meet intelligent substation and digital transformer substation digital relay protection device for the requirement of the sampling security reliability of merge cells.
Accompanying drawing explanation
Fig. 1 is a structural representation of preferably implementing of the present utility model.
The implication of Reference numeral in figure:
1, the two AD sampling circuits of merge cells, 2, primary coil, 3, the first coil, the 4, second coil, the 5, first sample resistance, 6, the second sample resistance, 7, the first low-pass filter circuit, the 8, second low-pass filter circuit, the 9, the one A/D sample circuit, 10, the 2nd A/D sample circuit, 11, main CPU system.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is done to concrete introduction.
Shown in Fig. 1, the two AD sampling circuits 1 of merge cells of the present utility model, comprise CT coil, CT coil there is a primary coil 2, the secondary of CT coil comprises the first coil 3 and the second coil 4; The first coil 3 connects the first sample resistance 5, the first sample resistances 5 and connects the first low-pass filter circuit 7, the first low-pass filter circuits 7 connection the one A/D sample circuits 9; The second coil 4 connects the second sample resistance 6, the second sample resistances 6 and connects the second low-pass filter circuit 8, the second low-pass filter circuits 8 connection the 2nd A/D sample circuits 10.
The utility model is to start the coil from CT from the source of sampling circuit, be that current transformer enters analog input merge cells and starts that safety is independent, so but because primary coil 2 parts of the reason CT coil of volume and wiring are still constant, therefore guaranteed whole integrality.CT coil adopts single former limit input, single core design, and the secondary of CT coil adopts two covers completely independently second protection coil, i.e. the first coil 3 and the second coil 4.As preferably, the no-load voltage ratio of primary coil 2 and the first coil 3 is 5A/0.001A or 1A/0.001A; The no-load voltage ratio of primary coil 2 and the second coil 4 is 5A/0.001A or 1A/0.001A.In reality, the no-load voltage ratio of primary coil 2 and the first coil 3 is preferably identical no-load voltage ratio with the no-load voltage ratio of primary coil 2 and the second coil 4.
In reality, as further preferably, the utility model can configure identical and two sample resistances completely independently: the first sample resistance 5 and the second sample resistance 6, and to complete analog quantity electric current to the conversion of voltage.Further, the first sample resistance 5 and the second sample resistance 6 are 85 Europe.Further, the first sample resistance 5 and the second sample resistance 6 adopt constant-temperature high-precision resistance, to guarantee the accuracy of merge cells sampling.
As further preferred, the utility model can adopt complete two independent and identical cover second-order low-pass filter loops, to realize merge cells for the limit bandwidth of analog signal.Further, the first low-pass filter circuit 7 and the second low-pass filter circuit 8 are second-order low-pass filter loop, and the cut-off frequency of the first low-pass filter circuit 7 and the second low-pass filter circuit 8 is 2000HZ.The utility model does not limit the concrete structure of the first low-pass filter circuit 7 and the second low-pass filter circuit 8, and those skilled in the art can adopt existing classical second-order low-pass filter loop design.
The utility model can access respectively two independently sample circuits from the two-way analog signals of the first low-pass filter circuit 7 and the second low-pass filter circuit 8 outputs, i.e. an A/D sample circuit 9 and the 2nd A/D sample circuit 10.Due to adopted two independently sample circuit sample to realize analog quantity to the conversion of digital quantity, so the damage that the utility model can not produce due to a road A/D sample circuit causes all A/D sample circuits all to obtain abnormal data.Can utilize self-correcting between two samplings to realize when arbitrary sampling element damages and can not cause the malfunction of digital relay protection, greatly improve the on-the-spot reliability of operation of merge cells.Consideration based on miniaturization, an A/D sample circuit 9 of the present utility model and the 2nd A/D sample circuit 10 are the AD7656 chip of 16.A kind of 16 sample circuits of AD7656 chip Shi You ADI company design, are enough to meet common employing requirement.
In reality, an A/D sample circuit 9, the 2nd A/D sample circuit 10 connect respectively main CPU system 11.Main CPU system 11 is responsible for the employing data of input to process.The utility model does not limit the structure of main CPU system 11, as further preferred, and main CPU system 11 sampling fpga chips.
In addition, when the power-supply system of merge cells of the present utility model is single power supply system, different A/D power-supply systems should be isolated, and AD electric power loop is implemented to self check, to guarantee fail safe, the reliability of A/D sampling circuit.
The two AD sampling circuits 1 of merge cells of the present utility model are completely independent; the two AD sampling circuits that redesign have independence completely; the inner step of its device has any common return again, can be because any individual component damages the malfunction that causes digital relay protection.The utility model, owing to adopting completely independently coil and sample resistance thereof, has guaranteed the good transient characterisitics of twin coil output.The utility model, owing to adopting the technology of single CT twin coil to realize, so its volume does not increase yet, is convenient to the application design of merge cells.The utility model has been eliminated in the two AD sampling circuits 1 of existing merge cells and has been overlapped between AD sampling circuits and exist common return to cause the hidden danger of digital relay protection device malfunction because of two, therefore can meet intelligent substation and digital transformer substation digital relay protection device for the requirement of the sampling security reliability of merge cells.
More than show and described basic principle of the present utility model, principal character and advantage.The technical staff of the industry should understand, and above-described embodiment does not limit the utility model in any form, and all employings are equal to replaces or technical scheme that the mode of equivalent transformation obtains, all drops in protection range of the present utility model.
Claims (7)
1. the two AD sampling circuits of merge cells, comprise CT coil, described CT coil there is a primary coil, it is characterized in that, the secondary of described CT coil comprises the first coil and the second coil; The first coil connects the first sample resistance, and the first sample resistance connects the first low-pass filter circuit, and the first low-pass filter circuit connects an A/D sample circuit; The second coil connects the second sample resistance, and the second sample resistance connects the second low-pass filter circuit, and the second low-pass filter circuit connects the 2nd A/D sample circuit.
2. the two AD sampling circuits of merge cells according to claim 1, is characterized in that, the no-load voltage ratio of described primary coil and the first coil is 5A/0.001A or 1A/0.001A; The no-load voltage ratio of described primary coil and the second coil is 5A/0.001A or 1A/0.001A.
3. the two AD sampling circuits of merge cells according to claim 2, is characterized in that, described the first sample resistance and the second sample resistance are 85 Europe.
4. two AD sampling circuits of merge cells according to claim 3, it is characterized in that, described the first low-pass filter circuit and the second low-pass filter circuit are second-order low-pass filter loop, and the cut-off frequency of described the first low-pass filter circuit and the second low-pass filter circuit is 2000HZ.
5. the two AD sampling circuits of merge cells according to claim 4, is characterized in that, a described A/D sample circuit and the 2nd A/D sample circuit are the AD7656 chip of 16.
6. the two AD sampling circuits of merge cells according to claim 5, is characterized in that, a described A/D sample circuit, the 2nd A/D sample circuit connect respectively main CPU system.
7. the two AD sampling circuits of merge cells according to claim 6, is characterized in that, described main CPU system sampling fpga chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320407509.9U CN203399089U (en) | 2013-07-10 | 2013-07-10 | Bi-AD sampling loop for merging unit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320407509.9U CN203399089U (en) | 2013-07-10 | 2013-07-10 | Bi-AD sampling loop for merging unit |
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| CN203399089U true CN203399089U (en) | 2014-01-15 |
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| CN201320407509.9U Expired - Lifetime CN203399089U (en) | 2013-07-10 | 2013-07-10 | Bi-AD sampling loop for merging unit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104332297A (en) * | 2014-09-19 | 2015-02-04 | 国家电网公司 | Current transformer for microcomputer protection device |
| CN104410042A (en) * | 2014-11-11 | 2015-03-11 | 许继集团有限公司 | Intelligent substation relay protection method based on double AD sampling |
| CN105119376A (en) * | 2015-09-09 | 2015-12-02 | 许继集团有限公司 | Routine sampling GOOSE trip mode-based sampling implementation method and apparatus |
-
2013
- 2013-07-10 CN CN201320407509.9U patent/CN203399089U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104332297A (en) * | 2014-09-19 | 2015-02-04 | 国家电网公司 | Current transformer for microcomputer protection device |
| CN104410042A (en) * | 2014-11-11 | 2015-03-11 | 许继集团有限公司 | Intelligent substation relay protection method based on double AD sampling |
| CN104410042B (en) * | 2014-11-11 | 2018-02-02 | 许继集团有限公司 | A kind of intelligent substation relay protecting method based on double AD samplings |
| CN105119376A (en) * | 2015-09-09 | 2015-12-02 | 许继集团有限公司 | Routine sampling GOOSE trip mode-based sampling implementation method and apparatus |
| CN105119376B (en) * | 2015-09-09 | 2017-08-22 | 许继集团有限公司 | A kind of sampling implementation method and device based on routine sampling GOOSE tripped modes |
| US9985428B2 (en) | 2015-09-09 | 2018-05-29 | Xj Group Corporation | Sampling implementation method and device based on conventional sampling goose trip mode |
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Granted publication date: 20140115 |
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| CX01 | Expiry of patent term |