CN203387515U - An outburst reception control circuit and an outburst mode optical receiver - Google Patents
An outburst reception control circuit and an outburst mode optical receiver Download PDFInfo
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- CN203387515U CN203387515U CN201320318247.9U CN201320318247U CN203387515U CN 203387515 U CN203387515 U CN 203387515U CN 201320318247 U CN201320318247 U CN 201320318247U CN 203387515 U CN203387515 U CN 203387515U
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Abstract
The utility model discloses an outburst reception control circuit and an outburst mode optical receiver. The outburst reception control circuit comprises a signal detection module, an inverter, and a TTL D trigger. The signal detection module receives first data signal, and carries out filtering, charging and maintenance processing to obtain direct current voltage signals. If a preset reference voltage threshold value is surpassed, high level detection signals are output to the TTL D trigger. If the preset reference voltage threshold value is not reached, low level detection signals are output to the TTL D trigger. The signal detection module also receives first reset pulse signals, and then discharging is carried out on a charging voltage. The inverter carries out anti-phase processing on the first reset pulse signals and outputs the processed first reset pulse signals to the TTL D trigger. The TTL D trigger, under the control of the first reset pulse signals, outputs turn-off control signals on rising edges of the reception detection signals and outputs conduction control signals on falling edges of the reception detection signals. Through the utilization of the outburst reception control circuit and the outburst mode optical receiver of the utility model, power consumption and costs of the outburst reception control circuit can be reduced.
Description
Technical field
The utility model relates to Fibre Optical Communication Technology, relates in particular to a kind of burst reception control circuit and burst mode optical receiver.
Background technology
Optical-fiber network (PON) is the latticed form a kind of commonly used of realizing broadband optical access, content by carrying is classified, and PON mainly comprises: the EPON based on ATM(Asynchronous Transfer Mode) (APON), broadband passive optical network (BPON), the EPON based on Ethernet (Ethernet) (EPON), the gigabit passive optical network based on Generic Framing Procedure (GFP) (GPON) etc.
Wherein, the GPON technology, for the PON standard more than 1Gb/s, has higher speed, supports full-service, efficiency higher, be suitable for minority high to bandwidth requirement, need to provide the carrier grade service quality, and to the access of the enterprises and institutions of the insensitive multiservice requirement of cost.
Existing GPON system mainly is comprised of optical sender, burst mode optical receiver, optical repeater, optical fiber and optical device etc.Wherein, burst mode optical receiver is for realizing light and electric conversion, be about to be reduced into the signal of telecommunication from the light signal of optical sender, carrying out input (SD) processes, and generate the decision level signal, for example, so that burst mode optical receiver carries out the processing of the signal of telecommunication according to decision level,, amplified, after shaping, regeneration process, formed the data-signal of difference to carry out the follow-up data processing.About structure and the workflow of optical sender, optical repeater, optical fiber and optical device, be known technology, and uncorrelated with the application, do not repeat them here.
Fig. 1 is existing burst mode optical receiver structural representation.Referring to Fig. 1, this burst mode optical receiver comprises: transimpedance amplifier (TIA, Transimpedance Amplifier) 11, decision level are set up circuit 12, burst reception control circuit 13 and limiting amplifier (LA, Limiting Amplifier) 14, wherein
Transimpedance amplifier 11, receive the light signal that optical sender is launched, and after carrying out opto-electronic conversion and amplifying processing, generates corresponding voltage signal, exports respectively limiting amplifier 14 and decision level to and set up circuit 12;
Decision level is set up circuit 12, under the control of the shutoff control signal of exporting at burst reception control circuit 13, generates fast the decision level signal, exports limiting amplifier 14 to; Receive the reseting pulse signal of GPON system output, under the control of the conducting control signal of burst reception control circuit 13 outputs, the decision level signal of quick generation is discharged;
Limiting amplifier 14, for receiving the voltage signal of transimpedance amplifier 11 outputs, the decision level signal of setting up circuit 12 outputs with decision level carries out amplitude limiting processing, outwards export the data differential signals after two-way recovers, simultaneously, data differential signals after two-way recovers, as detection signal, exports burst reception control circuit 13 to; Wherein, the voltage signal that amplitude limiting processing will soon receive and the decision level signal of reception are subtracted each other processing.
Burst reception control circuit 13, according to the two-way voltage differential signal received and from reset pulse (Reset) signal of GPON system, processed, set up circuit 12 output control signals to decision level, set up circuit 12 and generate the decision level signal the light signal duration to control decision level, and, between two light signals that receive in front and back, the decision level signal of quick generation is discharged.
Wherein,
The first input end of limiting amplifier 14 (Di+), receive the voltage signal of transimpedance amplifier 11 outputs, the second input (Di-) receives the decision level signal that decision level is set up circuit 12 outputs, the first output is exported the first voltage differential signal (RD+), the second output output second voltage differential signal (RD-).
Decision level is set up circuit 12 and is comprised: resistance (R) 121, electric capacity (C) 122 and electronic switch (SW) 123, wherein, one end of resistance 121 is connected with the output of transimpedance amplifier 11 and an end of electronic switch 123 respectively, the other end is connected with the other end of electronic switch 123, the second input of limiting amplifier 14 and an end of electric capacity 122 respectively, the other end ground connection of electric capacity 122, the happened suddenly control signal of reception control circuit 13 output of the break-make of electronic switch 123 is controlled.
Burst reception control circuit 13 comprises: emitter coupled logic integrated circuit (ECL, Emitter Coupled Logic IC) d type flip flop 131 and emitter coupled logic integrated circuit/transistor-transistor logic (ECL-TTL, Emitter Coupled Logic IC/Transistor-Transistor Logic) transducer 132, wherein, the first clock signal (CLK+) input of ECL d type flip flop 131 is connected with the first output of limiting amplifier 14, second clock signal (CLK-) input is connected with the second output of limiting amplifier 14, (Reset) signal input part that resets receives the Reset signal of GPON system output, the D input receives high level (VCC) signal, the first output (Q+) is connected with the D+ input of ECL-TTL transducer 132, the second output (Q-) is connected with the D-input of ECL-TTL transducer 132, the Q output of ECL-TTL transducer 132 is connected with electronic switch 123.
In Fig. 1, resistance 121 forms low pass filter with electric capacity 122, and its timeconstantτ meets:
τ≥10t
CID
In formula,
T
cIDfor the duration of maximum consecutive identical digital code in data-signal, wherein, data-signal is the part of the light signal of transmission.
In optical signal transmission, due to the bag guard time (guard time) of GPON agreement regulation, Tg only has 32 bits (bit).For instance, when 1.25G speed, Tg is 25.6ns.Thereby, in the burst mode optical receiver of GPON optical line terminal (OLT), when light signal arrives, need decision level in burst mode optical receiver to set up circuit and can generate at Tg the decision level signal in the time, to ensure the normal process of light signal.
In the GPON system, the optical network unit of each user side (ONU) is different with the distance of the optical line terminal (OLT) of local side.The luminous power of light signal that each ONU sends to OLT is also different, wherein, and more than optical power difference can reach 15dB.For the correct light signal received that recovers, need the signal of the quick output of the transimpedance amplifier to different amplitudes to generate corresponding decision level.
In existing burst mode optical receiver, the burst reception control circuit is under the effect of reset pulse (Reset) signal of the two-way voltage differential signal that receives limiting amplifier output and outside input, the output control signal, control decision level and set up the break-make of electronic switch in circuit, thereby change fast the RC time constant that limiting amplifier is inputted the burst reception control circuit.Specifically, when light signal arrives burst mode optical receiver, now, electronic switch is in conducting state, because the resistance of the electronic switch of conducting is very little, RC circuit with the electric capacity formation, charge constant is very little, thereby, low pass filter can be processed the voltage signal of transimpedance amplifier output fast, obtains recovering for limiting amplifier the direct current mean value of the decision level signal of data-signal, by this RC circuit, can make decision level set up circuit and generate rapidly decision level, and second input (Di-) of input saturation amplifier.Simultaneously, the first input end (Di+) of the direct input saturation amplifier of voltage signal of transimpedance amplifier output, the signal of input first input end and the signal of input the second input, after being subtracted each other in limiting amplifier, the data-signal be restored, i.e. the first voltage differential signal (RD+) and second voltage differential signal (RD-).After decision level generates, the burst reception control circuit turn-offs control signal according to the data-signal output of limiting amplifier output, electronic switch is disconnected fast, resistance 121 forms new RC circuit with electric capacity, time constant now is greater than the duration of maximum consecutive identical digital code in the data-signal of ten times, therefore can maintain the stable of decision level signal, make this charge constant can meet the correct requirement that recovers receiving optical signals medium and low frequency component.After the data-signal end of transmission, the GPON system is according to the configuration of network slot in advance, to burst reception control circuit output reseting pulse signal, the burst reception control circuit is according to reseting pulse signal, to electronic switch output conducting control signal, the electronic switch conducting, the RC circuit that the electronic switch of conducting and electric capacity form, its time constant is very little, can to electric capacity, be discharged fast, the decision level that resets is set up circuit, with the light letter that next cycle is received, is detected.
From above-mentioned, the burst reception control circuit of burst mode optical receiver, adopt ECL d type flip flop and ECL-TTL transducer, and supply current is all at 20～30mA, and ECL d type flip flop and ECL-TTL transducer purchase cost are high, make that burst reception control circuit power consumption is large, cost is high.Especially under high temperature (70 ℃) environment, whole burst reception control circuit power consumption often is greater than 1W, is unfavorable for the lifting of product batch production and the market competitiveness.Further, because burst reception control circuit power consumption is large, caloric value is corresponding increase also, will affect useful life and the job stability of burst mode optical receiver.
The utility model content
Embodiment of the present utility model provides a kind of burst reception control circuit, reduces burst reception control circuit power consumption and cost.
Embodiment of the present utility model also provides a kind of burst mode optical receiver based on the burst reception control circuit, reduces burst reception control circuit power consumption and cost.
For achieving the above object, a kind of burst reception control circuit that the utility model embodiment provides comprises: TTL d type flip flop, signal detection module and inverter, wherein,
Signal detection module, for receiving the first data-signal of limiting amplifier output, carry out filtering, charging and keep processing, obtain d. c. voltage signal, when the magnitude of voltage of the d. c. voltage signal obtained is greater than the reference voltage threshold set in advance, to the detection signal of TTL d type flip flop output high level; When the magnitude of voltage of the d. c. voltage signal obtained is less than the reference voltage threshold set in advance, to the detection signal of TTL d type flip flop output low level; Receive the first reseting pulse signal of GPON system output, charging voltage is discharged;
Inverter, carry out anti-phase processing for the first reseting pulse signal to the output of GPON system, exports the TTL d type flip flop to;
The TTL d type flip flop, under controlling for the first reseting pulse signal anti-phase, rising edge at the detection signal received, set up circuit output to outside decision level and turn-off control signal, at the trailing edge of the detection signal received, to outside decision level, set up circuit output conducting control signal.
Preferably, further comprise:
The pulse stretching module, carry out the broadening processing for the first reseting pulse signal to the output of GPON system, export the second reseting pulse signal to signal detection module, so that signal detection module is discharged to charging voltage according to the second reseting pulse signal received.
Preferably, described signal detection module comprises: isolation resistance, peak-detector circuit, leadage circuit and comparator, wherein,
Isolation resistance, isolated the first data-signal received, and is input to peak-detector circuit;
Peak-detector circuit, carry out filtering, charging and maintenance for the first data-signal to receiving, to comparator output dc voltage signal;
Leadage circuit, after finishing at the first data-signal, receive the first reseting pulse signal of GPON system output, and the voltage signal that peak-detector circuit is exported is discharged;
Comparator, compare for the d. c. voltage signal by reception and the reference voltage set in advance, when the d. c. voltage signal amplitude received is greater than the reference voltage amplitude, to the detection signal of TTL d type flip flop output high level; When the d. c. voltage signal amplitude received is less than the reference voltage amplitude, to the detection signal of TTLD trigger output low level.
Preferably, described peak-detector circuit comprises: the first electric capacity, the first Schottky diode, the second Schottky diode and the second electric capacity, wherein,
One end of the first electric capacity is connected with the output of isolation resistance, and the other end is connected with the negative pole anodal and the second Schottky diode of the first Schottky diode respectively;
The negative pole of the first Schottky diode is connected with an end of the second electric capacity;
The plus earth of the second Schottky diode, and be connected with the other end of the second electric capacity.
Preferably, described peak-detector circuit further comprises:
The first inductance, an end is connected with the other end of the first electric capacity, and the other end is connected with the negative pole anodal and the second Schottky diode of the first Schottky diode respectively.
Preferably, described leadage circuit comprises: bleeder resistance and the first electronic switch, wherein,
One end of bleeder resistance is connected with an end of the second electric capacity respectively with the first end of the first electronic switch, and the second end of the other end of bleeder resistance and the first electronic switch is ground connection respectively, and the 3rd end of the first electronic switch is connected with the output of pulse stretching module.
Preferably, described comparator comprises: in-phase input end, reference voltage input terminal, power end, earth terminal and output, wherein,
In-phase input end, for receiving the voltage signal of peak-detector circuit output;
Reference voltage input terminal, for accessing reference voltage;
Power end, for the cut-in operation power supply;
Earth terminal, for ground connection;
Output, while being greater than the reference voltage amplitude of reference voltage input terminal input for the d. c. voltage signal amplitude in the in-phase input end input, to the detection signal of TTL d type flip flop output high level; When the d. c. voltage signal amplitude of in-phase input end input is less than the reference voltage amplitude of reference voltage input terminal input, to the detection signal of TTL d type flip flop output low level.
Preferably, described comparator further comprises: the first resistance and the second resistance, wherein,
One end of the first resistance is connected with an end of the second electric capacity, and the other end is connected with an end of the second resistance and the in-phase input end of comparator respectively;
The other end of the second resistance is connected with the output of comparator.
Preferably, described pulse stretching module comprises: the 3rd resistance, the 3rd diode and the 3rd electric capacity, wherein,
One end of the 3rd resistance and the positive pole of the 3rd diode receive the first reseting pulse signal, and an end of the negative pole of the other end of the 3rd resistance, the 3rd diode and the 3rd electric capacity is connected with the 3rd end of the first electronic switch, the other end ground connection of the 3rd electric capacity.
Preferably, the data input pin of described TTL d type flip flop and S-end are predisposed to high level, reset terminal receives the first anti-phase reseting pulse signal of inverter output, and the CP termination is received the detection signal of comparator output, and Q-end is set up circuit output break-make control signal to outside decision level.
A kind of burst mode optical receiver based on the burst reception control circuit, this burst mode optical receiver comprises: transimpedance amplifier, decision level are set up circuit, burst reception control circuit and limiting amplifier, wherein,
Transimpedance amplifier, for receiving the light signal that comprises data-signal of exterior light transmitter emission, after carrying out opto-electronic conversion and amplifying processing, generate corresponding voltage signal, export respectively the first input end that decision level is set up circuit and limiting amplifier 54 to;
Decision level is set up circuit, under control for the conducting control signal in the output of burst reception control circuit, if transimpedance amplifier outputting data signals, carry out filtering, charging, generate the decision level signal, export the second input of limiting amplifier to, if transimpedance amplifier outputting data signals is not discharged to the decision level signal generated; Under the control of the shutoff control signal of exporting at the burst reception control circuit, carry out filtering, charging, generate the decision level signal, export the second input of limiting amplifier to;
Limiting amplifier, for the voltage signal by the first input end input, carry out amplitude limiting processing with the decision level signal of the second input input, outwards exports the two-way voltage differential signal, and ，Jiang mono-tunnel voltage differential signal exports the burst reception control circuit to simultaneously;
The burst reception control circuit, according to the road voltage differential signal received and from the first reseting pulse signal of GPON system, processed, set up circuit output control signal to decision level, set up circuit evolving decision level signal to control decision level, and, the decision level signal generated is discharged.
Preferably, described decision level is set up circuit and is comprised: the 4th resistance, the 4th electric capacity and the second electronic switch, wherein,
One end of the 4th resistance is connected with the output of transimpedance amplifier and an end of the second electronic switch respectively, the other end is connected with the other end of the second electronic switch, the second input of limiting amplifier and an end of the 4th electric capacity respectively, the other end ground connection of the 4th electric capacity, the happened suddenly control signal of reception control circuit output of the break-make of the second electronic switch is controlled.
Preferably, described burst reception control circuit comprises: TTL d type flip flop, signal detection module and inverter, wherein,
Signal detection module, for receiving the first data-signal of limiting amplifier output, carry out filtering, charging and keep processing, obtain d. c. voltage signal, when the magnitude of voltage of the d. c. voltage signal obtained is greater than the reference voltage threshold set in advance, to the detection signal of TTL d type flip flop output high level; When the magnitude of voltage of the d. c. voltage signal obtained is less than the reference voltage threshold set in advance, to the detection signal of TTL d type flip flop output low level; Receive the first reseting pulse signal of GPON system output, charging voltage is discharged;
Inverter, carry out anti-phase processing for the first reseting pulse signal to the output of GPON system, exports the TTL d type flip flop to;
The TTL d type flip flop, under controlling for the first reseting pulse signal anti-phase, rising edge at the detection signal received, set up circuit output to outside decision level and turn-off control signal, at the trailing edge of the detection signal received, to outside decision level, set up circuit output conducting control signal.
As seen from the above technical solution, a kind of burst reception control circuit and burst mode optical receiver that the utility model embodiment provides, adopt the TTL d type flip flop, utilize common electronic devices and components to form the signal detection module in the burst reception control circuit, make burst reception control circuit cost lower; A road differential voltage signal to limiting amplifier output carries out respective handling, export decision level to and set up circuit, in order to control the break-make of the second electronic switch, because Zhi Dui mono-road differential voltage signal is processed, can effectively reduce the supply current of burst reception control circuit, power consumption is less, thereby promotes useful life and the job stability of burst mode optical receiver.
The accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described.Apparently, the accompanying drawing in below describing is only embodiment more of the present utility model, for those of ordinary skills, can also obtain according to these accompanying drawing illustrated embodiments other embodiment and accompanying drawing thereof.
Fig. 1 is existing burst mode optical receiver structural representation.
Fig. 2 is the utility model embodiment reception control circuit structural representation that happens suddenly.
Fig. 3 is the utility model embodiment during without the first inductance, the voltage waveform view of peak-detector circuit output.
Fig. 4 is the utility model embodiment while having the first inductance, the voltage waveform view of peak-detector circuit output.
Fig. 5 is the burst mode optical receiver structural representation of the utility model embodiment based on the burst reception control circuit.
Embodiment
Below with reference to accompanying drawing, the technical scheme of each embodiment of the utility model is carried out to clear, complete description, obviously, described embodiment is only a part of embodiment of the present utility model, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are resulting all other embodiment under the prerequisite of not making creative work, all belong to the scope that the utility model is protected.
Existing burst reception control circuit, adopt ECL d type flip flop and ECL-TTL transducer to generate the control signal of controlling electronic switch, and supply current is large, manufacturing cost is high, makes that burst reception control circuit power consumption is large, cost is high; Further, because burst reception control circuit power consumption is large, caloric value is corresponding increase also, will affect useful life and the job stability of burst mode optical receiver.
In the utility model embodiment, consider to utilize common electronic devices and components to form the burst reception control circuit, reduce the supply current of burst reception control circuit, receive a road differential voltage signal of limiting amplifier output, after being processed, export decision level to and set up circuit, in order to control electronic switch, make that burst reception control circuit cost is lower, power consumption is less, thereby promote useful life and the job stability of burst mode optical receiver.
Fig. 2 is the utility model embodiment reception control circuit structural representation that happens suddenly.Referring to Fig. 2, this burst reception control circuit comprises: TTL d type flip flop 21, signal detection module 22 and inverter 24, and wherein, TTL d type flip flop 21 is connected with signal detection module 22 and inverter 24 respectively, and signal detection module 22 is connected with inverter 24;
In the utility model embodiment, signal detection module receives first voltage differential signal (RD+) of limiting amplifier output, i.e. the first data-signal namely comprises a road voltage differential signal of data message.When the limiting amplifier outputting data signals, data-signal is carried out to filtering, charging, and the magnitude of voltage of the d. c. voltage signal obtained in charging is while being greater than the reference voltage threshold set in advance, detection signal to TTL d type flip flop output high level, then, charging voltage rises to a relative steady state value and keeps.After the data-signal end of transmission, receive the first reseting pulse signal from the output of GPON system, charging voltage is discharged, for the arriving of next data-signal is prepared.
The first reseting pulse signal be an ONU transmission package containing after the light signal of data-signal, another ONU also not transmission package containing the light signal of data-signal, the control signal of GPON system output.The idiographic flow of exporting the first reseting pulse signal about the GPON system is known technology, at this, omits detailed description.
TTL d type flip flop 21, under controlling for the first reseting pulse signal anti-phase, rising edge at the detection signal received, set up circuit output to outside decision level and turn-off control signal, at the trailing edge of the detection signal received, to outside decision level, set up circuit output conducting control signal.
In the utility model embodiment, before burst mode optical receiver receives the light signal that comprises data-signal, TTL d type flip flop output conducting control signal, outside decision level is set up the second electronic switch in circuit in conducting state.
When burst mode optical receiver receives the light signal that comprises data-signal, because the second electronic switch in conducting state is very little, the RC circuit charging constant formed with electric capacity is very little, can the Rapid Establishment decision level, make limiting amplifier to recover data-signal according to the decision level received; Signal detection module in the burst reception control circuit, according to the data-signal of limiting amplifier output, after carrying out filtering, charging, obtain d. c. voltage signal, to the detection signal of TTL d type flip flop output high level, trigger the TTL d type flip flop and turn-off control signal to the second electronic switch output; The second electronic switch receives and turn-offs control signal, carry out and to turn-off and to form new RC circuit, continuation is charged according to the data-signal received, and maintains the stable of decision level signal, makes this charge constant can meet the correct requirement that recovers receiving optical signals medium and low frequency component.
When burst mode optical receiver does not receive the light signal that comprises data-signal, comprise the optical signal transmission of data-signal when complete, the GPON system is according to the configuration of network slot in advance, and signal detection module and inverter in the burst reception control circuit are exported the first reseting pulse signal.Signal detection module receives the first reseting pulse signal, the direct voltage that obtains of charging between the data-signal transmission period discharged, and to the detection signal of TTL d type flip flop output low level.Simultaneously, after inverter carries out anti-phase processing to the first reseting pulse signal of inputting, input to the TTL d type flip flop, the TTL d type flip flop is according to low level detection signal and the first anti-phase reseting pulse signal, to the second electronic switch output conducting control signal, conducting the second electronic switch, the RC circuit that the second electronic switch of conducting and electric capacity form, discharge time constant is very little, can to the charging in electric capacity, be discharged fast, thereby the decision level that resets is set up circuit, with the light signal that next cycle is received, detected.
In practical application, in order to ensure signal detection module, discharge the required time, make signal detection module to restPose, this burst reception control circuit can further include:
Pulse stretching module 23, carry out the broadening processing for the first reseting pulse signal to the output of GPON system, to signal detection module 22 output the second reseting pulse signals (Reset '), so that signal detection module 22 is discharged to charging voltage according to the second reseting pulse signal received.
In the utility model embodiment, between signal detection module and inverter, increase the pulse stretching module, the width of the first reseting pulse signal is carried out to broadening, make the time lengthening of signal detection module electric discharge, realize the abundant electric discharge to charging voltage.
Wherein,
Signal detection module comprises: isolation resistance 221, peak-detector circuit 222, leadage circuit 223 and comparator 224, wherein,
In the utility model embodiment, limiting amplifier receives the signal of telecommunication and the decision level of transimpedance amplifier output and sets up the signal of telecommunication of circuit output, after carrying out amplitude limit, amplification, generate the first data-signal and second data-signal of single spin-echo, it is the two-way voltage differential signal, when exporting to external equipment, and export the first data-signal to isolation resistance 221.
In the utility model embodiment, the first data-signal is the first voltage differential signal (RD+) RD+ signal, and the second data-signal is second voltage differential signal RD-signal, about RD+ signal and RD-signal, is known technology, does not repeat them here.
In practical application, limiting amplifier is also to isolation resistance 221 output the second data-signals.Isolation resistance 221 can be avoided the impact of peak-detector circuit on limiting amplifier output signal integrality.
Peak-detector circuit 222, carry out filtering, charging and maintenance for the first data-signal to receiving, to comparator 224 output dc voltage signals;
In the utility model embodiment, d. c. voltage signal amplitude and first data signal amplitude of peak-detector circuit 222 outputs are close.
Wherein, peak-detector circuit 222 comprises: the first electric capacity 251, the first Schottky diode 252, the second Schottky diode 253 and the second electric capacity 254, wherein,
One end of the first electric capacity 251 is connected with the output of isolation resistance 221, and the other end is connected with the negative pole anodal and the second Schottky diode 253 of the first Schottky diode 252 respectively;
The negative pole of the first Schottky diode 252 is connected with an end of the second electric capacity 254;
The plus earth of the second Schottky diode 253, and be connected with the other end of the second electric capacity 254.
In the utility model embodiment, the first data-signal comprises positive pulse signal and undersuing, when the first data-signal received at the first electric capacity 251 is positive pulse signal, the first Schottky diode 252 conductings, the second Schottky diode 253 cut-offs, the first data-signal, by the first electric capacity 251 and the first Schottky diode 252, is charged to the second electric capacity 254; When the first data-signal is undersuing, the first Schottky diode 252 cut-offs, the second Schottky diode 253 conductings, the first data-signal carries out reverse charging by 253 pairs of the first electric capacity 251 of the second Schottky diode, and an end polarity of the first electric capacity 251 be connected with the negative pole of the second Schottky diode 253 is for just.Like this, at next positive pulse signal, in the cycle, the reverse charging voltage that the first electric capacity 251 forms in the cycle in last undersuing, form forward with the positive pulse signal voltage received and connect, by the first Schottky diode 252, the second electric capacity 254 is charged.
Preferably, peak-detector circuit 222 can further include:
The first inductance 255, one ends are connected with the other end of the first electric capacity 251, and the other end is connected with the negative pole anodal and the second Schottky diode 253 of the first Schottky diode 252 respectively.
In the utility model embodiment, by increasing by the first inductance 255, make this first inductance and the second electric capacity 254 form series resonant circuit, the fundamental frequency that its resonance frequency is lead code in the light signal that comprises data-signal, i.e. 1/2 signal rate.
Fig. 3 is the utility model embodiment during without the first inductance, the voltage waveform view of peak-detector circuit output;
Fig. 4 is the utility model embodiment while having the first inductance, the voltage waveform view of peak-detector circuit output.
Referring to Fig. 3 and Fig. 4, the signal of input peak-detector circuit is the RD+ signal, the voltage (V that the output voltage of peak-detector circuit is the second electric capacity output
c501), in peak-detector circuit, after access the first inductance, the peak-detector circuit output voltage obviously increases, and response speed is also faster.And, due to the frequency-selecting effect of resonant circuit, can suppress the noise jamming occurred in guard time (guard time), avoid circuit erroneous action.
One end of bleeder resistance 256 is connected with an end of the second electric capacity 254 respectively with the first end of the first electronic switch 257, the second end of the other end of bleeder resistance 256 and the first electronic switch 257 is ground connection respectively, and the 3rd end of the first electronic switch 257 is connected with the output of pulse stretching module 23.
In the utility model embodiment, when the 3rd termination of the first electronic switch 257 is received high level signal, the first end of conducting the first electronic switch 257 and the second end, when the 3rd termination of the first electronic switch 257 is received low level signal, turn-off first end and second end of the first electronic switch 257.In practical application, the state commonly used of the first electronic switch 257 is for often opening, and conducting after the high level signal that receives the external equipment input, can make the second electric capacity 254 repid discharges.
The second electric capacity 254, bleeder resistance 256 form discharge loop, and its discharge time constant is relevant to the resistance value of capacitance and the bleeder resistance 256 of the second electric capacity 254.In practical application, timeconstantτ>=10t that bleeder resistance 256 and the second electric capacity 254 form
cID, its effect is to guarantee that the second electric capacity 254 initial condition voltage when receiver powers on is zero.
In-phase input end, for receiving the voltage signal of peak-detector circuit 222 outputs;
Reference voltage input terminal, for accessing reference voltage;
Power end, for the cut-in operation power supply;
Earth terminal, for ground connection;
Output, be greater than for the d. c. voltage signal amplitude in the in-phase input end input reference voltage (V that reference voltage input terminal is inputted
ref) during amplitude, to the detection signal of TTL d type flip flop 21 output high level; When the d. c. voltage signal amplitude of in-phase input end input is less than the reference voltage amplitude of reference voltage input terminal input, to the detection signal of TTL d type flip flop 21 output low levels.
In practical application, comparator the voltage signal received by weak to strong process, near the situation that the magnitude of voltage of the voltage signal that comparator receives fluctuates reference voltage level may appear, to cause the high or low level signal of the frequent output of comparator, make the detection signal of output unstable, thereby affect the processing that the TTL d type flip flop carries out the corresponding data signal.Thereby preferably, comparator can further include: the first resistance 258 and the second resistance 259, wherein,
One end of the first resistance 258 is connected with an end of the second electric capacity 254, and the other end is connected with an end of the second resistance 259 and the in-phase input end of comparator 224 respectively;
The other end of the second resistance 259 is connected with the output of comparator 224.
In the utility model embodiment, the first resistance 258 and the second resistance 259 form the hysteresis circuit, and the second resistance 259 feeds back to the in-phase input end of comparator 224 for the level signal by comparator 224 outputs.Like this, when the second electric capacity 254 starts to be discharged by bleeder resistance 256 or the first electronic switch 257, comparator 224 output high level signals, the impact of returning due to hysteresis, when the voltage on the second electric capacity 254 reaches the first hysteresis voltage set in advance, the high level signal of comparator 224 outputs just can overturn; Similarly, in the process of the second electric capacity 254 chargings, the initial output low level signal of comparator 224, when the voltage on the second electric capacity 254 reaches the second hysteresis voltage set in advance, the low level signal of comparator 224 outputs just can overturn.Thereby avoided the voltage between comparator 224 in-phase input ends and reference voltage input terminal to have less fluctuation, caused the output of comparator 224 that the output vibration caused occurs to change continuously.
Preferably, the value of reference voltage is 1/3 to 1/2 of peak-detector circuit 222 output voltage peak values.
As an example, signal detection module of the present utility model can also comprise the first data-signal duration testing circuit (not shown), determined for the first data-signal sustainable existence time for the first data-signal based on receiving, and, when the first data-signal sustainable existence time arrived, export the first reseting pulse signal.Determining for the first data-signal sustainable existence time about the first data-signal based on receiving is known technology, at this, omits detailed description.
Pulse stretching module 23 comprises: the 3rd resistance 231, the 3rd diode 232 and the 3rd electric capacity 233, wherein,
One end of the 3rd resistance 231 and the positive pole of the 3rd diode 232 receive the first reseting pulse signal, one end of the negative pole of the other end of the 3rd resistance 231, the 3rd diode 232 and the 3rd electric capacity 233 is connected with the 3rd end of the first electronic switch 257, the other end ground connection of the 3rd electric capacity 233.
Data inputs (D) end of TTL d type flip flop is predisposed to high level (VCC) with S-end, reset terminal (R-) receives the first anti-phase reseting pulse signal of inverter 204 outputs, the CP termination is received the detection signal of comparator 224 outputs, and Q-end is set up circuit output break-make control signal to outside decision level.Concrete structure about the TTL d type flip flop is known technology, at this, omits detailed description.
Fig. 5 is the burst mode optical receiver structural representation of the utility model embodiment based on the burst reception control circuit.Referring to Fig. 5, this burst mode optical receiver comprises: transimpedance amplifier 51, decision level are set up circuit 52, burst reception control circuit 53 and limiting amplifier 54, wherein,
Decision level is set up circuit 52, under control for the conducting control signal in 53 outputs of burst reception control circuit, if transimpedance amplifier 51 outputting data signals, carry out filtering, charging, generate the decision level signal, export the second input of limiting amplifier 54 to, if transimpedance amplifier 51 outputting data signals is not discharged to the decision level signal generated; Under the control of the shutoff control signal of exporting at burst reception control circuit 53, carry out filtering, charging, generate the decision level signal, export the second input of limiting amplifier 54 to;
Limiting amplifier 54, for the voltage signal by the first input end input, carry out amplitude limiting processing with the decision level signal of the second input input, outwards export the two-way voltage differential signal, ，Jiang mono-tunnel voltage differential signal exports burst reception control circuit 53 to simultaneously;
In the utility model embodiment, the first input end of limiting amplifier 54 (Di+), receive decision level and set up the voltage signal of the first output output of circuit 52, the second input (Di-) receives the decision level signal that decision level is set up the second output output of circuit 12; The first output of limiting amplifier is exported the first voltage differential signal (RD+), the second output output second voltage differential signal (RD-).
Preferably, limiting amplifier exports the first voltage differential signal (RD+) to the burst reception control circuit.
Burst reception control circuit 53, according to the road voltage differential signal received and from the first reset pulse (Reset) signal of GPON system, processed, set up circuit 52 output control signals to decision level, set up circuit 52 generation decision level signals to control decision level, and, the decision level signal generated is discharged.
In the utility model embodiment, control signal comprises the conducting control signal and turn-offs control signal.
Wherein,
Decision level is set up circuit 52 and is comprised: the 4th resistance (R) 521, the 4th electric capacity (C) 522 and the second electronic switch (SW) 523, wherein,
One end of the 4th resistance 521 is connected with the output of transimpedance amplifier 11 and an end of the second electronic switch 523 respectively, the other end is connected with the other end of the second electronic switch 523, the second input of limiting amplifier 54 and an end of the 4th electric capacity 522 respectively, the other end ground connection of the 4th electric capacity 522, the happened suddenly control signal of reception control circuit 53 output of the break-make of the second electronic switch 523 is controlled.
In Fig. 5, the 4th resistance and the 4th electric capacity form low pass filter, and its timeconstantτ meets:
τ≥10t
CID
In formula,
T
cIDfor the duration of consecutive identical digital code in data-signal (light signal).
Detailed description about the burst reception control circuit, specifically can, referring to Fig. 2, not repeat them here.
In the utility model embodiment, through test, the operating current of burst reception control circuit is about several milliamperes, with respect to the existing operating current that happens suddenly reception control circuit, is about 50～60 milliamperes, greatly reduces operating current.Thereby, effectively reduce the power consumption of burst mode optical receiver; Further, because burst reception control circuit power consumption is little, caloric value is corresponding minimizing also, makes the longer service life of burst mode optical receiver, and job stability is better.And, in the utility model embodiment, the burst reception control circuit formed by TTLD trigger, inverter, pulse stretching module and signal detection module, its cost is about 1 dollar, with respect to the existing burst reception control circuit formed by emitter coupled logic integrated circuit d type flip flop and emitter coupled logic integrated circuit/transistor-transistor logic transducer, its cost is about 3～5 dollars, effectively reduce the cost of burst reception control circuit, be beneficial to the lifting of product batch production and the market competitiveness.
It is example that the burst mode optical receiver of below take sequentially receives the light signal that two ONU send, and the workflow of burst mode optical receiver is described.
The data input pin of TTL d type flip flop (D) is predisposed to high level (VCC), after light signal end from an ONU, the GPON system is according to the configuration of network slot in advance, output first (Reset) pulse signal that resets, export respectively inverter and pulse stretching module to, the one Reset signal, after the inverter paraphase, enters the reset terminal (R-) of TTL d type flip flop; The pulse stretching module receives a Reset signal, when a Reset signal is high level, the 3rd diode current flow, the 3rd electric capacity is charged rapidly, after a Reset signal, during a Reset signal ended, a Reset signal is low level, the 3rd diode cut-off, the 3rd electric capacity, by the 3rd conductive discharge, makes the control signal that exports the first electronic switch to still be maintained high level, triggers the first electronic switch conducting, charging on the second electric capacity is discharged, exported the detection signal of high level to the CP end of TTL d type flip flop.Like this, can extend the ON time of the first electronic switch, make the ON time of the first electronic switch can be greater than a Reset deration of signal, like this, can make the second electric capacity that the grace time electric discharge can be arranged.Be effectively broadening the one Reset deration of signal of stretch circuit, the interference of the light signal that the light signal of the current ONU transmission of avoiding burst mode optical receiver to receive sends next ONU received.Because reset terminal (R-) logic of TTL d type flip flop is Low level effective, the Q of TTLD trigger end is set to 0, Q-end puts 1.High level signal (conducting control signal) to the decision level of Q-end output expression conducting is set up the second electronic switch in circuit, makes decision level set up the second electronic switch SW conducting in circuit, and the 4th electric capacity is discharged.Because the resistance of the second electronic switch SW of conducting is minimum, the time constant of the discharge circuit formed with the 4th electric capacity is also minimum, change decision level and set up the RC time constant of circuit when charging, made the decision level when receiving an ONU that exports limiting amplifier to discharge into rapidly minimumly.That is to say, after an ONU sends the light signal end, under the second reseting pulse signal effect, burst reception control circuit output conducting control signal, make the second electronic switch SW conducting, the 4th electric capacity is discharged, and make the second electronic switch SW keep conducting state always, until the light signal that next ONU sends arrives.With the 4th resistance, compare, (Ron) is minimum for the conducting resistance of the second electronic switch SW.Due to the resistance value of the 4th resistance conduction resistance value much larger than the second electronic switch SW, thereby, the decision level of the light signal that can make corresponding previous ONU send resets rapidly, even the decision level of the light signal that the previous ONU generated sends is discharged rapidly, thereby be that the light signal that receives next ONU transmission is prepared.
After the light signal that comprises data-signal from the 2nd ONU arrives, decision level is set up the second electronic switch in circuit still in conducting state, the second electronic switch and the 4th electric capacity form the RC circuit, light signal is carried out to filtering, charging, generate decision level, because the resistance of the second electronic switch is minimum, decision level is able to Rapid Establishment.Limiting amplifier is according to the decision level outputting data signals RD+ set up, signal detection module detects data-signal RD+, data-signal RD+ is carried out to filtering, charging, obtain d. c. voltage signal, after comparing with the voltage threshold set in advance in comparator, detection (SD) signal of corresponding output high level is to the CP end of TTL d type flip flop.The data input pin of TTL d type flip flop (D) has been placed in high level (VCC), rising edge at the SD signal, the Q end of TTL d type flip flop is set to 1, Q-end is set to 0, the low level shutoff control signal of Q-end output, the second electronic switch SW that decision level is set up in circuit turn-offs, and makes the time constant of the RC circuit (low pass filter) be comprised of the 4th resistance and the 4th electric capacity revert to RC >=10CID.Like this, burst mode optical receiver recovers the normal operating state that receives.
After the light signal that comprises data-signal from the 2nd ONU finishes, the GPON system is exported the first reset pulse (Reset) signal, carries out with the light signal of an ONU and finishes rear identical flow process.
Fig. 6 a～6f is a part of signal output waveform schematic diagram in the utility model embodiment burst mode optical receiver.Referring to Fig. 6 a～6g, the photosignal waveform of the ONU that Fig. 6 a is the burst mode optical receiver reception and the 2nd ONU transmission; The first reseting pulse signal waveform that Fig. 6 b is the output of GPON system; The second reseting pulse signal waveform that Fig. 6 c is the output of pulse stretching module, the period that period shown in arrow is the first electronic switch conducting, with respect to control the conducting of the first electronic switch by the first reseting pulse signal, the ON time of controlling the first electronic switch by the second reseting pulse signal has obtained prolongation; Fig. 6 d is the detection signal waveform of input TTL d type flip flop CP end; The first anti-phase reseting pulse signal waveform that Fig. 6 e is inverter output; Fig. 6 f is that the TTL d type flip flop exports the waveform that decision level is set up the control signal of circuit to, and during low level, decision level is set up the second electronic switch conducting in circuit, and during high level, the second electronic switch that decision level is set up in circuit turn-offs.
Obviously, those skilled in the art can carry out various changes and modification and not break away from spirit and scope of the present utility model the utility model.Like this, if of the present utility model these are revised and within modification belongs to the scope of the utility model claim and equivalent technologies thereof, the utility model also comprises these changes and modification interior.
Claims (13)
1. a burst reception control circuit, is characterized in that, this burst reception control circuit comprises: TTL d type flip flop, signal detection module and inverter, wherein,
Signal detection module, for receiving the first data-signal of limiting amplifier output, carry out filtering, charging and keep processing, obtain d. c. voltage signal, when the magnitude of voltage of the d. c. voltage signal obtained is greater than the reference voltage threshold set in advance, to the detection signal of TTL d type flip flop output high level; When the magnitude of voltage of the d. c. voltage signal obtained is less than the reference voltage threshold set in advance, to the detection signal of TTL d type flip flop output low level; Receive the first reseting pulse signal of GPON system output, charging voltage is discharged;
Inverter, carry out anti-phase processing for the first reseting pulse signal to the output of GPON system, exports the TTL d type flip flop to;
The TTL d type flip flop, under controlling for the first reseting pulse signal anti-phase, rising edge at the detection signal received, set up circuit output to outside decision level and turn-off control signal, at the trailing edge of the detection signal received, to outside decision level, set up circuit output conducting control signal.
2. burst reception control circuit according to claim 1, is characterized in that, further comprises:
The pulse stretching module, carry out the broadening processing for the first reseting pulse signal to the output of GPON system, export the second reseting pulse signal to signal detection module, so that signal detection module is discharged to charging voltage according to the second reseting pulse signal received.
3. burst reception control circuit according to claim 1 and 2, is characterized in that, described signal detection module comprises: isolation resistance, peak-detector circuit, leadage circuit and comparator, wherein,
Isolation resistance, isolated the first data-signal received, and is input to peak-detector circuit;
Peak-detector circuit, carry out filtering, charging and maintenance for the first data-signal to receiving, to comparator output dc voltage signal;
Leadage circuit, after finishing at the first data-signal, receive the first reseting pulse signal of GPON system output, and the voltage signal that peak-detector circuit is exported is discharged;
Comparator, compare for the d. c. voltage signal by reception and the reference voltage set in advance, when the d. c. voltage signal amplitude received is greater than the reference voltage amplitude, to the detection signal of TTL d type flip flop output high level; When the d. c. voltage signal amplitude received is less than the reference voltage amplitude, to the detection signal of TTLD trigger output low level.
4. burst reception control circuit according to claim 3, is characterized in that, described peak-detector circuit comprises: the first electric capacity, the first Schottky diode, the second Schottky diode and the second electric capacity, wherein,
One end of the first electric capacity is connected with the output of isolation resistance, and the other end is connected with the negative pole anodal and the second Schottky diode of the first Schottky diode respectively;
The negative pole of the first Schottky diode is connected with an end of the second electric capacity;
The plus earth of the second Schottky diode, and be connected with the other end of the second electric capacity.
5. burst reception control circuit according to claim 4, is characterized in that, described peak-detector circuit further comprises:
The first inductance, an end is connected with the other end of the first electric capacity, and the other end is connected with the negative pole anodal and the second Schottky diode of the first Schottky diode respectively.
6. burst reception control circuit according to claim 4, is characterized in that, described leadage circuit comprises: bleeder resistance and the first electronic switch, wherein,
One end of bleeder resistance is connected with an end of the second electric capacity respectively with the first end of the first electronic switch, and the second end of the other end of bleeder resistance and the first electronic switch is ground connection respectively, and the 3rd end of the first electronic switch is connected with the output of pulse stretching module.
7. burst reception control circuit according to claim 4, is characterized in that, described comparator comprises: in-phase input end, reference voltage input terminal, power end, earth terminal and output, wherein,
In-phase input end, for receiving the voltage signal of peak-detector circuit output;
Reference voltage input terminal, for accessing reference voltage;
Power end, for the cut-in operation power supply;
Earth terminal, for ground connection;
Output, while being greater than the reference voltage amplitude of reference voltage input terminal input for the d. c. voltage signal amplitude in the in-phase input end input, to the detection signal of TTL d type flip flop output high level; When the d. c. voltage signal amplitude of in-phase input end input is less than the reference voltage amplitude of reference voltage input terminal input, to the detection signal of TTL d type flip flop output low level.
8. burst reception control circuit according to claim 7, is characterized in that, described comparator further comprises: the first resistance and the second resistance, wherein,
One end of the first resistance is connected with an end of the second electric capacity, and the other end is connected with an end of the second resistance and the in-phase input end of comparator respectively;
The other end of the second resistance is connected with the output of comparator.
9. burst reception control circuit according to claim 8, is characterized in that, described pulse stretching module comprises: the 3rd resistance, the 3rd diode and the 3rd electric capacity, wherein,
One end of the 3rd resistance and the positive pole of the 3rd diode receive the first reseting pulse signal, and an end of the negative pole of the other end of the 3rd resistance, the 3rd diode and the 3rd electric capacity is connected with the 3rd end of the first electronic switch, the other end ground connection of the 3rd electric capacity.
10. burst reception control circuit according to claim 9, it is characterized in that, the data input pin of described TTLD trigger and S-end are predisposed to high level, reset terminal receives the first anti-phase reseting pulse signal of inverter output, the CP termination is received the detection signal of comparator output, and Q-end is set up circuit output break-make control signal to outside decision level.
11. the burst mode optical receiver based on the burst reception control circuit, is characterized in that, this burst mode optical receiver comprises: transimpedance amplifier, decision level are set up circuit, burst reception control circuit and limiting amplifier, wherein,
Transimpedance amplifier, for receiving the light signal that comprises data-signal of exterior light transmitter emission, after carrying out opto-electronic conversion and amplifying processing, generate corresponding voltage signal, export respectively the first input end that decision level is set up circuit and limiting amplifier 54 to;
Decision level is set up circuit, under control for the conducting control signal in the output of burst reception control circuit, if transimpedance amplifier outputting data signals, carry out filtering, charging, generate the decision level signal, export the second input of limiting amplifier to, if transimpedance amplifier outputting data signals is not discharged to the decision level signal generated; Under the control of the shutoff control signal of exporting at the burst reception control circuit, carry out filtering, charging, generate the decision level signal, export the second input of limiting amplifier to;
Limiting amplifier, for the voltage signal by the first input end input, carry out amplitude limiting processing with the decision level signal of the second input input, outwards exports the two-way voltage differential signal, and ，Jiang mono-tunnel voltage differential signal exports the burst reception control circuit to simultaneously;
The burst reception control circuit, according to the road voltage differential signal received and from the first reseting pulse signal of GPON system, processed, set up circuit output control signal to decision level, set up circuit evolving decision level signal to control decision level, and, the decision level signal generated is discharged.
12. burst mode optical receiver according to claim 11, is characterized in that, described decision level is set up circuit and is comprised: the 4th resistance, the 4th electric capacity and the second electronic switch, wherein,
One end of the 4th resistance is connected with the output of transimpedance amplifier and an end of the second electronic switch respectively, the other end is connected with the other end of the second electronic switch, the second input of limiting amplifier and an end of the 4th electric capacity respectively, the other end ground connection of the 4th electric capacity, the happened suddenly control signal of reception control circuit output of the break-make of the second electronic switch is controlled.
13. according to the described burst mode optical receiver of claim 11 or 12, it is characterized in that, described burst reception control circuit comprises: TTL d type flip flop, signal detection module and inverter, wherein,
Signal detection module, for receiving the first data-signal of limiting amplifier output, carry out filtering, charging and keep processing, obtain d. c. voltage signal, when the magnitude of voltage of the d. c. voltage signal obtained is greater than the reference voltage threshold set in advance, to the detection signal of TTL d type flip flop output high level; When the magnitude of voltage of the d. c. voltage signal obtained is less than the reference voltage threshold set in advance, to the detection signal of TTL d type flip flop output low level; Receive the first reseting pulse signal of GPON system output, charging voltage is discharged;
Inverter, carry out anti-phase processing for the first reseting pulse signal to the output of GPON system, exports the TTL d type flip flop to;
The TTL d type flip flop, under controlling for the first reseting pulse signal anti-phase, rising edge at the detection signal received, set up circuit output to outside decision level and turn-off control signal, at the trailing edge of the detection signal received, to outside decision level, set up circuit output conducting control signal.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103595473A (en) * | 2013-06-04 | 2014-02-19 | 青岛海信宽带多媒体技术有限公司 | Burst mode reception control circuit and burst mode light receiver |
| WO2016110000A1 (en) * | 2015-01-07 | 2016-07-14 | 中兴通讯股份有限公司 | Adjustment method, device and system for power-down reboot of single plate |
| CN109861761A (en) * | 2019-03-01 | 2019-06-07 | 电子科技大学 | A kind of CMOS high speed optical receiving circuit based on peak value sampling |
| CN113358141A (en) * | 2020-03-06 | 2021-09-07 | 欧姆龙(上海)有限公司 | Photoelectric sensor and signal processing method |
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2013
- 2013-06-04 CN CN201320318247.9U patent/CN203387515U/en not_active Withdrawn - After Issue
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103595473A (en) * | 2013-06-04 | 2014-02-19 | 青岛海信宽带多媒体技术有限公司 | Burst mode reception control circuit and burst mode light receiver |
| CN103595473B (en) * | 2013-06-04 | 2016-06-29 | 青岛海信宽带多媒体技术有限公司 | Burst reception control circuit and burst mode optical receiver |
| WO2016110000A1 (en) * | 2015-01-07 | 2016-07-14 | 中兴通讯股份有限公司 | Adjustment method, device and system for power-down reboot of single plate |
| CN105824381A (en) * | 2015-01-07 | 2016-08-03 | 中兴通讯股份有限公司 | Single board power down restart adjustment method, apparatus and system |
| CN109861761A (en) * | 2019-03-01 | 2019-06-07 | 电子科技大学 | A kind of CMOS high speed optical receiving circuit based on peak value sampling |
| CN109861761B (en) * | 2019-03-01 | 2021-04-23 | 电子科技大学 | CMOS high-speed light receiving circuit based on peak value sampling |
| CN113358141A (en) * | 2020-03-06 | 2021-09-07 | 欧姆龙(上海)有限公司 | Photoelectric sensor and signal processing method |
| CN113358141B (en) * | 2020-03-06 | 2023-05-09 | 欧姆龙(上海)有限公司 | Photoelectric sensor and signal processing method |
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